CN102663977A - 用于驱动发光器件显示器的方法和*** - Google Patents
用于驱动发光器件显示器的方法和*** Download PDFInfo
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Abstract
本发明提供了一种用于驱动发光器件显示器的方法和***。该***提供了增加显示器的准确性的时序表。该***可以提供时序表,通过时序表可以在一组行中连贯地实现工作周期。该***可以提供时序表,通过时序表老化系数被用于多个帧。
Description
本申请是2006年6月8日提交的中国专利申请号为200680026953.9(国际申请号为PCT/CA2006/000941)的题为“用于驱动发光器件显示器的方法和***”的国际申请的分案。
技术领域
本发明涉及显示器技术,具体而言涉及用于驱动发光器件显示器的方法和***。
背景技术
由于与有源液晶显示器相比具有优点,所以最近利用非晶硅(a-Si)、多晶硅、有机或其他驱动底板的主动式矩阵有机发光二极管(active-matrix organic light-emitting diode,AMOLED)已经变得更加吸引人。利用a-Si底板的AMOLED显示器例如具有以下优点:包括低温制造,所述低温制造扩展了不同基板的利用并使得灵活的显示器成为可能,降低了制造成本。此外,OLED产生出具有宽视角的高分辨率显示器。
AMOLED显示器包括像素行和列的阵列,每个都具有以行和列阵列排列的有机发光二极管(OLED)和底板电子仪器。因为OLED是电流驱动设备,所以AMOLED的像素电路应该能够提供精确的和恒定的驱动电流。
图1举例说明了传统的电压程控AMOLED显示器的传统工作周期。在图1中,“行i(i=1,2,3)”表示AMOLED显示器的矩阵像素阵列的第i行。在图1中,“C”表示补偿电压生成周期,在补偿电压生成周期中在像素电路的驱动晶体管的栅极-源极端子两端生成补偿电压,“VT-GEN”表示VT生成周期,在VT生成周期中生成驱动晶体管的阈值电压VT,“P”表示电流稳定周期,在电流稳定周期中通过向驱动晶体管的栅极施加程控的电压的方式来调节像素电流,“D”表示驱动周期,在驱动周期中像素电路的OLED受由驱动晶体管控制的电流驱动。
对AMOLED显示器的每一行而言,工作周期包括补偿电压生成周期“C”、VT生成周期“VT-GEN”、电流稳定周期“P”和驱动周期“D”。一般而言,如图1所示,对于矩阵结构连续执行这些工作周期。例如,对第一行(也就是行1)执行整个程控周期(也就是“C”、“VT-GEN”和“P”),然后对第二行(也就是行2)执行。
然而,因为VT生成周期“VT-GEN”需要大量时间预算来生成驱动TFT的精确阈值电压,所以该时序表(timing schedule)不能用于大面积显示器。此外,执行两个额外的工作周期(也就是“C”和“VT-GEN”)导致大功率的消耗并且还需要额外的控制信号从而导致实施成本较高。
发明内容
本发明的目的在于提供一种消除或缓和现有***的至少一个缺点的方法和***。
根据本发明的一个方面,提供了一种显示器***,其包括:具有以行列方式排列的多个像素电路的像素阵列。像素电路具有发光器件、电容器、开关晶体管和用于驱动发光器件的驱动晶体管。像素电路包括用于程控驱动晶体管的阈值的通路,以及用于生成驱动晶体管的阈值的第二通路。该***包括:用于提供程控数据至像素阵列的第一驱动器;以及用于为一个或多个驱动晶体管控制驱动晶体管的阈值的生成的第二驱动器。第一驱动器和第二驱动器驱动像素阵列以独立地实现程控和生成操作。
根据本发明的另一方面,提供了一种用于驱动显示器***的方法。该显示器***包括:具有以行列方式排列的多个像素电路的像素阵列。像素电路具有发光器件、电容器、开关晶体管和用于驱动发光器件的驱动晶体管。该像素电路包括用于程控驱动晶体管的阈值的通路,以及用于生成驱动晶体管的阈值的第二通路。该方法包括下述步骤:为一个或多个驱动晶体管控制驱动晶体管的阈值的生成,独立于控制步骤提供程控数据至像素阵列。
根据本发明的又一方面,提供了一种显示器***,其包括:包括以行列方式排列的多个像素电路的像素阵列,像素电路具有发光器件、电容器、开关晶体管以及用于驱动发光器件的驱动晶体管。该***包括:第一驱动器,用于提供程控数据至像素阵列;以及第二驱动器,用于生成每一个像素电路的老化系数并将其存储到相应的像素电路中,以及根据所存储的老化系数程控和驱动多个帧的行中的像素电路。像素阵列被分成多个分段。受用于生成老化系数的第二驱动器驱动的至少一个信号线被分段所共用。
根据本发明的又一方面,提供了一种用于驱动显示器***的方法。该显示器***包括:具有以行列方式排列的多个像素电路的像素阵列。像素电路具有发光器件、电容器、开关晶体管和用于驱动发光器件的驱动晶体管。像素阵列被分成多个分段。该方法包括下述步骤:利用分段信号生成每一个像素电路的老化系数并将老化系数存储到每行的对应像素电路中,分段信号被每个分段所共用;以及根据所存储的老化系数程控和驱动多个帧的行中的像素电路。
本发明内容未必描述了本发明的全部特征。
附图说明
参照附图,通过以下的说明,本发明的这些及其他特征将变成更加显而易见,其中:
图1举例说明了传统的AMOLED显示器的传统工作周期;
图2举例说明了根据本发明一个实施例的稳定运行的发光显示器的并行时序表的实例;
图3举例说明了根据本发明一个实施例的稳定运行的发光显示器的并行时序表的实例;
图4举例说明了图2和3的时序表的AMOLED显示器阵列结构的实例;
图5举例说明了电压程控像素电路的实例,其中分段时序表和并行时序表适用于电压程控像素电路。
图6举例说明了应用于图5的像素电路的时序表的实例;
图7举例说明了电压程控像素电路的另一个实例,其中分段时序表和并行时序表适用于该电压程控像素电路;
图8举例说明了应用于图7的像素电路的时序表的实例;
图9举例说明了根据本发明一个实施例的用于发光显示器的共享信令寻址方案(shared signaling addressing scheme)的实例;
图10举例说明了像素电路的实例,其中共享信令寻址方案适用于该像素电路;
图11举例说明了应用于图10的像素电路的时序表的实例;
图12举例说明了图10的像素电路的像素电流稳定性;
图13举例说明了像素电路的另一个实例,其中共享信令寻址方案适用于该像素电路;
图14举例说明了应用于图13的像素电路的时序表的实例;
图15举例说明了用于图10的像素电路的AMOLED显示器阵列结构的实例;
图16举例说明了用于图13的像素电路的AMOLED显示器阵列结构的实例;
图17举例说明了像素电路的又一个实例,其中共享信令寻址方案适用于该像素电路;
图18举例说明了应用于图17的像素电路的时序表的实例;
图19举例说明了用于图17的像素电路的AMOLED显示器阵列结构的实例;
图20举例说明了像素电路的又一个实例,其中共享信令寻址方案适用于该像素电路;
图21举例说明了应用于图20的像素电路的时序表的实例;以及
图22举例说明了用于图20的像素电路的AMOLED显示器阵列结构的实例。
具体实施方式
本发明描述了这样一种实施例,该实施例利用具有发光器件以及多个晶体管的像素电路,所述发光器件诸如有机发光二极管(organiclight emitting diode,OLED)之类,所述晶体管诸如薄膜晶体管(thin filmtransistors,TFT)之类,以行列方式排列来构成AMOLED显示器。像素电路可以包括OLED的像素驱动器。然而,像素可以包括除OLED以外的任何发光器件,像素可以包括除TFT以外的任何晶体管。像素电路中的晶体管可以是N型晶体管、P型晶体管或者其组合。像素中的晶体管可以利用非晶硅、纳米/微米晶体硅、多晶硅(poly silicon)、有机半导体技术(例如有机TFT)、NMOS/PMOS技术或者CMOS技术(例如MOSFET)。在说明书中,“像素电路”和“像素”可以交替使用。像素电路可以是电流程控像素或者电压程控像素,在以下的说明书中,“信号”和“行”可以交替使用。
本发明的实施例涉及用于生成驱动TFT的精确阈值电压的技术。结果,尽管例如由于像素老化以及流程变化的缘故导致像素元件的特征改变,但仍能生成稳定电流。其改善了OLED的亮度稳定性。同时其还减少了功率消耗和信号,从而导致实施成本的降低。
详细描述分段时序表和并行时序表。这些时序表扩展了用于生成驱动晶体管的阈值电压VT的周期的时间预算。如下所述,显示器阵列中的行被分段,工作周期被分成多种类别,例如两种类别。例如,第一种类别包括补偿周期和VT生成周期,而第二种类别包括电流调整周期和驱动周期。对每个分段连续地执行每种类别的工作周期,同时对两个相邻分段执行两种类别。例如,当连续地对第一分段执行电流调整和驱动周期时,对第二分段执行补偿和VT生成周期。
图2举例说明了根据本发明一个实施例的用于稳定工作的发光显示器的分段时序表的实例。在图2中,“行k”(k=1,2,3,...,j,j+1,j+2)表示显示器阵列的第k行,箭头显示了执行方向。
对每一行,图2的时序表包括补偿电压生成周期“C”、VT生成周期“VT-GEN”、电流调整周期“D”以及驱动周期“P”。
图2的时序表在不影响程控时间的情况下扩展VT生成周期“VT-GEN”。为了达到这一点,显示器阵列的行被分类为几个分段,其中图2的分段寻址方案适用于该显示器阵列的行。每个分段因此包括在其中执行VT生成周期的行。在图2中,行1,行2,行3,...,和行j处于显示器阵列多个行的一个分段中。
每个分段的程控开始于执行第一和第二个工作周期“C”以及“VT-GEN”。然后,对整个分段预形成电流校准周期“P”。结果,VT生成周期“VT-GEN”的时间预算延至j.τP,其中j是每个分段中的行数,τP是第一个工作周期“C”(或者电流调整周期)的时间预算。
此外,帧时间τF是Z×n×τP,其中n是显示器中的行数,Z是分段中重复次数的函数。例如,在图2中,VT生成始于分段的第一行并进行到最后一行(第一次重复),然后程控从第一行开始并进行到最后一行(第二次重复)。因此,Z被设置为2。如果重复次数增加,那么帧时间将变成Z×n×τP,其中Z是重复次数并可以大于2。
图3举例说明了根据本发明一个实施例的用于稳定运行的发光显示器的并行时序表的实例。在图3中,“行k”(k=1,2,3,...,j,j+1)表示显示器阵列的第k行。
类似于图2,图4的时序表包括每行的补偿电压生成周期“C”、VT生成周期“VT-GEN”、电流调整周期“P”以及驱动周期“D”。
图3的时序表扩展VT生成周期“VT-GEN”的时间预算,而τP被保存为τF/n,其中τP是第一工作周期“C”的时间预算,τF是帧时间,n是显示器阵列中的行数。在图3中,行1至行j处于显示器阵列多个行的分段中。
根据以上寻址方案,每个分段的电流调整周期“P”并行于下一个分段的第一工作周期“C”被预形成。因此,显示器阵列被设计成能支持并行操作,也就是具有能独立地执行不同周期而不会彼此影响的能力,例如补偿和生成程控的VT以及电流调整。
图4举例说明了用于图2和3的时序表的AMOLED显示器阵列结构的实例。在图4中,SEL[a](a=1,...,m)表示用于选择行的选择信号,CTRL[b](b=1,...,m)表示用于在行的每一个像素处生成驱动TFT的阈值电压的控制信号,VDATA[c](c=1,...,n)表示用于提供程控数据的数据信号。图4的AMOLED显示器10包括多个以行列方式排列的像素电路12,用于控制SEL[a]和CTRL[b]的地址驱动器14以及用于控制VDATA[c]的数据驱动器16。如上所述像素电路12的行(例如,行1,...,行m-h和行m-h+1,...,行m)是分段的。为了并行地实现某些周期,AMOLED显示器10被设计成能支持并行操作。
图5举例说明了像素电路的一个实例,其中分段时序表和并行时序表适用于该像素电路。图5的像素电路50包括OLED52、存储电容器54、驱动TFT56和开关TFT58和60。选择线SELl与开关TFT58的栅极端子相连接。选择线SEL2与开关TFT 60的栅极端子相连接。开关TFT 58的第一端子与数据线VDATA相连接,开关TFT 58的第二端子与驱动TFT 56的栅极端子在结点A1相连接。开关TFT 60的第一端子与结点A1相连接,开关TFT 60的第二端子与接地线相连接。驱动TFT 56的第一端子与可控电源电压VDD相连接,驱动TFT 56的第二端子与OLED52的阳极在结点B1处相连接。存储电容器54的第一端子与结点A1相连接,存储电容器54的第二端子与结点B1相连接。像素电路50可以与分段时序表、并行时序表及其组合一起被利用。
通过晶体管56和60生成VT,同时通过VDATA线由晶体管58执行电流调整。因此,该像素能够实现并行操作。
图6举例说明了应用于像素电路50的时序表的实例。在图7中,“X11”、“X12”、“X13”和“X14”表示工作周期。X11与图2和3的“C”对应,X12与图2和3的“VT-GEN”对应,X13与图2和3的“P”对应,X14与图2和3的“D”对应。
参照图5和6,存储电容器54在第一工作周期X11期间被充电至负电压(-Vcomp),同时驱动TFT 56的栅极电压是零。在第二工作周期X12期间,结点B1被充电至-VT,其中VT是驱动TFT 56的阈值。因为通过开关晶体管60而不是通过开关晶体管58被预执行,所以该周期X12可以被执行但不会影响数据线VDATA,从而可以为其它行执行其他工作周期。在第三工作周期X13期间,结点A1被充电至程控电压VP,导致VGS=VP+VT,其中VGS表示驱动TFT 56的栅极-源极电压。
图7举例说明了像素电路的另一个实例,其中分段时序表和并行时序表适用于该像素电路。图7的像素电路70包括OLED72、存储电容器74和76、驱动TFT78和开关TFT80、82和84。第一选择线SELl与开关TFT80和82的栅极端子相连接。第二选择线SEL2与开关TFT 84的栅极端子相连接。开关TFT 80的第一端子与OLED72的阴极相连接,开关TFT 80的第二端子与驱动TFT 78的栅极端子在结点A2相连接。开关TFT 82的第一端子与结点B2相连接,开关TFT 82的第二端子与接地线相连接。开关TFT 84的第一端子与数据线VDATA相连接,开关TFT 84的第二端子与结点B2相连接。存储电容器74的第一端子与结点A2相连接,存储电容器74的第二端子与结点B2相连接。存储电容器76的第一端子与结点B2相连接,存储电容器76的第二端子与接地线相连接。驱动TFT 78的第一端子与OLED72的阴极相连接,驱动TFT 78的第二端子与接地线相连接。OLED72的阳极与可控电源电压VDD相连接。像素电路70具有采用分段时序表、并行时序表及其组合的能力。
通过晶体管78、80和82生成VT,同时通过VDATA线由晶体管84执行电流调整。因此,该像素能够实现并行操作。
图8举例说明了应用于像素电路70的时序表的实例。在图8中,“X21”、“X22”、“X23”和“X24”表示工作周期。X21与图2和3的“C”对应,X22与图2和3的“VT-GEN”对应,X23与图2和3的“P”对应,X24与图2和3的“D”对应。
参照图7和8,像素电路70采用自引导作用(bootstrapping effect)来将程控电压增加到所存储的VT上,其中VT是驱动TFT 78的阈值电压。在第一工作周期x21期间,结点A2被充入补偿电压VDD-VOLED,其中VOLED是OLED72的电压,节点B2被放电为接地。在第二工作周期X22期间,结点A2的电压被充电至驱动TFT 78的VT。在第三工作周期X23中发生电流调整,其中在第三工作周期X23期间结点B2被充电至程控电压VP以便结点A2被充电至VP+VT。
如上所述分段时序表和并行时序表为像素电路提供了充足的时间以生成驱动TFT的精确阈值电压。结果,尽管像素老化、流程变化或者其组合,但仍生成稳定的电流。工作周期被分段分享以便分段中一行的程控周期与分段中另一行的程控周期相重叠。因此,无论显示器的尺寸多少,它们都可以保持高显示速度。
详细描述共享信令寻址方案。根据共享信令寻址方案,显示器阵列中的行被分成几个分段。像素电路的老化系数(例如驱动TFT的阈值电压、OLED电压)被存储在像素中。所存储的老化系数用于多个帧。生成老化系数所需的一个或多个信号共用于分段中。
例如,对每个分段同时生成驱动TFT的阈值电压VT。然后,分段被执行正常操作。生成阈值电压(例如,图10的VSS)所需的除数据线和选择线之外的所有额外信号共用于每个分段中的行。因为TFT的泄放电流很小,所以利用合理的存储电容器来存储VT会导致不频繁的补偿周期。结果,能量消耗急剧减少。
因为逐段执行VT生成周期,所以分配给VT生成周期的时间被分段中的行数所扩展从而生成更精确的补偿。因为Si:TFT的泄放电流很小(例如,大约10-14),所以所生成的VT可以被存储在电容器中并供几个其他帧使用。结果,在下一个后期补偿帧期间的工作周期被减少为程控和驱动周期。因此,与外部驱动器有关的以及与充电/放电寄生电容有关的功率消耗被在相同的几个帧之间分配。
图9举例说明了根据本发明一个实施例的用于发光显示器的共享信令寻址方案的实例。共享信令寻址方案降低了接口和驱动器的复杂性。
共享信令寻址方案所适用的显示器阵列被分成几个分段,类似于图2和3的那些。在图9中,“行[j,k]”(k=1,2,3,...,h)表示第j个分段中的第k行,“h”是每个分段中的行数,“L”是使用相同的生成VT的帧数。在图9中,“行[j,k]”(k=1,2,3,...,h)处于一个分段中,“行[j-1,k]”(k=1,2,3,...,h)处于另一个分段中。
图9的时序表包括补偿周期“C&VT-GEN”(例如图9的301)、程控周期“P”和驱动周期“D”。除显示器的正常操作以及作为正常操作帧的L-1后期补偿帧周期304之外,补偿间隔300还包括帧生成周期302,以及补偿周期“C&VT-GEN”(例如图9的301),其中在帧生成周期302期间驱动TFT的阈值电压被生成并被存储在像素内部。帧生成周期302包括一个程控周期“P”和一个驱动周期“D”。L-1后期补偿帧周期304包括一组连续的程控周期“P”和驱动周期“D”。
如图9所示,每行的驱动周期开始于前一行的τP延迟,其中是τP是分配给程控周期“P”的时间预算。最后一帧的驱动周期“D”的时间被减少,每一行被减少了i*τP,其中“i”是分段中那个行之前的行数(例如,对[j,h]而言是(h-1))。
因为τP(例如,大约10μs)比帧时间(例如,大约16ms)小很多,所以等待时间的影响是可以忽略的。然而,为了使该影响最小化,每次可以改变程控方向,以便由于等待时间所导致的平均亮度损失变得所有行都相等,或者考虑到在补偿周期前后对帧的程控电压的该影响。例如,在每个VT生成周期(也就是程控从顶端至底部还是从底部至顶端重复)之后程控行的序列可以被改变。
图10举例说明了像素电路的实例,其中共享信令寻址方案适用于所述实例。图10的像素电路90包括OLED92、存储电容器94和96、驱动TFT 98以及开关TFT 100、102和104。像素电路90类似于图7的像素电路70。驱动TFT 98、开关TFT 100以及第一存储电容器94在结点A3相连接。开关TFT 102和104以及第一和第二存储电容器94和96在结点B3相连接。OLED92、驱动TFT 98和开关TFT 100在结点C3相连接。开关TFT102、第二存储电容器96和驱动TFT 98与可控电源电压VSS相连接。
图11举例说明了应用于像素电路90的时序表的实例。在图11中,“X31”、“X32”、“X33”、“X34”和“X35”表示工作周期。X31、X32和X33与补偿周期(例如图9的301)对应,X34与图9的“P”对应,X35与图9的“D”对应。
参照图10和11,像素电路90采用自引导作用(bootstrapping effect)来将程控电压增加至所生成的VT,其中VT是驱动TFT98的阈值电压。补偿周期(例如图9的301)包括前三个周期X31、X32和X33。在第一工作周期X31期间,结点A3被充电至补偿电压VDD-VOLED。第一工作周期X31的时间很小以控制无用发射的影响。在第二工作周期X32期间,VSS上升至高正压V1(例如,V1=20V),因此结点A3被自引导至高压,结点C3上升至V1,导致关闭OLED92。在第三工作周期X33期间,结点A3的电压被通过开关TFT100和驱动TFT98放电,并被降至V2+VT,其中VT是驱动TFT98的阈值电压,V2例如是16V。在电流稳定周期以前,VSS变为零,并且节点A3变为VT。程控电压VPG通过在第四工作周期X34期间自引导的方式被添加至所生成的VT上。电流调整发生在第四工作周期X34,在第四工作周期X34期间结点B3被充电至程控电压VPG(例如,VPG=6V)。因此结点A3处的电压变为VPG+VT,从而生成独立于VT的过载电压。在第五周期X35(驱动周期)期间像素电路的电流变得与VT变换无关。在这里,第一存储电容器94用来存储在VT生成间隔期间的VT。
图12举例说明了图10的像素电路90的像素电流稳定性。在图12中,“ΔVT”表示驱动TFT(例如,图10的98)的阈值电压的变化,“Ipixel误差(%)”表示由ΔVT引起的像素电流的变化。如图12所示,即使在驱动TFT的VT发生2V的变化之后,图10的像素电路90也提供了高度稳定的电流。
图13举例说明了像素电路的另一个实例,其中共享信令寻址方案适用于所述实例。图13的像素电路110类似于图10的像素电路90,然而,其包括两个开关TFT。像素电路110包括OLED112、存储电容器114和116、驱动TFT118和开关TFT120和122。驱动TFT118、开关TFT120和第一存储电容器114在结点A4相连接。开关TFT122以及第一和第二存储电容器114和116在结点B4相连接。OLED112的阴极、驱动TFT118和开关TFT120在结点C4相连接。第二存储电容器116和驱动TFT118与可控电源电压VSS相连接。
图14举例说明了应用于像素电路110的时序表的实例。在图15中,“X41”、“X42”、“X43”、“X44”和“X45”表示工作周期。X41、X42和X43与补偿周期(例如图9的301)对应,X44与图9的“P”对应,X45与图9的“D”对应。
参照图13和14,像素电路110使用自引导作用来将程控电压添加至生成的VT中。补偿周期(例如图9的301)包括前三个周期X41、X42和X43。在第一工作周期X41期间,结点A4被充电至补偿电压VDD-VOLED。第一工作周期X41的时间很小以控制无用发射的影响。在第二工作周期X42期间,VSS上升至高正压V1(例如,V1=20V),因此结点A4被自引导至高压,结点C4也上升至V1,导致断开OLED112。在第三工作周期X43期间,结点A4的电压被通过开关TFT120和驱动TFT118放电,并被降至V2+VT,其中VT是驱动TFT118的阈值电压,V2例如是16V。在电流稳定周期以前,VSS变为零,并且节点A4变为VT。程控电压VPG通过在第四工作周期X44期间自引导的方式被添加至所生成的VT。电流调整发生在第四工作周期X44,在第四工作周期X44期间结点B4被充电至程控电压VPG(例如,VPG=6V)。因此结点A4的电压变为VPG+VT,从而生成独立于VT的过载电压。在第五周期X45(驱动周期)期间像素电路的电流变得与VT变换无关。在这里,第一存储电容器114用来存储在VT生成间隔期间的VT。
图15举例说明了用于图10的像素电路的AMOLED显示器结构的实例。在图15中,GSEL[a](a=1,...,k)与图10的SEL2对应,SELl[b](b=1,...,m)与图10的SELl对应,GVSS[c](c=1,...,k)与图10的VSS对应,VDATA[d](d=1,...,n)与图10的VDATA对应。图15的AMOLED显示器200包括多个以行和列方式排列的像素电路90、用于控制GSEL[a]、SELl[b]和GVSS[c]的地址驱动器204、以及用于控制VDATA[s]的数据驱动器206。像素电路90的行如上所述被分段。在图15中,作为实例显示了分段[1]和分段[k]。
参照图10和15,一个分段中的行的SEL2和VSS信号彼此联通并形成GSEL和GVSS信号。
图16举例说明了用于图14的像素电路的AMOLED显示器结构的实例。在图17中,GSEL[a](a=1,...,k)与图14的SEL2对应,SELl[b](b=1,...,m)与图14的SELl对应,GVSS[c](c=1,...,k)与图14的VSS对应,VDATA[d](d=1,...,n)与图14的VDATA对应。图16的AMOLED显示器210包括多个以行和列的方式排列的像素电路110、用于控制GSEL[a]、SELl[b]和GVSS[c]的地址驱动器214、以及用于控制VDATA[s]的数据驱动器216。像素电路110的行如上所述被分段。在图15中,作为实例显示了分段[1]和分段[k]。
参照图14和16,一个分段中行的SEL2和VSS信号彼此联通并形式GSEL和GVSS信号。
参照图15和16,显示器阵列通过在物理相邻的行之间共享VSS和GSEL信号的方式可以减少它的区域。此外,相同分段中的GVSS和GSEL被合并,并形成分段的GVSS和GSEL线。因此,控制信号被减少。此外,驱动信号的块数也被减少,从而导致功率消耗降低以及实施成本降低。
图17举例说明了像素电路的另一个实例,其中共享信令寻址方案适用于所述实例。图17的像素电路包括OLED132、存储电容器134和136、驱动TFT138、以及开关TFT140、142和144。第一选择线SEL与开关TFT142的栅极端子相连接。第二选择线GSEL与开关TFT144的栅极端子相连接。GCOMP信号线与开关TFT140的栅极端子相连接。开关TFT140的第一端子与结点A5相连接,开关TFT140的第二端子与结点C5相连接。驱动TFT138的第一端子与结点C5相连接,驱动TFT138的第二端子与OLED132的阳极相连接。开关TFT142的第一端子与数据线VDATA相连接,开关TFT 142的第二端子与结点B5相连接。开关TFT144的第一端子与电源电压VDD相连接,开关TFT144的第二端子与结点C5相连接。第一存储电容器134的第一端子与结点A5相连接,第一存储电容器134的第二端子与结点B5相连接。第二存储电容器136的第一端子与结点B5相连接,第二存储电容器136的第二端子与VDD相连接。
图18举例说明了应用于像素电路130的时序表的实例。在图18中,工作周期X51、X52、X53和X54形成帧生成周期(例如图9的302),第二工作周期X53和X54形成后期补偿帧周期(例如,图9的304)。X53和X54是正常工作周期,而其余的是补偿周期。
参照图17和18,像素电路130使用自引导作用以将程控电压添加至生成的VT上,其中VT是驱动TFT 138的阈值电压。补偿周期(例如图9的301)包括开始两个周期X51和X52。在第一工作周期X51期间,结点A5被充电至补偿电压,结点B5被通过开关TFT 142和VDATA充电至VREF。第一工作周期X51的时间很小以控制无用发射的影响。在第二工作周期X52期间,GSEL变为为零,因此其断开开关TFT 144。结点A5处的电压通过开关TFT 140和驱动TFT 138被放电,并下降至VOLED+VT,其中VOLED是OLED 132的电压,VT是驱动TFT 138的阈值电压。在程控周期期间,也就是在第三工作周期X53期间,结点B5被充电至VP+VREF,其中VP是程控电压。因此驱动TFT 138的栅极电压变成VOLED+VT+VP。在这里,第一存储电容器134用来存储补偿间隔期间的VT+VOLED。
图19举例说明了用于图17的像素电路130的AMOLED显示器阵列结构的实例。在图19中,GSEL[a](a=1,...,k)与图17的GSEL对应,SEL[b](b=1,...,m)与图17的SELl对应,GCMP[c](c=1,...,k)与图17的GCOMP对应,VDATA[d](d=1,...,n)与图17的VDATA对应。图19的AMOLED显示器220包括以行和列方式排列的多个像素电路130、用于控制SEL[a]、GSEL[b]和GCOMP[c]的地址驱动器224以及用于控制VDATA[c]的数据驱动器226。如上所述,像素电路130的行被分段(例如,分段[1]和分段[k])。
如图17和19所示,一个分段中的GSEL和GCOMP信号彼此相连接并形成GSEL和GCOMP线。GSEL和GCOMP信号被以分段的形式所共用。此外,相同分段中的GVSS和GSEL被合并,并形成分段的GVSS和GSEL线。因此,控制信号被减少。此外,驱动信号的块数也被减少,导致功率消耗降低以及实施成本降低。
图20举例说明了像素电路的另一个实例,其中共享寻址方案适用于所述实例。图20的像素电路150类似于图17的像素电路130。像素电路150包括OLED152、存储电容器154和156、驱动TFT158、以及开关TFT160、162和164。开关TFT164的栅极端子与可控电源电压VDD相连接,而不是GSEL。驱动TFT158、开关TFT162和第一存储电容器154在结点A6相连接。开关TFT 162以及第一和第二存储电容器154和156在结点B6相连接。驱动TFT158以及开关TFT160和164与结点C6相连接。
图21举例说明了应用于像素电路150的时序表的实例。在图21中,工作周期X61、X62、X63和X64形成帧生成周期(例如图9的302),第二工作周期X63和X64形成后期补偿帧周期(例如图9的304)。
参照图20和21,像素电路150使用自引导作用来将程控电压添加至生成的VT上,其中VT是驱动TFT158的阈值电压。补偿周期(例如图9的301)包括前两个周期X61和X62。在第一工作周期X61期间,结点A6被充电至补偿电压,结点B6被通过开关TFT162和VDATA被充电至VREF。第一工作周期x61的时间很小以控制无用发射的影响。在第二工作周期x62期间,VDD变为零,因此其关掉开关TFT164。结点A6的电压通过开关TFT160和驱动TFT158被放电,并被降为VOLED+VT,其中VOLED是OLED152的电压,VT是驱动TFT158的阈值电压。在程控周期期间,也就是在第三工作周期x63期间,结点B6被充电至VP+VREF,其中VP是程控电压。其已经被识别,因此驱动TFT 158的栅极电压变成VOLED+VT+VP。在这里,第一存储电容器154用来存储补偿间隔期间的VT+VOLED。
图22举例说明了用于图20的像素电路150的AMOLED显示器阵列结构的实例。在图22中,SEL[a](a=1,...,m)与图22的SEL对应,GCMP[b](b=1,...,k)与图22的GCOMP对应,GVDD[c](c=1,...,k)与图22的VDD对应,VDATA[d](d=1,...,k)与图22的VDATA对应。图22的AMOLED显示器230包括以行和列方式排列的多个像素电路150、用于控制SEL[a]、GCOMP[b]和GVDD[c]的地址驱动器234以及用于控制VDATA[c]的数据驱动器236。如上所述像素,电路330的行被分段(例如,分段[1]和分段[k])。
参照图20和22,一个分段中行的VDD和GCOMP信号彼此相连并形成GVDD和GCOMP线。在分段中GVDD和GCOMP信号被共用。此外,相同分段中的GVDD和GCOMP被合并,并形成分段的GVDD和GCOMP线。因此,控制信号被减少。此外,驱动信号的块数也减少,导致功率消耗降低和实施成本降低。
根据本发明的实施例,在分段中共用工作周期以生成驱动TFT的精确的阈值电压。这降低了功率消耗和信号消耗,导致实施成本降低。分段中一行的工作周期与分段中另一行的工作周期相重叠。因此,它们可以保持高的显示速度,而不论显示器的尺寸是多少。
生成的VT的准确性取决于分配给VT生成周期的时间。生成的VT是存储电容和驱动TFT参数的函数,结果,特定失配影响在驱动晶体管的指定阈值电压的存储电容器中的失配相关的生成的VT。VT生成周期时间的增加降低了特定失配对所生成的VT的影响。根据本发明的实施例,在不影响帧频率或者降低行数的情况下分配给VT的时间是可扩展的,因此无论面板的尺寸是多少,其都能够降低不完善的补偿和空间失配影响。
VT生成时间被增加以实现跨越其栅极-源极端子的驱动TFT的阈值电压VT的高精度恢复。结果,面板的均匀性得以改善。此外,寻址方案的像素电路具有在像素老化时提供显著强电流以便补偿OLED亮度减少的能力。
根据本发明的实施例,寻址方案改善了底板稳定性,还对OLED亮度降低进行了补偿。与现有补偿驱动方案相比,功率消耗和实施成本的开销减少了90%以上。
因为共享寻址方案确保了低功率消耗,所以其适合于诸如移动式应用之类的低功率应用。移动式应用可以是但不限于是个人数字助理(Personal Digital Assistants,PDA)、网络电话等。
全部引证文献被结合于此以供参考。
已经参照一个或多个实施例描述了本发明。然而,对所属技术领域的专业人员来说:在不脱离在权利要求中定义的本发明的范围的情况下可以做出多种变化和修改是显而易见的。
Claims (38)
1.一种显示器***,包括:
像素阵列,其包括划分成多个分段的多个像素电路,该多个分段中的每一个包括在该像素阵列的多于一行中的像素电路,每一个像素电路具有发光器件,用于驱动该发光器件以发光的驱动晶体管、电容器、被连接到数据线用于对该像素电路进行编程的第一开关晶体管,以及用于生成该驱动晶体管的阈值电压的第二开关晶体管;以及
驱动器,其用于控制所述多个像素电路的所述第一开关晶体管,以在编程操作中接收数据,并控制所述多个像素电路的所述第二开关晶体管,以在生成阈值电压操作期间生成所述驱动晶体管的所述阈值电压,
其中,所述驱动器被配置成,在该像素阵列的多于一行的多个像素电路中,同时地实现生成阈值电压操作,所述多个像素电路中的每一个在所述多个分段的第一分段中,同时在所述多个分段的第二分段的第二像素电路中实现驱动操作或编程操作。
2.如权利要求1所述的显示器***,其中,所述驱动器被配置成实现对所述第二分段的所述编程操作,同时独立于该编程操作实现对所述第一分段的生成阈值电压操作。
3.如权利要求1所述的显示器***,其中,每一个分段包括多个行,所述编程操作在每一个分段中的多个行中每一行上连续地执行。
4.如权利要求1所述的显示器***,其中,每一个分段包括多个行,所述生成阈值电压操作在每一个分段上连续地执行。
5.如权利要求1所述的显示器***,其中,所述多个像素电路分别被配置成,所述第一开关晶体管的栅极与第一选择线相连接、所述第二开关晶体管的栅极与第二选择线相连接,该第一和第二选择线由所述驱动器来驱动,所述第二开关晶体管的所述第一端与所述驱动晶体管的栅极相连接,该第一开关晶体管的第一端与所述数据线相连接,所述第一开关晶体管的第二端与所述驱动晶体管的所述栅极相连接,所述数据线由所述驱动器驱动,所述电容器被连接在所述驱动晶体管的所述栅极和所述发光器件之间。
6.如权利要求1所述的显示器***,其中,所述多个像素电路分别被配置成,将所述电容器作为第一电容器,所述多个像素电路中的每一个进一步包括第二电容器和第三开关晶体管,并且其中,所述多个像素电路分别被配置成,所述第一开关晶体管的栅极与第一选择线相连接,所述第二和第三开关晶体管的栅极与第二选择线相连接,所述第一和第二选择线由所述驱动器驱动,所述第一开关晶体管的第一端与所述数据线相连接,所述第一开关晶体管的第二端与所述第一和第二电容器相连接,所述第二开关晶体管的第一端与所述第一和第二电容器相连接,所述第三开关晶体管的第一端与所述驱动晶体管和所述发光器件相连接,所述第三开关晶体管的第二端与所述驱动晶体管的栅极相连接,所述第一和第二电容器与所述驱动晶体管的所述栅极串联连接。
7.如权利要求6所述的显示器***,其中,所述第二开关晶体管、所述第三开关晶体管和所述驱动晶体管形成了用于生成所述驱动晶体管的所述阈值电压的电路。
8.如权利要求1所述的显示器***,其中,所述晶体管中的至少一个是利用非晶硅、纳米/微米晶体硅、多晶硅、包括有机晶体管的有机半导体、包括MOSFET的NMOS/PMOS技术或CMOS技术、P型材料,或者N型材料来制造的。
9.如权利要求1所述的显示器***,其中,所述驱动晶体管或所述发光器件与通过所述驱动器控制的可控电压线相连接,以用于在所述生成阈值电压操作的第一阶段期间预充电所述像素电路的所述电容器。
10.如权利要求1所述的显示器***,其中,在每一个像素电路中,所述电容器被连接在所述驱动晶体管的栅极和所述发光器件之间。
11.如权利要求1所述的显示器***,其中所述多个像素电路分别被配置成,将所述电容器作为第一电容器,其具有第一端和第二端,所述第一端与所述驱动晶体管的栅极相连接,所述多个像素电路中的每一个进一步包括第二电容器,其具有与所述第一电容器的所述第二端相连接的第一端,和与电势相连接的第二端,并且其中,所述第一开关晶体管与所述第二电容器的所述第一端和所述第一电容器的第二端相连接。
12.如权利要求1所述的显示器***,其中,所述驱动器被配置成驱动在所述第二分段中的所述第二像素电路以进行发光,同时生成在所述第一分段中的所述多个像素电路的所述阈值电压。
13.一种驱动显示器***的方法,所述显示器***包括像素阵列,其包括被划分成多个分段的多个像素电路,每一个像素电路具有发光器件、用于驱动该发光器件以发光的驱动晶体管、电容器、与用于对所述像素电路进行编程的数据线相连接的第一开关晶体管,以及用于生成所述驱动晶体管的阈值电压的第二开关晶体管,所述方法包括:
控制在像素阵列的多于一行的多个像素电路中的所述第二开关晶体管,所述多个像素电路中的每一个在所述多个分段的第一分段中,以同时地生成在该第一分段中的多个像素电路的所述驱动晶体管的所述阈值电压,而不影响所述数据线,以及
控制在所述多个分段的第二分段中的第二像素电路的第一开关晶体管,以编程该第二像素电路,这独立于控制在所述第一分段中的所述多个像素电路的所述第二开关晶体管。
14.如权利要求13所述的方法,其中,每一个分段包括多个行,对所述第二开关晶体管的控制是对在所述多个分段中的每一个分段连续执行的。
15.如权利要求13所述的方法,
在所述第二分段中执行控制所述第二开关晶体管和控制所述第一开关晶体管之后,随后实现控制所述第二开关晶体管和控制所述第一分段的所述第一开关晶体管。
16.如权利要求13所述的方法,其中,在所述第二分段中执行控制所述第二开关晶体管的同时,在所述第一分段中执行控制所述第二开关晶体管。
17.如权利要求13所述的方法,其中,在执行所述控制所述第二开关晶体管的同时,执行所述控制所述第一开关晶体管,使得对在所述第一分段中的所述多个像素电路的所述阈值电压的生成与对在所述第二分段中的所述第二像素电路的所述编程并行地执行。
18.如权利要求13所述的方法,进一步包括:
执行对在所述第一分段中的多个像素电路的所述晶体管的所述控制的同时,驱动在所述第二分段中的所述第二像素电路以发光,使得对在所述第一分段中的所述多个像素电路的所述阈值电压生成与对在所述第二分段中的所述第二像素电路的所述驱动并行地执行。
19.一种显示器***,包括:
像素阵列,其包括以行和列方式排列的多个像素电路,每个所述像素电路具有发光器件、电容器、用于驱动该发光器件的驱动晶体管、与用于编程所述像素电路的数据线相连接的第一开关晶体管,和用于生成所述驱动晶体管的阈值电压的第二开关晶体管,以及
驱动器,其被配置成操作所述第二开关晶体管,以通过操作在所述像素阵列的第一行中的第一像素电路的所述第二开关晶体管生成所述驱动晶体管的所述阈值电压,同时,通过操作在所述第二像素电路中的所述第一开关晶体管编程在所述像素阵列的第二行中的第二像素电路,其中,所述生成第一像素电路的阈值电压操作具有比所述显示器***的编程时间预算更长的持续时间。
20.如权利要求19所述的显示器***,其中,所述驱动器被进一步配置成,在编程所述第二像素电路之后,通过操作在所述第三像素电路中的第一开关晶体管,编程在所述像素阵列的第三行中的第三像素电路,同时,在所述第一像素电路中执行所述生成阈值电压操作,使得在所述第一像素电路中生成所述阈值电压的同时,对所述第二像素电路和所述第三像素电路两者进行编程。
21.如权利要求19所述的显示器***,其中,所述驱动器被进一步配置成,通过在所述生成阈值电压操作的第一阶段期间预充电所述像素电路,并通过在所述生成阈值电压操作的第二阶段期间充电在所述电容上的所述各个驱动晶体管的所述阈值电压,在所述显示器上生成所述驱动晶体管的所述阈值电压,生成阈值电压操作的所述第二阶段具有比所述第一阶段的持续时间更长的持续时间。
22.如权利要求21所述的显示器***,其进一步包括:可调节电源,用于在所述生成阈值电压操作的所述第一阶段期间,预充电在所述多个像素电路的每一个中的电容器。
23.如权利要求19所述的显示器***,其中,所述第一像素电路和所述第二像素电路共用所述像素阵列的数据线,并且其中,在所述第一个像素电路中执行所述生成阈值电压操作,而不影响所述数据线,使得对所述第二像素电路的所述编程独立于在所述第一像素电路中的所述生成阈值电压操作。
24.如权利要求19所述的显示器***,其中,所述像素阵列被划分成多个分段,其每个包括在所述像素阵列中的所述像素电路的子集,并且其中,在使用显示数据编程第二分段或驱动其发光的同时,所述驱动器被进一步配置成实现在所述多个分段的第一分段中的所述生成阈值电压操作。
25.如权利要求19所述的显示器***,其中,所述多个像素电路被分别配置成,所述第一开关晶体管的栅极与第一选择线相连接,所述第二开关晶体管的栅极与第二选择线相连接,所述第一和第二选择线通过所述驱动器驱动,所述第二开关晶体管的所述第一端与所述驱动晶体管的栅极相连接,所述第一开关晶体管的第一端与所述数据线相连接,所述第一开关晶体管的第二端与所述驱动晶体管的栅极相连接,所述数据线通过所述驱动器驱动,所述电容器被连接在所述驱动晶体管的栅极和所述发光器件之间。
26.如权利要求19所述的显示器***,其中,所述多个像素电路被分别配置成,将所述电容器作为第一电容器,所述多个像素电路中的每一个进一步包括第二电容器和第三开关晶体管,并且其中,所述多个像素电路被分别配置成,所述第一开关晶体管的栅极与第一选择线相连接,所述第二和第三开关晶体管的栅极与第二选择线相连接,所述第一和第二选择线通过所述驱动器驱动,所述第一开关晶体管的第一端与所述数据线相连接,所述第一开关晶体管的第二端与所述第一和第二电容器相连接,所述第二开关晶体管的第一端与第一和第二电容器相连接,所述第三开关晶体管的第一端与所述驱动晶体管和所述发光器件相连接,所述第三开关晶体管的第二端与所述驱动晶体管的栅极相连接,所述第一和第二电容器与所述驱动晶体管的栅极串联连接。
27.一种驱动显示器的方法,所述显示器包括像素阵列,所述像素阵列包括以行列方式排列的多个像素电路,每个所述像素电路具有发光器件、电容器、用于驱动所述发光器件以发光的驱动晶体管、与用于编程所述像素电路的数据线相连接的第一开关晶体管,和用于生成所述驱动晶体管的阈值电压的第二开关晶体管,该方法包括:
通过控制在所述第一像素电路中的第二开关晶体管生成在所述像素阵列的第一行中的第一像素电路的驱动晶体管的阈值电压以生成所述阈值电压,而不影响与所述第一像素电路相关联的数据线;以及
通过控制在所述第二像素电路中的所述第一开关晶体管以经由与所述第一像素电路相关联的所述数据线来编程所述第二像素电路,以编程在所述像素阵列的第二行中的第二像素电路,所述编程是在生成所述第一像素电路的所述阈值电压的同时执行的,并且
其中,生成所述阈值电压具有比所述显示器的编程时间预算更长的持续时间。
28.如权利要求27所述的方法,进一步包括:
通过操作在所述第三像素电路中的第一开关晶体管以经由与所述第一像素电路相关联的所述数据线编程所述第三像素电路,来编程在所述像素阵列的第三行中的第三像素电路,编程所述第三像素电路是在生成所述第一像素电路的所述阈值电压的同时执行的,使得在所述第一像素电路中生成所述阈值电压的同时编程所述第二像素电路和所述第三像素电路。
29.如权利要求27所述的方法,其中,生成所述阈值电压包括:
在第一阶段期间,使用初始电压预充电所述第一像素电路的电容器,以及
在第二阶段期间,通过对经过所述驱动晶体管的所述初始电压进行充电或放电,生成所述电容器上的驱动晶体管的所述阈值电压,并且
其中,所述第二阶段具有比所述显示器的编程时间预算更长的持续时间。
30.如权利要求29所述的方法,其中,所述预充电是通过调节可控电源线的电压执行的。
31.如权利要求27所述的方法,其中,所述像素阵列被划分成多个分段,其分别包括在所述像素阵列中的所述多个像素电路的子集,在所述像素阵列的所述第一行中的所述像素电路被包括在所述多个分段的第一分段中,并且在所述像素阵列的所述第二行中的像素电路被包括在所述多个分段的第二分段中,并且其中,在所述第一分段中的所述像素电路中的所述各个第二开关晶体管由共用的第一全局选择线分别控制,并且在所述第二分段中的所述像素电路中的所述各个第二开关晶体管由共用的第二全局选择线分别控制,并且其中,通过操作所述第一全局选择线执行生成所述第一像素电路的所述阈值电压,以同时地生成在所述第一分段中的所述多个像素电路中的所述各个驱动晶体管的各个阈值电压。
32.如权利要求31所述的方法,进一步包括:
驱动在所述第二分段中的所述多个像素以发光,同时,生成在所述第一分段中的所述多个像素的所述阈值电压同时地执行。
33.一种用于显示器的像素电路,该像素电路包括:
发光器件;
驱动晶体管,其用于通过控制通过所述发光器件的电流驱动所述发光器件;
第一和第二电容器,其串联地耦接在电源线和所述驱动晶体管栅极之间;
第一开关晶体管,其用于通过将数据线耦接到在所述第一和第二电容器之间的节点上来编程所述像素电路;以及
第二开关晶体管,其被耦接到所述驱动晶体管的所述栅极上,以用于生成所述驱动晶体管的阈值电压,其中,依据由多个相似的像素电路共用的全局选择线来操作所述第二开关晶体管,所述多个相似的像素电路依据所述全局选择线,同时地生成在所述多个相似的像素电路中的所述各个驱动晶体管的阈值电压。
34.如权利要求33所述的像素电路,其中,所述第二开关晶体管被耦接到所述驱动晶体管的所述栅极和所述发光器件之间,并且其中,依据第一选择线操作所述第一开关晶体管,并且其中,所述电源线是可控电源线,其被耦接在所述驱动晶体管的第一端,所述驱动晶体管的所述第二端被耦接到所述发光器件上。
35.如权利要求33所述的像素电路,其中,共用所述全局选择线的所述多个像素电路是排列在具有行和列的像素阵列中的相似像素电路的子集,该像素阵列被划分成多个分段,所述多个分段中的每一个包括在所述像素阵列的多于一行中的所述多个相似像素电路的子集,并且其中,在所述多个分段的每一个分段中的所述第二开关晶体管通过由每一个分段中的所述像素电路共用的全局选择线操作。
36.如权利要求33所述的像素电路,其中,所述第二开关晶体管被耦接在所述驱动晶体管的所述栅极和所述驱动晶体管的第一端之间,所述驱动晶体管的所述第二端与所述发光器件相连接,所述像素电路进一步包括:
第三开关晶体管,其被耦接在所述驱动晶体管的所述第一端和电源线之间。
37.如权利要求33所述的像素电路,其中,依据第一选择线操作所述第一开关晶体管。
38.如权利要求37所述的像素电路,其中,共用所述全局选择线以同时生成阈值电压的所述多个相似像素电路包括来自像素阵列的多个行和多个列的像素电路。
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- 2006-06-08 KR KR1020087000382A patent/KR20080032072A/ko not_active Application Discontinuation
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JP6207472B2 (ja) | 2017-10-04 |
US9330598B2 (en) | 2016-05-03 |
CN102663977B (zh) | 2015-11-18 |
US20160217737A1 (en) | 2016-07-28 |
US20110012884A1 (en) | 2011-01-20 |
US10388221B2 (en) | 2019-08-20 |
US20180018919A1 (en) | 2018-01-18 |
EP1904995A1 (en) | 2008-04-02 |
JP2013190829A (ja) | 2013-09-26 |
JP2014194582A (ja) | 2014-10-09 |
WO2006130981A1 (en) | 2006-12-14 |
US8860636B2 (en) | 2014-10-14 |
JP2014240972A (ja) | 2014-12-25 |
JP2008542845A (ja) | 2008-11-27 |
KR20080032072A (ko) | 2008-04-14 |
JP5355080B2 (ja) | 2013-11-27 |
US9805653B2 (en) | 2017-10-31 |
TW200707376A (en) | 2007-02-16 |
US7852298B2 (en) | 2010-12-14 |
EP1904995A4 (en) | 2011-01-05 |
US20140375705A1 (en) | 2014-12-25 |
US20060290614A1 (en) | 2006-12-28 |
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