CA2537173A1 - Low-power low-cost driving scheme for mobile applications - Google Patents
Low-power low-cost driving scheme for mobile applications Download PDFInfo
- Publication number
- CA2537173A1 CA2537173A1 CA002537173A CA2537173A CA2537173A1 CA 2537173 A1 CA2537173 A1 CA 2537173A1 CA 002537173 A CA002537173 A CA 002537173A CA 2537173 A CA2537173 A CA 2537173A CA 2537173 A1 CA2537173 A1 CA 2537173A1
- Authority
- CA
- Canada
- Prior art keywords
- low
- voltage
- node
- mobile applications
- driving scheme
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
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Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
- G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0243—Details of the generation of driving signals
- G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/04—Maintaining the quality of display appearance
- G09G2320/043—Preventing or counteracting the effects of ageing
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
Disclosed is a technique for driving technique to increase the accuracy in the AMOLED
voltage programmed pixel circuits while reducing the cost.
voltage programmed pixel circuits while reducing the cost.
Description
Provisional Application Applicant:
G. Reza Chaji 507-197 Westmount Road North Waterloo, ON, N2L3G5 CANADA
Canadian resident Inventor:
G. Reza Chaji 507-197 Westmount Road North Waterloo, ON, N2L3G5 CANADA
Canadian resident Filing: Canada or USA
BRIEF DESCRIPTION OF THE DRAWINGS
FIG.1 is timing diagrams for AMOLED displays: shared signaling FIG. 2 shows a pixel circuit suitable for the shared signaling addressing scheme.
FIG. 3 shows the pixel current stability.
FIG. 4 shows a pixel circuit suitable for the shared signaling addressing scheme.
FIG. 5 shows array structure for the pixel circuit in FIG.4.
FIG.1 shows the new addressing schedule proposed to reduce the interface and driver complexity. Here, the display is divided into few segments. The threshold voltage of the drive TFT is generated for each segment at the same time. Therefore, all the extra signals required to generate the VT is shared between the rows in each segment. After that these segment is put back on the normal operation. Considering that the leakage current of the TFT is very small, using a reasonable storage capacitor to store the generated VT
results in less frequent VT generation cycle. As a result, the power consumption reduces dramatically.
In this figure, the number of row in each segment is h. and the number of frames that use the same generated VT is 'f. As it is seen, the timing of the driving cycle at the last frame is reduced for each rows by i*iP where 'i' is the number of rows before that row in the segment and ip the timing budget assigned to the programming cycle. To minimize this effect, the sequence of programming the rows can be change after each VT
generation cycle.
The pixel in FIG. 2 employs a bootstrapping effect to add the programming voltage to the generated VT. Here, the VT generation cycles include the first three cycles. During the first operating cycle, node A is charged to a compensation voltage, VDD-VOLED. The timing of the first operating cycle should be very small to control the effect of unwanted emission. During the second operating cycle, VSS goes to a high positive voltage (V 1=
20 V), and so node A is bootstrapped to a high voltage, and also node C goes to V 1(=20 V) turning off the OLED. During the third operating cycle, the voltage at node A is discharged through T2 and T1 and settles to V2+VT where VT is the threshold voltage of TI and V2 is 16 V. VSS goes to zero before the current-regulation cycle, and so node A
goes to VT. The current regulation occurs in the fourth operating cycle during which node B is charged to a programming voltage (VpG= 6 V); thus the voltage at node A
changes to VPG+VT resulting in an overdrive voltage independent of VT. Here, Csl is used to store the VT during the VT_generation interval.
As demonstrated in FIG.3, the pixel circuit provides a highly stable current even after a 2-V shift in the VT of T1.
The pixel in FIG. 4 employs a bootstrapping effect to add the programming voltage to the generated VT. Here, the VT generation cycles include the first three cycles. During the first operating cycle, node A is charged to a compensation voltage, VDD-VOLED. The timing of the first operating cycle should be very small to control the effect of unwanted emission. During the second operating cycle, VSS goes to a high positive voltage (V 1=
20 V), and so node A is bootstrapped to a high voltage, and also node C goes to V 1(=20 V) turning off the OLED. During the third operating cycle, the voltage at node A is discharged through T2 and TI and settles to V2+VT where VT is the threshold voltage of TI and V2 is 16 V. VSS goes to zero before the current-regulation cycle, and so node A
goes to VT. The current regulation occurs in the fourth operating cycle during which node B is charged to a programming voltage (VPG= 6 V); thus the voltage at node A
changes to VPG+VT resulting in an overdrive voltage independent of VT. Here, Csl is used to store the VT during the VT_generation interval.
FIG.5 shows an array structure based on the pixel circuit depicted in FIG.4.
As it is seen, SEL2 and VSS signals of the rows in one segment are connected together and form the GSEL and GVSS signals.
G. Reza Chaji 507-197 Westmount Road North Waterloo, ON, N2L3G5 CANADA
Canadian resident Inventor:
G. Reza Chaji 507-197 Westmount Road North Waterloo, ON, N2L3G5 CANADA
Canadian resident Filing: Canada or USA
BRIEF DESCRIPTION OF THE DRAWINGS
FIG.1 is timing diagrams for AMOLED displays: shared signaling FIG. 2 shows a pixel circuit suitable for the shared signaling addressing scheme.
FIG. 3 shows the pixel current stability.
FIG. 4 shows a pixel circuit suitable for the shared signaling addressing scheme.
FIG. 5 shows array structure for the pixel circuit in FIG.4.
FIG.1 shows the new addressing schedule proposed to reduce the interface and driver complexity. Here, the display is divided into few segments. The threshold voltage of the drive TFT is generated for each segment at the same time. Therefore, all the extra signals required to generate the VT is shared between the rows in each segment. After that these segment is put back on the normal operation. Considering that the leakage current of the TFT is very small, using a reasonable storage capacitor to store the generated VT
results in less frequent VT generation cycle. As a result, the power consumption reduces dramatically.
In this figure, the number of row in each segment is h. and the number of frames that use the same generated VT is 'f. As it is seen, the timing of the driving cycle at the last frame is reduced for each rows by i*iP where 'i' is the number of rows before that row in the segment and ip the timing budget assigned to the programming cycle. To minimize this effect, the sequence of programming the rows can be change after each VT
generation cycle.
The pixel in FIG. 2 employs a bootstrapping effect to add the programming voltage to the generated VT. Here, the VT generation cycles include the first three cycles. During the first operating cycle, node A is charged to a compensation voltage, VDD-VOLED. The timing of the first operating cycle should be very small to control the effect of unwanted emission. During the second operating cycle, VSS goes to a high positive voltage (V 1=
20 V), and so node A is bootstrapped to a high voltage, and also node C goes to V 1(=20 V) turning off the OLED. During the third operating cycle, the voltage at node A is discharged through T2 and T1 and settles to V2+VT where VT is the threshold voltage of TI and V2 is 16 V. VSS goes to zero before the current-regulation cycle, and so node A
goes to VT. The current regulation occurs in the fourth operating cycle during which node B is charged to a programming voltage (VpG= 6 V); thus the voltage at node A
changes to VPG+VT resulting in an overdrive voltage independent of VT. Here, Csl is used to store the VT during the VT_generation interval.
As demonstrated in FIG.3, the pixel circuit provides a highly stable current even after a 2-V shift in the VT of T1.
The pixel in FIG. 4 employs a bootstrapping effect to add the programming voltage to the generated VT. Here, the VT generation cycles include the first three cycles. During the first operating cycle, node A is charged to a compensation voltage, VDD-VOLED. The timing of the first operating cycle should be very small to control the effect of unwanted emission. During the second operating cycle, VSS goes to a high positive voltage (V 1=
20 V), and so node A is bootstrapped to a high voltage, and also node C goes to V 1(=20 V) turning off the OLED. During the third operating cycle, the voltage at node A is discharged through T2 and TI and settles to V2+VT where VT is the threshold voltage of TI and V2 is 16 V. VSS goes to zero before the current-regulation cycle, and so node A
goes to VT. The current regulation occurs in the fourth operating cycle during which node B is charged to a programming voltage (VPG= 6 V); thus the voltage at node A
changes to VPG+VT resulting in an overdrive voltage independent of VT. Here, Csl is used to store the VT during the VT_generation interval.
FIG.5 shows an array structure based on the pixel circuit depicted in FIG.4.
As it is seen, SEL2 and VSS signals of the rows in one segment are connected together and form the GSEL and GVSS signals.
Claims
Priority Applications (17)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA002537173A CA2537173A1 (en) | 2006-02-20 | 2006-02-20 | Low-power low-cost driving scheme for mobile applications |
| KR1020087000382A KR20080032072A (en) | 2005-06-08 | 2006-06-08 | Method and system for driving a light emitting device display |
| CA002549722A CA2549722C (en) | 2005-06-08 | 2006-06-08 | Method and system for driving a light emitting device display |
| EP06752777A EP1904995A4 (en) | 2005-06-08 | 2006-06-08 | Method and system for driving a light emitting device display |
| US11/449,487 US7852298B2 (en) | 2005-06-08 | 2006-06-08 | Method and system for driving a light emitting device display |
| JP2008515013A JP5355080B2 (en) | 2005-06-08 | 2006-06-08 | Method and system for driving a light emitting device display |
| CN2006800269539A CN101228569B (en) | 2005-06-08 | 2006-06-08 | Method and system for driving a light emitting device display |
| TW095120426A TW200707376A (en) | 2005-06-08 | 2006-06-08 | Method and system for driving a light emitting device display |
| PCT/CA2006/000941 WO2006130981A1 (en) | 2005-06-08 | 2006-06-08 | Method and system for driving a light emitting device display |
| CN201210152425.5A CN102663977B (en) | 2005-06-08 | 2006-06-08 | For driving the method and system of light emitting device display |
| US12/893,148 US8860636B2 (en) | 2005-06-08 | 2010-09-29 | Method and system for driving a light emitting device display |
| JP2013138321A JP2013190829A (en) | 2005-06-08 | 2013-07-01 | Method and system for driving light emitting device display |
| JP2014133475A JP6207472B2 (en) | 2005-06-08 | 2014-06-30 | Method and system for driving a light emitting device display |
| JP2014154749A JP2014240972A (en) | 2005-06-08 | 2014-07-30 | Method and system for driving light emitting device display |
| US14/481,370 US9330598B2 (en) | 2005-06-08 | 2014-09-09 | Method and system for driving a light emitting device display |
| US15/090,769 US9805653B2 (en) | 2005-06-08 | 2016-04-05 | Method and system for driving a light emitting device display |
| US15/717,043 US10388221B2 (en) | 2005-06-08 | 2017-09-27 | Method and system for driving a light emitting device display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA002537173A CA2537173A1 (en) | 2006-02-20 | 2006-02-20 | Low-power low-cost driving scheme for mobile applications |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2537173A1 true CA2537173A1 (en) | 2007-08-20 |
Family
ID=38433792
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002537173A Abandoned CA2537173A1 (en) | 2005-06-08 | 2006-02-20 | Low-power low-cost driving scheme for mobile applications |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA2537173A1 (en) |
-
2006
- 2006-02-20 CA CA002537173A patent/CA2537173A1/en not_active Abandoned
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FZDE | Dead |