CA2508972A1 - New timing schedule for stable operation of amoled displays - Google Patents

Abstract

Disclosed is a technique for driving technique to increase the accuracy in the AMOLED
voltage programmed pixel circuits.

Description

FIELD OF THE INVENTION
The present invention generally relates to a light emitting device display, and more particularly, to a driving technique of the active matrix organic light emitting diode (AMOLED), and the enhancement of OLED brightness stability by using compensation.
SUMMARY OF INVENTION
The invention provides the enough time for the pixel circuit to generate an accurate threshold voltage of the drive TFT. As a result, it generate a very stable current despite the pixel aging BRIEF DESCRIPTION OF THE DRAWINGS
FIG.1 is timing diagrams for AMOLED displays: (a) conventional, (b) segmented, and (c) parallel.
FIG. 2 shows two VPPCs based on segmented and parallel scheduling: (a) 3-TFT
circuit and (b) bootstrapped circuit.

For the voltage-programmed AMOLED display, the operating cycles are the compensation voltage generation, VT-generation, current-regulation, and driving cycles.
Typically, these operating cycles are performed sequentially for a matrix structure, as indicated in FIG.1 (a). For example, the entire programming cycles of the first row are executed, and then the second row is programmed. Since the VT-generation cycle requires a large timing budget to generate an accurate VT, this timing schedule cannot be adopted in large-area displays.
FIG.1 (b) is the new timing schedule that extends the timing budget of the VT-generation cycle without affecting the programming time. To achieve that, the rows in the AMOLED are categorized as few segments. The programming of each segment starts with executing the first and second operating cycles. After that, the current-calibration cycle is preformed for the entire segment. As a result, the timing budget of the VT-generation cycle is extended to j.iP where j is the number of rows in each segment, and iP
is the timing budget of the first operating cycle. Also, the frame time (iF) is 2n.iP where n is the number of rows in the display. As a result, iP is twice as small as the one in the conventional 2-TFT matrix. Also, this timing schedule cannot be applied to the new 2-TFT pixel without a few modifications.
The other timing schedule, displayed in FIG.1 (c), extends the timing budget of the VT-generation cycle, whereas iP is preserved as iF/n. The current-regulation cycle of each segment is preformed in parallel with the first operating cycles of the next segment.
However, the pixel circuit must be able to support the parallel operation.
FIG. 2 shows the modified pixel circuits that can support the new timing schedules.
In the circuit in FIG.2 (a), storage capacitor is charge to a negative voltage (-V~omp) during the first operating cycle while the gate voltage is zero. During the second operating cycle node B is charge up to -VT. It is obvious that this cycle can be done without affecting the data line, so that the other operating cycle can be executed for the other rows. During the third operating cycle, node A is charged to a programming voltage resulting in VGS=VP+VT. It is evident that this pixel can be used with both the segmented and parallel timing schedule.

The pixel in FIG.2 (b), however, employs bootstrapping effect to add a programming voltage to the stored VT. During the first operating cycle, node A is charged to a compensating voltage, VDp-VOLED~ and node B is discharged to ground. During the second operating cycle, voltage at node A changes to the VT of T1. The current regulation occurs in the third operating cycle during which node B is charge to a programming voltage so that node A changes to Vp+VT. It is obvious that this pixel circuit has the capability of adopting both segmented and parallel timing schedule.

Claims