CA2542678A1 - Amoled display for mobile applications - Google Patents

Abstract

Disclosed is a technique to increase the accuracy in the AMOLED voltage programmed pixel circuits while reducing the cost.

Description

FIELD OF THE INVENTION

The present invention generally relates to a light emitting device display, and more particularly, to a driving technique of the active matrix organic light emitting diode (AMOLED), and the enhancement of OLED brightness stability by using compensation.

SUMMARY OF INVENTION

The invention shares the operating cycles to generate an accurate threshold voltage of the drive TFT
and reduce the power consumption and signals, resulting in lower impleinentation cost.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG.1 is timing diagrams for AMOLED displays: interleaved addressing scheme FIG. 2 shows a pixel circuit suitable for the interleaved addressing scheme.
FIG. 3 array structure for the pixel circuit in FIG. 2.
FIG. 4 shows a pixel circuit suitable for the interleaved addressing scheme.
FIG. 5 array structure for the pixel circuit in FIG. 4.

FIG.1 shows the new addressing schedule proposed to reduce the interface and driver complexity.
Here, the display is divided into few segments. The threshold voltage of the drive TFT is generated for each segment at the same time. Therefore, all the extra signals required to generate the VT is shared between the rows in each segment. After that these segment is put on the normal operation.
Considering that the leakage current of the TFT is small, using a reasonable storage capacitor to store the VT results in less frequent VT generation cycle. As a result, the power consumption reduces dramatically.
In this figure, the number of row in each segment is h. and the number of frames that use the same generated VT is T. As it is seen, the timing of the driving cycle at the last frame is reduced for each rows by i*iP where 'i' is the number of rows before that row in the segment and tiP the timing budget assigned to the programming cycle. To minimize this effect, the sequence of programming the rows can be change after each VT generation cycle.

The pixel in FIG. 2 employs a bootstrapping effect to add the programming voltage to the generated VT. Here, the VT generation cycles include the first two cycles.
During the first operating cycle, node A is charged to a compensation voltage and node B is charged to VREF through T3 and VDATA. The timing of the first operating cycle should be very small to control the effect of unwanted emission. During the second operating cycle, GSEL goes to zero and so T4 is OFF, and so the voltage at node A is discharged through T2 and Tl and settles to VOLED+VT where VT is the threshold voltage of Tl and VOLED is the OLED Voltage. During the programming cycle, third operating cycle, node B
is charged to VP+VREF where VP is a programming voltage and so the gate voltage of T1 becomes VOLED+VT+VP. Here, Csl is used to store the VT +VOLED during the compensation interval.

FIG.3 shows an array structure based on the pixel circuit depicted in FIG.2.
As it is seen, GSEL
and GCMP signals of the rows in one segment are connected together and form the GSEL and GCMP
lines.
The pixel in FIG. 4 employs a bootstrapping effect to add the programming voltage to the generated VT. Here, the VT generation cycles include the first two cycles.
During the first operating cycle, node A is charged to a compensation voltage and node B is charged to VREF through T3 and VDATA. The timing of the first operating cycle should be very small to control the effect of unwanted emission. During the second operating cycle, VDD goes to zero and so T4 is OFF. Thus, the voltage at node A is discharged through T2 and T1 and settles to VOLED+VT where VT is the threshold voltage of Ti and VOLED is the OLED Voltage. During the programming cycle, third operating cycle, node B is charged to VP+VREF where VP is a programming voltage and so the gate voltage of Tl becomes VOLED+'VT+Vp. Here, Cs, is used to store the VT +VoLED during the compensation interval.

FIG.5 shows an array structure based on the pixel circuit depicted in FIG.4.
As it is seen, VDD
and GCMP signals of the rows in one segment are connected together and form the GVDD and GCMP
lines.

Claims