JP2015207736A - 半導体装置の製造方法、半導体装置の評価方法および半導体装置 - Google Patents
半導体装置の製造方法、半導体装置の評価方法および半導体装置 Download PDFInfo
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Abstract
【解決手段】まず、n-型半導体基板1のおもて面に、素子の深さ方向に延びるゲート電極8を備えたトレンチMOSセルと、素子の深さ方向に延びるダミーゲート電極18を備えたダミートレンチMOSセルと、を形成する。次に、n-型半導体基板1のおもて面上に、エミッタ電極9およびスクリーニングパッドDGを形成する。スクリーニングパッドDGには、ダミーゲート電極18が接続される。次に、エミッタ電極9とスクリーニングパッドDGとの間に所定電圧を印加して、ダミーゲート絶縁膜17に対するスクリーニングを行う。次に、エミッタ電極9およびスクリーニングパッドDGを覆うめっき膜13により、エミッタ電極9とスクリーニングパッドDGとを短絡することで、製品が完成する。
【選択図】図1
Description
まず、実施の形態1にかかる半導体装置の製造方法により作製(製造)される半導体装置の一例としてトレンチゲート型IGBTの構造について説明する。図1は、実施の形態1にかかる半導体装置の製造方法により製造される半導体装置の一例を示す断面図である。図1(a)には、製造途中のスクリーニング時の状態を模式的に示す。図1(b)には、組立後の状態を模式的に示す。図1に示すように、実施の形態1にかかる半導体装置は、n-型ドリフト層となるn-型半導体基板(半導体チップ)1上に、トレンチ6側壁をチャネル領域(反転層)とするトレンチMOSセル(第1トレンチゲート構造)と、トレンチ(以下、ダミートレンチとする)16側壁にチャネル領域を形成しないトレンチMOSセル(以下、ダミートレンチMOSセル(第2トレンチゲート構造)とする)と、を備える。
次に、実施の形態2にかかる半導体装置の製造方法によって作製される半導体装置の構造について説明する。図6は、実施の形態2にかかる半導体装置の各電極パッドの平面レイアウトを示す平面図である。図6の切断線A−A’における断面構造は、実施の形態1(図4)と同様である。図7は、実施の形態2にかかる半導体装置の各電極パッドの別の一例の平面レイアウトを示す平面図である。図8は、図6のスクリーニングパッド付近を拡大して示す平面図である。実施の形態2にかかる半導体装置の製造方法によって作製される半導体装置が実施の形態1にかかる半導体装置の製造方法によって作製される半導体装置と異なる点は、スクリーニングパッドDGの周囲2辺以上がエミッタ電極9に対向する点である。
次に、実施の形態3にかかる半導体装置の製造方法について説明する。図9は、実施の形態3にかかる半導体装置の製造方法の概要を示すフローチャートである。図10は、実施の形態3にかかる半導体装置の各電極パッドの平面レイアウトを示す平面図である。実施の形態3にかかる半導体装置の製造方法が実施の形態1にかかる半導体装置の製造方法と異なる点は、次の2点である。1つ目の相違点は、ゲート絶縁膜7およびダミーゲート絶縁膜17に対するスクリーニングをウエハ検査時に行う点である。2つ目の相違点は、組立工程におけるワイヤーボンディングにより、エミッタ電極9とスクリーニングパッドDGとを短絡させる点である。
次に、実施の形態4にかかる半導体装置の製造方法について説明する。図11は、実施の形態4にかかる半導体装置の製造方法の概要を示すフローチャートである。図12は、実施の形態4にかかる半導体装置の各電極パッドの平面レイアウトを示す平面図である。図13は、図12の切断線B−B’における断面構造を示す断面図である。実施の形態4にかかる半導体装置の製造方法が実施の形態3にかかる半導体装置の製造方法と異なる点は、組立工程における銅ブロック19へのチップおもて面の半田付けにより、エミッタ電極9とスクリーニングパッドDGとを短絡させる点である。
次に、実施の形態5にかかる半導体装置の製造方法について、図5を参照しながら説明する。実施の形態5にかかる半導体装置の製造方法が実施の形態1にかかる半導体装置の製造方法と異なる点は、一旦、すべてのトレンチゲート構造をトレンチMOSセルとして形成し(すなわち、n-型半導体基板に形成したすべてのトレンチゲート構造をすべてゲート電極8としてゲートランナーに接続し)、すべてのゲート絶縁膜7を一括してスクリーニングした後に、ゲートランナーに接続された一部のゲート電極8を電気的に切り離してダミーゲート電極18にする点である。
1a 活性領域
1b エッジ終端領域
2 p型ベース層
3 第1ベース領域
4 第2ベース領域
5 n+型エミッタ領域
6 トレンチ
7 ゲート絶縁膜
8 ゲート電極
9 エミッタ電極
10 層間絶縁膜
11 p+型コレクタ層
12 コレクタ電極
13 めっき膜
14 おもて面保護膜
14a おもて面保護膜の内終端
15 半田層
16 ダミートレンチ
17 ダミーゲート絶縁膜
18 ダミーゲート電極
19 銅ブロック
DG スクリーニングパッド
E エミッタパッド
G ゲートパッド
w エミッタ電極とスクリーニングパッドとの間隔
Claims (9)
- 素子の深さ方向に延びるゲート電極を備えたトレンチゲート構造を複数備え、複数の前記トレンチゲート構造が、素子の制御に寄与する第1トレンチゲート構造と、素子の制御に寄与しない第2トレンチゲート構造とからなる半導体装置の製造方法であって、
半導体基板のおもて面側に、複数の前記トレンチゲート構造を形成する第1工程と、
前記半導体基板のおもて面上に、複数の前記トレンチゲート構造のうち、1つ以上の前記トレンチゲート構造の前記ゲート電極が接続された電極パッドを形成する第2工程と、
ゲート電位以外の電位をもつ電極部と前記電極パッドとの間に所定電圧を印加して、前記電極パッドに接続された前記ゲート電極に接するゲート絶縁膜に前記所定電圧を印加するスクリーニングを行う第3工程と、
前記第3工程後、前記電極部と前記電極パッドとを短絡させて、前記電極パッドに接続された前記ゲート電極を備えた前記第2トレンチゲート構造を形成する第4工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記第2工程では、同一の配線によってすべての前記トレンチゲート構造の前記ゲート電極が接続された前記電極パッドを形成し、
前記第3工程後、前記第4工程前に、前記配線から一部の前記ゲート電極を電気的に切り離し、前記切り離された前記ゲート電極を前記電極パッドとは異なる電極パッドに接続し、
前記第4工程では、前記電極部と、前記切り離された前記ゲート電極が接続された前記電極パッドとを短絡させて、前記切り離された前記ゲート電極を備えた前記第2トレンチゲート構造を形成することを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記第4工程では、
前記電極部、および前記第2トレンチゲート構造の前記ゲート電極が接続された前記電極パッドを覆うめっき膜を形成し、
前記電極部と、前記第2トレンチゲート構造の前記ゲート電極が接続された前記電極パッドとの間に広がった前記めっき膜を介して、前記電極部と、前記第2トレンチゲート構造の前記ゲート電極が接続された前記電極パッドとを接続することを特徴とする請求項1または2に記載の半導体装置の製造方法。 - 前記第4工程は、
前記電極部の表面、および前記第2トレンチゲート構造の前記ゲート電極が接続された前記電極パッドの表面にめっき膜を形成する工程と、
前記めっき膜を介して前記電極部、および前記第2トレンチゲート構造の前記ゲート電極が接続された前記電極パッドに電極端子となる電極層を半田付けする工程と、を含み、
前記電極部と、前記第2トレンチゲート構造の前記ゲート電極が接続された前記電極パッドとの間に広がった半田層によって、前記電極部と、前記第2トレンチゲート構造の前記ゲート電極が接続された前記電極パッドとを接続することを特徴とする請求項1または2に記載の半導体装置の製造方法。 - 前記第4工程では、前記電極部と前記第1トレンチゲート構造の前記ゲート電極とにそれぞれワイヤーボンディングによる配線処理を行うとともに、ワイヤーボンディングにより前記電極部と、前記第2トレンチゲート構造の前記ゲート電極が接続された前記電極パッドとを接続することを特徴とする請求項1または2に記載の半導体装置の製造方法。
- 前記第3工程後、前記第4工程前に、前記電極部と前記第1トレンチゲート構造の前記ゲート電極とにそれぞれワイヤーボンディングによる配線処理を行い、
前記第4工程では、前記第2トレンチゲート構造の前記ゲート電極が接続された前記電極パッドを外部回路に設けられた前記電極部に接続することを特徴とする請求項1または2に記載の半導体装置の製造方法。 - 前記電極部は、前記半導体基板の、前記トレンチゲート構造のトレンチに沿った部分に電気的に接続されたエミッタ電極であることを特徴とする請求項1〜6のいずれか一つに記載の半導体装置の製造方法。
- 請求項1〜7のいずれか一つに記載の半導体装置の製造方法によって製造されてなる半導体装置。
- 素子の深さ方向に延びるゲート電極を備えたトレンチゲート構造を複数備え、複数の前記トレンチゲート構造が、素子の制御に寄与する第1トレンチゲート構造と、素子の制御に寄与しない第2トレンチゲート構造とからなる半導体装置の評価方法であって、
半導体基板のおもて面側に形成された複数の前記トレンチゲート構造のうち、1つ以上の前記トレンチゲート構造の前記ゲート電極が接続された電極パッドをゲート電位以外の電位をもつ電極部に短絡させて、前記電極パッドに接続された前記ゲート電極を備えた前記第2トレンチゲート構造を形成する前に、
前記電極部と前記電極パッドとの間に所定電圧を印加して、前記電極パッドに接続された前記ゲート電極に接するゲート絶縁膜に前記所定電圧を印加するスクリーニングを行うことを特徴とする半導体装置の評価方法。
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US9761663B2 (en) | 2017-09-12 |
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US9437678B2 (en) | 2016-09-06 |
US20160336403A1 (en) | 2016-11-17 |
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US20150311285A1 (en) | 2015-10-29 |
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