CN113054009B - 一种沟槽igbt芯片 - Google Patents

一种沟槽igbt芯片 Download PDF

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CN113054009B
CN113054009B CN201911374310.9A CN201911374310A CN113054009B CN 113054009 B CN113054009 B CN 113054009B CN 201911374310 A CN201911374310 A CN 201911374310A CN 113054009 B CN113054009 B CN 113054009B
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CN113054009A (zh
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宁旭斌
谭真华
李迪
肖海波
肖强
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Zhuzhou CRRC Times Semiconductor Co Ltd
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Abstract

本申请提供了一种沟槽IGBT芯片，包括N‑型漂移层；多个并联的元胞，元胞包括两个设置于N‑型漂移层上表面的第一沟槽内的主栅极，两个主栅极沿N‑型漂移层的表面延伸且平行分布；虚栅极，位于元胞之间并设置于N‑型漂移层上表面的第二沟槽内，虚栅极平行于主栅极；虚栅极通过虚栅主线引出电位，主栅极和虚栅极之间的第一虚栅P阱或者两个虚栅P阱之间的第二虚栅P阱中的虚栅P+接触区通过虚栅P阱主线引出电位。利用该沟槽IGBT芯片，通过引出虚栅以及虚栅P阱，使其分别能够施加不同的电位，避免了虚栅和P阱浮空时因Cgc较大产生的位移电流导致关断瞬间Vge抬升而减小了器件关断能力，在不降低性能的情况下有效地避免了开关过程中的电压或电流过冲。

Description

一种沟槽IGBT芯片
技术领域
本发明涉及半导体器件技术领域，并且更具体地，涉及一种沟槽IGBT芯片。
背景技术
绝缘栅双极晶体管(Insulated Gate Bipolar Transistor，简称“IGBT”)结合了MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor,简称“MOSFET”)输入阻抗高、栅极驱动简单和双极结型晶体管(Bipolar Junction Transistor，简称“BJT”)导通压降小、工作电流大等优点，广泛应用于工业控制、电动汽车、轨道交通、智能电网和变频家电等领域。
沟槽IGBT导通时电流密度大，会降低抗短路能力，因此需要合理设计有源区分布来提升器件的抗短路能力，从而保证芯片的安全工作区。通常采用虚栅或浮空P阱技术来抑制横向电场扩展，避免出现横向的电压峰值导致IGBT阻断耐压降低，因此存在虚栅和非有效沟道区的P阱区域。目前虚栅结构通常采用电学短路方式，将虚栅与发射极连接，或者虚栅与栅极连接，或者虚栅与终端区的场限环连接，或者虚栅浮空。目前这些方式存在开关损耗增加、浪涌电压变大、耐压降低等问题。虚栅与主栅以及虚栅之间存在的P阱与主栅之间的P阱功能不同，一般将虚栅P阱浮空或者接地。当P阱浮空时，因米勒电容Cgc大，可能会在关断时产生位移电流，引起Vge电位提升，使器件关断能力恶化；而当P阱接地时，栅极G和发射极E之间的电容变大，米勒电容Cgc减小和Cge增大，使得关断位移电流减小，但芯片开通过程的延迟增加，开通过程di/dt的可控性变差。
发明内容
针对上述现有技术中的问题，本申请提出了一种新型的沟槽IGBT芯片，通过引出虚栅以及虚栅P阱，使其分别能够施加不同的电位，在不降低性能的情况下有效地避免了开关过程中的电压或电流过冲，并且实现了定量调节IGBT开通过程中的电流上升速率，根据应用调整提高抗电磁干扰能力。
本申请提供的沟槽IGBT芯片，包括N-型漂移层；多个并联的元胞，所述元胞包括两个设置于所述N-型漂移层上表面向下蚀刻而成的第一沟槽内的主栅极，两个所述主栅极沿所述N-型漂移层的表面延伸且平行分布；虚栅极，所述虚栅极位于元胞之间并设置于所述N-型漂移层上表面向下蚀刻而成的第二沟槽内，所述虚栅极平行于所述主栅极；其中，所述虚栅极通过虚栅主线引出电位，所述主栅极和所述虚栅极之间的第一虚栅P阱或者两个所述虚栅P阱之间的第二虚栅P阱中设置的虚栅P+接触区通过虚栅P阱主线引出电位。利用该沟槽IGBT芯片，通过引出虚栅以及虚栅P阱，使其分别能够施加不同的电位，避免了虚栅和P阱浮空时因Cgc较大产生的位移电流导致关断瞬间Vge抬升而减小了器件关断能力，在不降低性能的情况下有效地避免了开关过程中的电压或电流过冲。
在一个实施方式中，所述虚栅主线与元胞区的发射极或栅极连接，所述虚栅P阱主线与元胞区的发射极或栅极连接。
在一个实施方式中，包括多个所述虚栅极，其中，所述第一虚栅P阱引出电位时，所述第二虚栅P阱浮空，或者所述第二虚栅P阱引出电位时，所述第一虚栅P阱浮空。
在一个实施方式中，所述虚栅P+接触区通过金属电极连接、多晶电阻与虚栅P阱主线连接。
在一个实施方式中，所述多晶电阻与芯片表面之间设置有隔离氧化层。通过该实施方式，多晶电阻沿着沟槽方向，即使多晶电阻上存在电位，也不会对元胞区域产生影响
在一个实施方式中，所述隔离氧化层的厚度为1000A-1300A。
在一个实施方式中，包括至少两个虚栅极，且相邻虚栅极之间设置有多个横向沟槽，其垂直于所述所述虚栅极的长度方向，以将虚栅P阱分割为交替排列的多个虚栅有源区和多个虚栅陪区，所述虚栅有源区的虚栅P阱中设置所述虚栅P+接触区，所述虚栅陪区的虚栅P阱浮空。通过该实施方式，这样可以设计不同数目的接电位的P阱，来实现虚栅P阱面积的调整，实现根据应用要求定量调整电流上升速率，提升***的抗电磁干扰能力，增强器件与***的电磁兼容性。
在一个实施方式中，所述元胞为六角形元胞结构，并且多个所述元胞以蜂窝状分布在所述N-型漂移层上；或者，所述元胞为方形元胞结构，并且多个所述元胞矩阵式地分布在所述N-型漂移层上；或者，所述元胞为条形元胞结构，并且多个所述元胞并排地分布在所述N-型漂移层上。
在一个实施方式中，所述N型漂移层下方还包括穿通型结构、软穿通型结构或非穿通型结构。
在一个实施方式中，所述两个主栅极之间的主栅极P阱包括主栅P+接触区以及设置于所述主栅P+接触区两侧的主栅N+发射极。
在一个实施方式中，还包括：P+集电极层；N型缓冲层，其设置在所述P+集电极层和所述N-型漂移层之间。
本申请提供的沟槽IGBT芯片，相较于现有技术，具有如下的有益效果：
1)本发明避免了虚栅和P阱浮空时因Cgc较大产生的位移电流导致关断瞬间Vge抬升而减小了器件关断能力；
2)本发明通过版图来调整虚栅P阱的连接方式，实现根据应用要求定量调整电流上升速率(di/dt)，提升***的抗电磁干扰能力，增强器件与***的电磁兼容性；
3)本发明的可控di/dt的IGBT结构，不影响芯片的关断安全工作区，对关断损耗(Eoff)影响小。但是可以提升开通损耗(Eon)和反向恢复损耗(Erec)的折中关系。增加虚栅P阱的接地比例，使导通速度di/dt下降，会使开通损耗增加和关断损耗下降；减小虚栅P阱的接地比例，使导通速度di/dt加快，会使开通损耗下降和Erec增加。
4)本发明可以将虚栅P阱引出电极，在IGBT导通、开关过程中施加不同的电位，从而获得不同的性能。
上述技术特征可以各种适合的方式组合或由等效的技术特征来替代，只要能够达到本发明的目的。
附图说明
在下文中将基于实施例并参考附图来对本发明进行更详细的描述。其中：
图1显示了根据本发明实施例的沟槽IGBT芯片的局部结构示意图；
图2显示了根据本发明实施例的沟槽IGBT芯片的剖面图；
图3显示了根据本发明另一实施例的沟槽IGBT芯片的剖面图；
图4显示了根据本发明实施例的沟槽IGBT芯片的俯视图；
图5和图6显示了根据本发明实施例的沟槽IGBT芯片的剖面图；
图7显示了根据本发明又一实施例的沟槽IGBT芯片的俯视图；
图8显示了根据本发明又一实施例的沟槽IGBT芯片的俯视图；
图9显示了根据本发明实施例的沟槽IGBT芯片的电流上升速率随虚拟P阱面积的变化图；
图10显示了根据本发明又一实施例的沟槽IGBT芯片的结构示意图；
图11显示了根据本发明又一实施例的沟槽IGBT芯片的剖视图；
图12显示了根据本发明又一实施例的沟槽IGBT芯片的剖视图。
附图标记清单：
100-沟槽IGBT芯片；110-P+集电极层；120-N型缓冲层；130-N-型漂移层；140-主栅极；141-第一沟槽；142-栅氧化层；143-主栅P+接触区；144-主栅N+发射极；150-虚栅极；151-第二沟槽；152-虚栅主线；153-虚栅P+接触区；154-虚栅P阱主线；155-接触开孔；156-金属层；157-多晶电阻；158-隔离氧化层；160-横向沟槽；170-虚栅有源区；171-虚栅陪区；180-第一虚栅P阱；190-第二虚栅P阱；200-母排。
在附图中，相同的部件使用相同的附图标记。附图并未按照实际的比例。
具体实施方式
下面将结合附图对本发明作进一步说明。
图1为本发明提供的沟槽IGBT芯片100的局部立体示意图。如图1所示，该沟槽IGBT芯片110可以包括由下到上依次叠置的P+集电极层110、N型缓冲层120和N-型漂移层130。该沟槽IGBT芯片100的上表面上设置有多个并联的元胞，每个元胞均包括有源区和栅极区，其中，栅极区包括平行排列的两个主栅极140，该主栅极140设置于N-型漂移层130的上表面向下蚀刻而成的第一沟槽141内，在第一沟槽141的侧壁上设置有栅氧化层142，主栅有源区包括自下而上分布的主栅极N阱和主栅极P阱，主栅极P阱包括主栅P+接触区143以及设置于该主栅P+接触区143两侧的主栅N+发射极144，有源区的主栅极N阱、主栅极P阱、该主栅P+接触区143和主栅N+发射极144的侧部止于栅氧化层142。该主栅P+接触区143和主栅N+发射极144电学短路，并通过金属层与外部连接。
在图1中，在并联的相邻元胞之间(即主栅极之间)可以设置一个或多个虚栅极150，与主栅极140类似，该虚栅极150设置于N-型漂移层130的上表面向下蚀刻而成的第二沟槽151内，在第二沟槽151的侧壁上设置有栅氧化层142。
可选地，该第一沟槽141的宽度和深度与第二沟槽151的宽度和深度可以相同，也可以不同，本发明在此不作限定。
为了说明的目的，将以两个虚栅极150为例来说明包含多个虚栅极150的沟槽IGBT芯片的情形。如图1和图2所示地，在一个实施例中，相邻元胞之间包括两个虚栅极150，该两个虚栅极150平行于主栅极140并且其彼此平行分布。如图4详细示出地，虚栅极150可以通过虚栅主线152(参见图4)引出电位，该虚栅主线152可以与元胞区的发射极或栅极连接。两个虚栅极150之间的虚栅有源区包括自下而上分布的虚栅极N阱和虚栅极P阱，该虚栅P阱包括主栅极140和虚栅极150之间的第一虚栅P阱180以及两个相邻虚栅极150之间的第二虚栅P阱190，第二虚栅P阱190仅包括虚栅P+接触区153而不包括发射极，该虚栅P+接触区153可以通过虚栅P阱主线154(参见图4)引出电位，该虚栅P阱主线可以与元胞区中的发射极或者栅极连接，或者通过电极与外部电位相连。另一方面，在主栅极140的不存在导电沟槽的一侧与虚栅极150之间的第一虚栅P阱180浮空。
作为对图2实施例的备选实施例，如图10和11所示，在主栅极140和虚栅极150之间不存在虚栅P阱，而是直接与N-型漂移层130相通。两个虚栅极150之间的第二虚栅P阱190中的虚栅P+接触区153与虚栅P阱主线连接。
在与图2实施例相反的另一个实施例中，如图3所示，主栅极140的不存在导电沟槽的一侧与虚栅极150之间的第一虚栅P阱180包括虚栅P+接触区153，其可以通过虚栅P阱主线引出电位，该虚栅P阱主线可以与元胞区中的发射极或者栅极连接，或者通过电极与外部电位相连。另一方面，两个虚栅极150之间的第二虚栅P阱190浮空。
同样地，作为对图3实施例的备选，如图12所示，两个虚栅150之间不存在虚栅P阱，而是直接与N-型漂移层130相通。主栅极140和虚栅极150之间的第一虚栅P阱180中的虚栅P+接触区153与虚栅P阱主线连接。
在另外的实施例中，在相邻的两个元胞之间仅存在一个虚栅极，则引出电位的虚栅P+接触区153则位于主栅极140的不存在导电沟槽的一侧与虚栅极150之间的第一虚栅P阱180上，该虚栅P+接触区153可以通过虚栅P阱主线引出电位，该虚栅P阱主线可以与元胞区中的发射极或者栅极连接，或者通过电极与外部电位相连。
利用上述实施例中的结构，通过分别引出虚栅以及虚栅P阱，并分别施加不同的电位，在不降低IGBT性能的前提下，能够有效地避免开关过程中的电压或电流过冲，即避免了现有技术中虚栅和虚栅P阱浮空时因Cgc较大产生的位移电流导致关断瞬间Vge抬升而减小了器件关断能力。
图4为本发明提供的沟槽IGBT芯片100的俯视图，其重点展示了母排200附近的多晶电阻和金属电极之间的联接方式。这种连接能在正面仅有一层金属时实现虚栅P阱的外部连接，不需要增加额外的工艺成本。具体来说，第二虚栅P阱190的虚栅P+接触区153通过接触开孔155与金属层156连接，再通过多晶电阻157与虚栅P阱主线154连接。多晶电阻156与半导体表面存在1000A～1300A厚度的隔离氧化层158，多晶电阻156沿着沟槽方向，即使多晶电阻156上存在电位，也不会对元胞区域产生影响。图5和图6分别是不同表面区域的截面图，该示意图展示了虚拟P阱的连接特点。图5是P阱引出电极区域附近的截面图，图6是P阱没有引出电极附近的截面图，该区域的P阱表面存在多晶电阻走线。
本领域技术人员理解，在IGBT芯片中，虚栅P阱的面积对开关过程中的电流上升速率di/dt有显著影响，如图9所示，当虚栅P阱接地时，随着虚栅P阱面积的增加，电流上升速率di/dt近似线性下降。在本发明的一个优选的实施例中，如图7所示，该沟槽IGBT芯片100还包括至少两个虚栅极150，且相邻两个虚栅极150之间设置有多个横向沟槽160，该多个横向沟槽160设置在垂直于虚栅极150的长度方向，以将第二虚栅P阱190物理地分割为多个交替排列的多个虚栅有源区170和虚栅陪区171，在虚栅有源区170中的虚栅P阱通过设置于其中的虚栅P+接触区153如上文所述地与虚栅P阱主线连接，虚栅陪区171中的虚栅P阱浮空。这样可以根据需求设计不同数目的接电位的虚栅P阱，通过增加接电位的虚栅P阱的数目来实现虚栅P阱面积的调整。
进一步地，如图8所示地，该IGBT芯片100的两个虚栅极150之间包括虚栅有源区170，其中设置有接电位的第二虚栅P阱190，通过虚栅P+接触区153如上文所述地与虚栅P阱主线连接，虚栅陪区171中的虚栅P阱浮空，且该接电位的第二虚栅P阱190和虚栅P+接触区153的长度增大，从而增大虚栅P阱的面积。
应理解，本发明以上是基于条形元胞进行解释和说明的，二本发明同样也适用与方形元胞、六角形元胞、圆形元胞等结构。
另外应理解，本发明以上是基于非穿通结构进行解释和说明的,本发明同样也适用于穿通结构和软穿通结构。
本申请提供的沟槽IGBT芯片，避免了虚栅和P阱浮空时因Cgc较大产生的位移电流导致关断瞬间Vge抬升而减小了器件关断能力；通过版图来调整虚栅P阱的连接方式，实现根据应用要求定量调整电流上升速率(di/dt)，提升***的抗电磁干扰能力，增强器件与***的电磁兼容性；本发明的可控di/dt的IGBT结构，不影响芯片的关断安全工作区，对关断损耗(Eoff)影响小。但是可以提升开通损耗(Eon)和反向恢复损耗(Erec)的折中关系。增加虚栅P阱的接地比例，使导通速度di/dt下降，会使开通损耗增加和关断损耗下降；减小虚栅P阱的接地比例，使导通速度di/dt加快，会使开通损耗下降和Erec增加；将虚栅P阱引出电极，在IGBT导通、开关过程中施加不同的电位，从而获得不同的性能。
在本发明的描述中，需要理解的是，术语“上”、“下”、“底”、“顶”、“前”、“后”、“内”、“外”、“左”、“右”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
虽然在本文中参照了特定的实施方式来描述本发明，但是应该理解的是，这些实施例仅仅是本发明的原理和应用的示例。因此应该理解的是，可以对示例性的实施例进行许多修改，并且可以设计出其他的布置，只要不偏离所附权利要求所限定的本发明的精神和范围。应该理解的是，可以通过不同于原始权利要求所描述的方式来结合不同的从属权利要求和本文中所述的特征。还可以理解的是，结合单独实施例所描述的特征可以使用在其他所述实施例中。

Claims (8)

1.一种沟槽IGBT芯片，其特征在于，包括：
N-型漂移层；
多个并联的元胞，所述元胞包括两个设置于所述N-型漂移层上表面向下蚀刻而成的第一沟槽内的主栅极，两个所述主栅极沿所述N-型漂移层的表面延伸且平行分布；
虚栅极，所述虚栅极位于元胞之间并设置于所述N-型漂移层上表面向下蚀刻而成的第二沟槽内，所述虚栅极平行于所述主栅极；
其中，所述虚栅极通过虚栅主线引出电位，所述主栅极和所述虚栅极之间的第一虚栅P阱或者两个所述虚栅P阱之间的第二虚栅P阱中设置的虚栅P+接触区通过虚栅P阱主线引出电位；
包括至少两个所述虚栅极，且相邻所述虚栅极之间设置有多个横向沟槽，其垂直于所述虚栅极的长度方向，以将所述虚栅P阱分割为交替排列的多个虚栅有源区和多个虚栅陪区，所述虚栅有源区的虚栅P阱中设置所述虚栅P+接触区，所述虚栅陪区的虚栅P阱浮空；
所述虚栅P+接触区通过接触开孔与金属电极连接，再通过多晶电阻与虚栅P阱主线连接，所述多晶电阻与芯片表面之间设置有隔离氧化层。
2.根据权利要求1所述的沟槽IGBT芯片，其特征在于，所述虚栅主线与元胞区的发射极或栅极连接，所述虚栅P阱主线与元胞区的发射极或栅极连接。
3.根据权利要求2所述的沟槽IGBT芯片，其特征在于，包括多个所述虚栅极，其中，所述第一虚栅P阱引出电位时，所述第二虚栅P阱浮空，或者所述第二虚栅P阱引出电位时，所述第一虚栅P阱浮空。
4.根据权利要求1所述的沟槽IGBT芯片，其特征在于，所述隔离氧化层的厚度为1000A-1300A。
5.根据权利要求1至3中任一项所述的沟槽IGBT芯片，其特征在于，
所述元胞为六角形元胞结构，并且多个所述元胞以蜂窝状分布在所述N-型漂移层上；或者，
所述元胞为方形元胞结构，并且多个所述元胞矩阵式地分布在所述N-型漂移层上；或者，
所述元胞为条形元胞结构，并且多个所述元胞并排地分布在所述N-型漂移层上。
6.根据权利要求1至3中任一项所述的沟槽IGBT芯片，其特征在于，所述N-型漂移层下方还包括穿通型结构、软穿通型结构或非穿通型结构。
7.根据权利要求1至3中任一项所述的沟槽IGBT芯片，其特征在于，所述两个主栅极之间的主栅极P阱包括主栅P+接触区以及设置于所述主栅P+接触区两侧的主栅N+发射极。
8.根据权利要求1至3中任一项所述的沟槽IGBT芯片，其特征在于，还包括：
P+集电极层；
N型缓冲层，其设置在所述P+集电极层和所述N-型漂移层之间。
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