JP2009004398A - 半導体装置およびこれを用いた電力変換装置 - Google Patents
半導体装置およびこれを用いた電力変換装置 Download PDFInfo
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- JP2009004398A JP2009004398A JP2007160882A JP2007160882A JP2009004398A JP 2009004398 A JP2009004398 A JP 2009004398A JP 2007160882 A JP2007160882 A JP 2007160882A JP 2007160882 A JP2007160882 A JP 2007160882A JP 2009004398 A JP2009004398 A JP 2009004398A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 317
- 239000000758 substrate Substances 0.000 claims abstract description 76
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- 239000012535 impurity Substances 0.000 claims description 18
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical group [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 12
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- 230000004888 barrier function Effects 0.000 claims description 9
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- 230000000694 effects Effects 0.000 description 3
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- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
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- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
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- 230000007423 decrease Effects 0.000 description 1
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
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- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
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Abstract
【解決手段】同一の半導体チップ30内に、ダイオードおよび高電子移動度トランジスタを内蔵する半導体装置であって、ダイオードが有する半導体基板20の主面(第1主面)20a上に高電子移動度トランジスタが有する化合物半導体層10を形成し、ダイオードのアノード電極26は、化合物半導体層10の主面10aから半導体基板20の主面20aのアノード領域であるp+領域23に達するビアホール(孔)25に埋め込まれた導電体を通じてアノード領域に電気的に接続するように構成するものである。
【選択図】図2
Description
本実施の形態1では、高電子移動度トランジスタを備えた半導体装置を、電力変換装置のスイッチング素子として適用する実施態様について説明する。
まず、図1を用いて本実施の形態1の電力変換装置の回路構成について説明する。図1は本実施の形態1の電力変換装置の回路図である。
次に、図2を用いて本実施の形態1の半導体装置の構造について説明する。
次に図3を用いて図2に示す半導体チップ30を電力変換装置のスイッチング素子として実装した半導体パッケージの構造例について説明する。図3は図1の半導体チップ30のパッケージ構造例を示す平面図である。
次に、図4〜図9を用いて図2に示す半導体装置の製造方法を説明する。
次に、図10を用いて本実施の形態2の半導体装置について説明する。図10は本実施の形態2の半導体装置を構成する半導体チップ40の要部断面図である。
次に、図11を用いて本実施の形態3の半導体装置について説明する。図11は本実施の形態3の半導体装置を構成する半導体チップ50の要部断面図である。
次に、図12を用いて本実施の形態4の半導体装置について説明する。図12は本実施の形態4の半導体装置を構成する半導体チップ60の要部断面図である。
次に、図13を用いて本実施の形態5の半導体装置について説明する。図13は本実施の形態5の半導体チップ70の構造を示す断面図である。
次に、図14を用いて本実施の形態6の半導体装置について説明する。図14は本実施の形態6の半導体装置を構成する半導体チップ80の要部断面図である。
2 ダイオード
3 スイッチング素子
4 ゲートドライバ
10 化合物半導体層(第2基板)
10a 主面(第3主面)
11 バッファ層(第1化合物半導体層)
12 チャネル層(第2化合物半導体層)
13 電子供給層(第3化合物半導体層)
15 ドレイン電極
16 ゲート電極
17 ソース電極
18 絶縁層
19 コンタクトホール
20 半導体基板(第1基板)
20a 主面(第1主面)
20b 主面(第2主面)
21 n+層(第1半導体層、カソード領域)
22 n−層(第2半導体層、カソード領域)
23 p+領域(アノード領域)
24 p−領域(アノード領域)
25 ビアホール
26 アノード電極
27 カソード電極
30、40、50、60、70、80 半導体チップ(半導体装置)
31 ゲートパッド
32 ソースパッド
33 ドレインパッド
34 ゲート端子
35 ソース端子
36 ドレイン端子
37、38、39 ボンディングワイヤ
41 ビアホール
42 導電体
43 コンタクトホール
51 n+領域(第3半導体領域)
61 カソード電極
71 ショットキーバリア金属
81 n+層(第1半導体層、カソード領域)
82 n−層(第2半導体層、カソード領域)
100 電力変換装置
101 直流電源
102 モータ
Claims (13)
- 同一の半導体チップ内に高電子移動度トランジスタとダイオードとを有し、
前記半導体チップは、
厚さ方向に沿って互いに反対側に位置する第1主面および第2主面を有する半導体基板と、
前記半導体基板上に形成された化合物半導体層とを有しており、
前記高電子移動度トランジスタは、
前記化合物半導体層と、前記化合物半導体層の主面上に形成されたドレイン電極、ゲート電極およびソース電極とを有しており、
前記ダイオードは、
前記半導体基板に形成されたカソード領域と、
前記カソード領域に接するように前記半導体基板の前記第1主面側に形成されたアノード領域と、
前記化合物半導体層の主面上に形成されたアノード電極とを有しており、
前記アノード電極は、前記化合物半導体層の主面から前記半導体基板の前記第1主面の前記アノード領域に達する孔に埋め込まれた導電体を通じて前記アノード領域に電気的に接続されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記高電子移動度トランジスタの前記ソース電極と、前記ダイオードの前記アノード領域とは電気的に接続されていることを特徴とする半導体装置。 - 請求項2に記載の半導体装置において、
前記高電子移動度トランジスタの前記ソース電極と、前記ダイオードの前記アノード領域とは前記アノード電極を構成する前記導電体によって接続されていることを特徴とする半導体装置。 - 請求項3に記載の半導体装置において、
前記化合物半導体層の主面上には、前記ドレイン電極、前記ゲート電極および前記ソース電極が所定の間隔を持って順に配置され、
前記アノード電極は、前記化合物半導体層の主面上方において、前記ソース電極側から前記ゲート電極と前記ドレイン電極との間まで前記化合物半導体層の主面に沿って延在するように配置されていることを特徴とする半導体装置。 - 請求項2に記載の半導体装置において、
前記ダイオードのカソード電極は、前記高電子移動度トランジスタの前記ドレイン電極と、前記半導体チップ内で電気的に接続されていることを特徴とする半導体装置。 - 請求項5に記載の半導体装置において、
前記半導体基板は、
前記第2主面から順に積層される第1導電型の第1半導体層、および第2半導体層とを備え、
前記第1半導体層は、第1不純物濃度であり、
前記第2半導体層は、前記第1不純物濃度よりも低い第2不純物濃度であり、
前記ダイオードの前記カソード電極は、前記化合物半導体層の主面から前記半導体基板の前記第1半導体層に達する孔に埋め込まれた前記導電体を通じて前記ドレイン電極に電気的に接続されていることを特徴とする半導体装置。 - 請求項5に記載の半導体装置において、
前記半導体基板は、
前記第2主面から順に積層される第1導電型の第1半導体層、および第2半導体層とを備え、
前記第1半導体層は、第1不純物濃度であり、
前記第2半導体層は、前記第1不純物濃度よりも低い第2不純物濃度であり、
前記第2半導体層には、前記第1主面から前記第1半導体層との接触面まで達するように延在する第3半導体領域を備え、
前記ダイオードの前記カソード電極は、前記化合物半導体層の主面から前記半導体基板の前記第3半導体領域に達する孔に埋め込まれた前記導電体を通じて前記ドレイン電極に電気的に接続されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記半導体基板は、
前記第2主面から順に積層される第1導電型の第1半導体層、および第2半導体層とを備え、
前記第1半導体層は、第1不純物濃度であり、
前記第2半導体層は、前記第1不純物濃度よりも低い第2不純物濃度であり、
前記ダイオードは、前記第1基板の前記第2主面にカソード電極を備えていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記半導体基板を構成する半導体材料はシリコンであることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記ダイオードの前記アノード領域は、前記第1導電型と反対導電型の半導体領域であることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記半導体基板は、
前記第2主面から順に積層される第1導電型の第1半導体層、および第2半導体層とを備え、
前記第1半導体層は、第1不純物濃度であり、
前記第2半導体層は、前記第1不純物濃度よりも低い第2不純物濃度であり、
前記ダイオードの前記アノード領域は、ショットキーバリア金属であることを特徴とする半導体装置。 - 請求項11に記載の半導体装置において、
前記半導体基板を構成する半導体材料はシリコンカーバイドであることを特徴とする半導体装置。 - スイッチング素子としての半導体装置を備え、
前記半導体装置は、
同一の半導体チップ内に高電子移動度トランジスタとダイオードとを有し、
前記半導体チップは、
厚さ方向に沿って互いに反対側に位置する第1主面および第2主面を有する半導体基板と、
前記半導体基板上に形成された化合物半導体層とを有しており、
前記高電子移動度トランジスタは、
前記化合物半導体層と、前記化合物半導体層の主面上に形成されたドレイン電極、ゲート電極およびソース電極とを有しており、
前記ダイオードは、
前記半導体基板に形成されたカソード領域と、
前記カソード領域に接するように前記半導体基板の前記第1主面側に形成されたアノード領域と、
前記化合物半導体層の主面上に形成されたアノード電極とを有しており、
前記アノード電極は、前記化合物半導体層の主面から前記半導体基板の前記第1主面の前記アノード領域に達する孔に埋め込まれた導電体を通じて前記アノード領域に電気的に接続されていることを特徴とする電力変換装置。
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US7838907B2 (en) | 2010-11-23 |
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