TWI528477B - 具有線接合互連之無基板可堆疊封裝、製造微電子單元的方法、製造微電子封裝的方法以及製造微電子組件的方法 - Google Patents

具有線接合互連之無基板可堆疊封裝、製造微電子單元的方法、製造微電子封裝的方法以及製造微電子組件的方法 Download PDF

Info

Publication number
TWI528477B
TWI528477B TW102117978A TW102117978A TWI528477B TW I528477 B TWI528477 B TW I528477B TW 102117978 A TW102117978 A TW 102117978A TW 102117978 A TW102117978 A TW 102117978A TW I528477 B TWI528477 B TW I528477B
Authority
TW
Taiwan
Prior art keywords
microelectronic
wire
conductive
layer
package
Prior art date
Application number
TW102117978A
Other languages
English (en)
Other versions
TW201401398A (zh
Inventor
伊黎雅斯 莫罕默德
Original Assignee
英帆薩斯公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 英帆薩斯公司 filed Critical 英帆薩斯公司
Publication of TW201401398A publication Critical patent/TW201401398A/zh
Application granted granted Critical
Publication of TWI528477B publication Critical patent/TWI528477B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4046—Through-connections; Vertical interconnect access [VIA] connections using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45155—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45565—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45624—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45655—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/45664—Palladium (Pd) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/45669—Platinum (Pt) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H01L2224/4569—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1052—Wire or wire-like electrical connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/46—Structure, shape, material or disposition of the wire connectors prior to the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00012—Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/182—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10287—Metal wires as connectors or conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

具有線接合互連之無基板可堆疊封裝、製造微電子單元的方法、製造微電子封裝的方法以及製造微電子組件的方法
本發明關於一種具有線接合互連之無基板可堆疊封裝。
諸如半導體晶片的微電子裝置通常需要連接到其它電子構件的許多輸入和輸出。半導體晶片或其他可比較的設備的輸入和輸出接點一般設置在類似格子狀的圖案中，格子狀的圖案基本上覆蓋裝置的表面(通常被稱為“區域陣列”)，或在平行並相鄰裝置的前表面的每個邊緣而延伸的細長的列中，或在所述前表面的中心中。通常情況下，例如晶片的裝置必須物理地安裝在例如印刷電路面板的基板上，以及該裝置的接點必須被電連接到電路面板的電性傳導特徵。
半導體晶片通常設在有利於在製造期間和晶片的安裝在諸如電路面板或其它電路面板的外部基板上期間的晶片處理的封裝中。例如，許多半導體晶片設在適合於表面安裝的封裝中。已經提出了針對各種應用的這種通用類型的許多封裝。最常見的是，這種封裝包括介電質元件， 通常被稱為“晶片載體”，帶有在介電質上電鍍或蝕刻金屬結構形成的端子。這些端子通常藉由諸如沿著本身的晶片載體延伸的薄的跡線以及藉由在晶片的接點和端子或跡線之間延伸的精細引線或導線而連接到本身的晶片的接點。在表面安裝操作中，封裝被放置在電路基板上，使得在封裝上的每個端子與在電路面板上對應的接觸墊對準。焊接或其他接合材料設置在端子和接觸墊之間。封裝可以藉由加熱組件永久地接合在適當位置，以便熔化或“回流”焊料或以其它方式激活接合材料。
許多封裝包括以焊料球的形式的焊料群，通常直徑為約0.1毫米和約0.8毫米(5至30密耳)，連接到封裝的端子。具有從底表面突出的焊料球陣列的封裝通常被稱為球閘陣列或“BGA”封裝。簡稱為閘格陣列或“LGA”封裝的其他的封裝係藉由來自焊料所形成的薄層或平面固定到基板。這種類型的封裝可以是相當緊湊的。通常被稱為“晶片尺度封裝”的特定封裝佔用電路面板的面積等於或僅稍大於併入封裝中的裝置的面積。這是有利的，這封裝減少了組件的整體尺寸，並且允許在基板上的各種裝置之間的短的互連之使用，亦限制了在裝置之間的信號傳播時間，從而有利於在高速下組件的操作。
經封裝的半導體晶片通常設置在經“堆疊”的排列中，其中例如一個封裝設在電路面板上，另一個封裝被安裝在第一個封裝的頂部上。這些排列可以允許多個不同的晶片被安裝在電路面板上的單一的足跡，且可以進一步藉由封裝之間的短的互連而促進高速操作。通常，這種互連距離為僅稍大於本身晶片的厚度。針對實現互連在晶片封裝的堆疊內，有必要提供在每個封裝(除了最上面的封裝)的兩側上用於機械和電 性連接的結構。例如，通過提供接觸墊或平面在晶片被安裝的基板的兩側上而完成這項工作，該墊藉由傳導通孔或類似物連接通過基板。焊料球或類似物已被用於橋接在較下層基板的頂部上的接點到下一個較上層基板的底部上的接點之間的間隙。焊料球必須是高於晶片的高度，以連接接點。 堆疊晶片排列和互連結構的範例在提供在美國專利申請公開案第2010/0232129號(“'129公開”)中，其公開內容在此通過引用而將其全部內容併入。
儘管上述所有在本領域中的進步，仍對進一步改善在微電子封裝之製造和測試是值得嚮往的。
本公開的一個態樣涉及一種用於製造一微電子單元的方法。該方法包括在以包括可圖案化金屬元件的結構之傳導層的傳導接合表面的形式之第一表面上來形成複數個線接合。線接合係形成以具有連結到第一表面的基底及遠離基底且遠離第一表面的末端表面。線接合進一步具有在基底和末端表面之間延伸的邊緣表面。該方法也包括形成介電質膠封層在傳導層的第一表面的至少一部分上方且在線接合的部分上方，使得線接合的未膠封的部分藉由末端表面或未被膠封層所覆蓋的邊緣表面的一部分而定義。金屬元件係選擇性圖案化以形成藉由膠封層的至少部分彼此絕緣的第一傳導元件。該線接合中的至少一些設置在該第一傳導元件的頂上。
微電子元件可以包含在該結構中且當執行除去部分的該傳導層的步驟時與該傳導層電性連接。形成該介電質膠封層的步驟可以與偕同該傳導層電性連接的該微電子元件完成，使得該膠封層至少部分地覆蓋 其之至少一個表面。該第一傳導元件中的至少一些可以在該線接合的各自者和該微電子元件之間電性連接。
該方法的範例可以進一步包括以下步驟：形成一再分佈層於該膠封層的該第二表面上方。該再分佈層可以包括從該線接合的未暴露部分的至少一個橫向方向位移之傳導接點。
該線接合中的至少一些可以形成，使得線接合的末端表面在從線接合的基底的一個或多個橫向方向位移。在範例中，該線接合的基底可以被佈置在具有一第一最小間距的一第一圖案中，該線接合的該未膠封的部分能佈置在具有大於該第一最小間距的一第二最小間距的一圖案中。 該基底可以佈置在具有一第一最小間距的一第一圖案中，該線接合的該未膠封的部分能佈置在具有小於該第一最小間距的一第二最小間距的一圖案中。
該方法可以進一步包括形成覆蓋該第二介電質層的該第二表面的第二傳導元件。該第二傳導元件中的至少一些可以與該線接合的該未膠封部分中的至少一些的個別者連接。
選擇性除去部分的該傳導層的步驟可以包括形成至少一些第一傳導元件，作為接觸墊以電性連接至沒有與該單元中的其他元件電性連接的線接合的基底。
該方法可以進一步包括藉由研磨或拋光中的一者使該單元變薄。在一範例中，該膠封層可以形成以具有初始厚度，使得該線接合的該末端表面基本上被覆蓋，使該單元變薄的步驟包括：去除部分的該膠封層，使得該末端表面變成未藉由該膠封層所膠封。
形成該膠封層的步驟可以包括分配一膠封劑到該傳導層的該第一表面的和該線接合的至少邊緣表面。進一步，形成該膠封層的步驟可以包括模制該膠封劑以與該傳導層、該線接合的至少邊緣表面以及該微電子元件的至少表面接觸。
該方法可以進一步包括在執行選擇性去除部分的該傳導層的步驟之前，從相對於該線接合的該傳導層的表面去除一載體。
在一實施例中，該傳導層可以具有小於20微米的厚度。
本發明的另一個態樣涉及一種用於製造一微電子封裝的方法。該方法可以包括形成複數個線接合在一處理中單元的一傳導層的一第一表面上。該處理中單元具有至少一個微電子元件，該微電子元件被連結且該微電子元件之部分被電性連接。該線接合係形成以具有連結到該第一表面的基底和遠離該基底且遠離該第一表面的末端表面。該線接合進一步具有在該基底和該末端表面之間延伸的邊緣表面。該方法也包括形成介電質膠封層在該傳導層的該第一表面的至少一部分上方，在至少一個該微電子元件的至少一部分的上方，以及在該線接合的部分上方，使得該線接合的未膠封的部分藉由該末端表面或未藉由該膠封層所覆蓋的線接合之邊緣表面的部分中的至少一個所定義。選擇性除去部分的該傳導層，以形成第一傳導元件。該第一傳導元件中的至少一些電性連接該線接合中的至少一些，以及該第一傳導元件中的至少一些包括與該微電子元件電性連接的該傳導層的部分中的至少一些。
本發明的另一個態樣涉及一種用於製造一微電子單元的方法。該方法包括形成複數個線接合在一第一表面上，該第一表面是包括一 可圖案化金屬元件的一結構之傳導層的一傳導接合表面。該線接合具有連結到該第一表面的基底及遠離該基底且遠離該第一表面的末端表面。該線接合進一步具有在該基底和該末端表面之間延伸的邊緣表面。當形成該線接合時，該傳導層包括在至少一些邊緣處的複數個彼此附接的區域。該方法也包括形成一介電質膠封層在該傳導層的該第一表面的至少一部分上方與該線接合的部分上方，使得該線接合的未膠封部分藉由末端表面或未由膠封層所覆蓋的邊緣表面的部分的至少一個所定義，其中，當執行選擇性去除部分的該膠封層的步驟時，複數個微電子元件連結到該傳導層，以具有電性連接該傳導層的該區域中的至少一些的每一個的至少一個微電子元件之一處理中單元的形式。然後選擇性圖案化該金屬元件以形成藉由至少部分的該膠封層彼此絕緣的第一傳導元件。該線接合中的至少一些設置在該第一傳導元件的頂上。然後該處理中單元成分割成複數個微電子單元，各包括該傳導層的該區域的該第一傳導元件和與其電性連接的至少一個微電子元件。
本發明的另一個態樣涉及一種用於製造一微電子組件的方法。該方法包括製造一第一微電子封裝，其包括形成複數個線接合在一處理中單元的一傳導層的一第一表面上。該處理中單元具有至少一個微電子元件，該微電子元件被連結且該微電子元件之部分被電性連接。該線接合係形成以具有連結該第一表面的基底和遠離該基底且遠離該第一表面的末端表面，該線接合進一步具有在該基極和該末端表面之間延伸的邊緣表面。該線接合進一步包括形成介電質膠封層在該傳導層的該第一表面的至少一部分上方，在該至少一個微電子元件的至少部分上方，以及該線接合 的部分上方，使得該線接合的未膠封部分藉由該末端表面或未由該膠封層所覆蓋的其之邊緣表面的部分的至少一個所定義。選擇性除去部分的該傳導層，以形成第一傳導元件。該第一傳導元件中的至少一些電性連接該線接合中的至少一些以及該第一傳導元件中的至少一些包括與該微電子元件電性連接的該傳導層的部分中的至少一些。該方法也包括連結該第一微電子封裝與覆蓋該第一微電子封裝的該膠封層的該第二表面的第二微電子封裝。該第二微電子封裝包括在第二微電子封裝之一第一表面處暴露的複數個接點。連結該第一微電子封裝與該第二微電子封裝包括電性連接該第一微電子封裝的該線接合的該未膠封部分與該第二微電子封裝的該接點。
本公開的另一個態樣涉及一種包括至少一個微電子元件的微電子封裝。該封裝進一步包括第一傳導元件，第一傳導元件包括在該封裝的一安裝表面處暴露的端子。該第一傳導元件中的至少一些透過與該第一傳導元件一體地形成的通孔電性連接到至少一個該微電子元件。該封裝進一步包括線接合，具有連結到該傳導元件的個別者且鄰近該介電質膠封層的該第一表面之基底以及遠離該基底的末端表面。各個線接合定義在基底和末端表面之間延伸的一邊緣表面。該封裝也包括一介電質膠封層，具有一第一表面和遠離該第一表面的一第二表面。該第一表面的至少一部分被暴露在該封裝的該安裝表面處。該介電質膠封層填充在該線接合之間的空間，使得該線接合藉由該膠封層彼此分開。該線接合的未膠封的部分藉由在該介電質膠封層之該第二表面處未被該膠封層所覆蓋的該線接合的該末端表面的至少一部分所定義。
該線接合的該未封裝部分中的至少一些可以在從個別的基 底的至少一個橫向方向中位移。
該封裝可以進一步包括一第二微電子元件。在一範例中，該第一微電子元件可以包括暴露在朝向該介電質層的該第一表面設置之正面的接點，以及該第二微電子元件可以包括暴露在朝向該介電質層的該第二表面設置之正面的接點。在這一範例中，該封裝可以進一步包括暴露在該膠封層的該第二表面處的第二傳導元件。該第二傳導元件中的至少一些可以在該第二微電子元件的該接點的個別者與該未膠封線接合部分的個別者之間連接。該第一和第二微電子元件可以藉由與該第一微電子元件的至少一個接點和該第二微電子元件的至少一個接點電性連接的至少一個線接合所電性連接。或者，該第二微電子元件可以藉由連結在該第二微電子元件的該接點的一者和該第二微電子元件的個別一者之間的一線接合連接第二傳導元件的一者。在另一範例中，該第一和第二微電子元件可以藉由連結至該第二微電子元件的一接點與暴露在該膠封層的該第一表面處的該傳導元件的個別一者的線接合電性連接。
一種微電子組件，包括：如上述的一第一微電子封裝；以及一第二微電子封裝，其包括一微電子元件和在暴露於該第二微電子封裝的一表面處的端子。該端子電性連接該微電子元件。進一步，該第二微電子封裝可以覆蓋該第一微電子封裝，且可以電性連接到該第一微電子封裝的該線接合的該未膠封部分中的至少一些的端子與第一微電子封裝接合。
一種系統可以包括如上述的微電子封裝以及一個或多個電子構件。
10‧‧‧微電子封裝
10A‧‧‧第一微電子單元或封裝
10B‧‧‧第二微電子單元或封裝
20‧‧‧前表面
22‧‧‧微電子元件
24‧‧‧微電子接點
25‧‧‧通孔
28‧‧‧傳導元件、傳導特徵
28’‧‧‧傳導金屬層
30’‧‧‧表面
31‧‧‧跡線
32‧‧‧線接合
34‧‧‧基底
35‧‧‧末端表面
36‧‧‧末端
38‧‧‧末端表面
42‧‧‧膠封層
44‧‧‧表面
45‧‧‧表面
52‧‧‧焊料塊
90‧‧‧電路面板
92‧‧‧面板接點
110‧‧‧微電子封裝
120‧‧‧附著層
122‧‧‧微電子元件
124‧‧‧微電子接點
125‧‧‧金屬化通孔
128‧‧‧微電子元件、微電子特徵
128’‧‧‧傳導金屬層
130’‧‧‧表面
131‧‧‧跡線
132‧‧‧線接合
134‧‧‧基底
142‧‧‧膠封層
144‧‧‧表面
145‧‧‧表面
210‧‧‧微電子封裝
222A‧‧‧微電子元件
222B‧‧‧微電子元件
224‧‧‧接點
228‧‧‧傳導元件
231‧‧‧跡線
232‧‧‧線接合
242‧‧‧膠封層
244‧‧‧表面
245‧‧‧表面
310‧‧‧微電子封裝
322A-C‧‧‧微電子元件
324‧‧‧接點
325‧‧‧金屬化通孔
331‧‧‧路由電路
332‧‧‧線接合
342‧‧‧膠封層
344‧‧‧表面
362‧‧‧線接合
422A-B‧‧‧微電子元件
424‧‧‧接點
425‧‧‧金屬化通孔
431‧‧‧跡線
442‧‧‧膠封層
444‧‧‧表面
445‧‧‧表面
466‧‧‧線接合
510‧‧‧微電子組件
522‧‧‧微電子元件
532‧‧‧線接合
534‧‧‧基底
536‧‧‧末端
542‧‧‧膠封層
544‧‧‧表面
545‧‧‧表面
546‧‧‧角度
現在將參照附圖來描述本發明的各種實施例。可以理解，這些附圖僅示出本發明的一些實施例，因此不被認為是限制本發明的範圍。
圖1示出了藉由根據本發明的方法的步驟處理以形成微電子封裝之處理中單元的俯視示意圖；圖2示出了圖1的處理中單元的側視圖；圖3示出了在該方法的進一步處理步驟中圖1的處理中單元的頂視圖；圖4示出了圖3的處理中單元的側視圖；圖5示出了藉由區域A表示的圖4的處理中單元的一部分的詳細視圖；圖6示出了在該方法的進一步處理步驟中圖1的處理中單元的頂視圖；圖7示出了圖6的處理中單元的側視圖；圖8示出了藉由區域B表示的圖7的處理中單元的一部分的詳細視圖；圖9示出了可以由該方法所致的微電子封裝的側視圖；圖10示出了藉由區域C表示的圖9的封裝的詳細視圖；圖11示出了在該方法的進一步可選處理步驟之後的圖10的詳細視圖；圖12示出了在該方法的進一步可選處理步驟中的圖9的封裝的側視圖；圖13示出了藉由區域D表示的圖12的封裝的一部分的詳細視圖；圖14示出了藉由根據本發明的方法的變化的步驟可以處理以形成微電子封裝之替代的處理中單元的俯視示意圖；圖15示出了藉由區域E表示的圖14的封裝的一部分的詳細視圖；圖16示出了可以由該方法變化所致的微電子封裝的側視圖；圖17示出了在該方法的進一步可選處理步驟變化之後的圖16的封裝 的一部分的詳細視圖；圖18示出了替代的微電子封裝；圖19示出了藉由區域F表示的圖18的封裝的一部分的詳細視圖；圖20示出了進一步替代的微電子封裝；圖21示出了藉由區域G表示的圖20的封裝的一部分的詳細視圖；圖22示出了進一步替代的微電子封裝；圖23示出了進一步替代的微電子封裝；圖24示出了可以包括根據此處所示的各種實施的一個或多個封裝的微電子組件的範例。
現在回到附圖，其中類似的參考數字用於表示相似的特徵，圖9顯示了根據本發明的實施例的微電子裝置或封裝10，圖1-8示出根據本發明的另一個實施例的方法的微電子封裝的形成的各個階段。圖9的實施例是以經封裝的微電子元件的形式的微電子封裝10，例如用於計算機或其它電子應用中的半導體晶片組件。
圖9的微電子封裝10包括微電子元件22。如進一步參見圖10，微電子封裝10可以嵌入在膠封層42之內，或者可以在微電子封裝之一個或多個表面上藉由膠封層所接觸，例如，前或後表面或者在前或後表面之間延伸的邊緣表面。膠封層42具有從第一表面45到第二表面44延伸的厚度。第一和第二表面可至少部分地暴露封裝10的各自的第一和第二安裝表面11和12。這樣的厚度可以至少等於微電子元件22本身的厚度。可以於圖10看出，膠封層42可以從微電子元件22以橫向方向進一步向外延伸， 如圖6的平面視圖所示。複數個線接合32也嵌入在膠封層之內且在分別未藉由膠封層所覆蓋且可能與表面45和44齊平(例如，共平面)的末端表面35和38之間延伸。為了本討論的目的，第一表面45可被描述為從第二表面44相對或遠離來定位。這樣的描述，以及用於此處的元件的涉及這種元件的垂直或水平位置之相對位置的其他的描述係僅供說明之用以對應於附圖內的元件的位置，且不限制。
微電子元件22可以是半導體晶片或另一個可比較的裝置，具有可以是以在晶片上的整合或被動的形式(“IPOC)之複數個主動或被動電路元件或者主動和被動電路元件皆有等等。在圖10所示的實施例中，微電子元件22具有藉由膠封層42接觸(例如，覆蓋)的邊緣表面和後表面的至少部分。微電子元件22可定位使得接點24相鄰封裝的第一安裝表面11。另外，在這樣的排列中，接點24與沿膠封層42的第一表面43延伸的傳導元件28連接以在末端表面35處電性連接線接合32，末端表面可以由各自的線接合32的基底34所定義。這種基底34可以是用於形成線接合32的處理的加工品，並且可以是藉由球型接合所形成的這種基底34的形狀，如所示，或者楔形接合、縫編法或類似所形成。在其他實施例中，如示於圖16，基底可以在製造期間部分或完全地除去，如藉由研磨(grinding)、抹磨(lapping)、拋光(polishing)或其它合適的技術的變薄處理。這樣的變薄或用其它處理也可以減少線接合132的高度，使得末端表面135被定義為在基底之上的線接合132的盡頭。再次參見圖10，在一個實施例中，微電子接點24可以藉由傳導(例如，金屬化)通孔25而電性連接傳導元件28，傳導通孔包括沉積到微電子元件的接點24的通孔，例如，藉由一種或多個金屬的 電鍍、濺射或氣相沉積，如銅、鎳、鉻、鋁、金、鈦、鎢、鈷或其中一種或多種的合金，但不設限。在一個實施例中，傳導元件可以藉由沉積具有金屬和非金屬成分的液體的傳導性基體材料並在之後固化已沉積的傳導性基體材料所形成。例如，傳導性基體材料可以沉積和使用。
傳導元件28可以包括各自的“接點”或“墊”，其可以暴露在膠封層42的第二表面44處。如本描述中所使用的，當電性傳導元件被描述為“暴露”於具有介電質結構的另一元件的表面，這表明電性傳導元件是可利用於接觸在垂直介電質結構的表面且從介電結構外側朝向介電結構的表面之方向移動的理論上的點。因此，暴露在介電質結構的表面處的端子或其它傳導結構可以從這樣的表面投影；可以是與這樣的表面齊平；或者可以相對於這樣的表面凹陷且經由在介電質中的孔或凹地所暴露。在一個實施例中，傳導元件28可以是平的，薄的元件暴露在膠封層42的第一表面45處。傳導元件28可以具有任何合適的形狀，並在某些情況下可以是圓形的。傳導元件28可以藉由跡線31彼此電性互連、電性互連至微電子元件22或兩者。傳導元件28也可以沿微電子元件22的前表面20所形成。
如圖12和13所示，額外的傳導元件28可以暴露在膠封層42的第二表面44處。這種傳導元件可以壓在線接合32的末端表面38上且與線接合32電性連接。在其他變化中，這樣的傳導元件可以包括墊，墊在沿著表面44的至少一個橫向方向上從對應的線接合位移至墊可以藉由跡線31連接在線接合之末端表面之處。
線接合32可以連結至傳導元件28的至少一些，如傳導元件之表面上。線接合32可以在線接合之基座34處連結至傳導元件28且可以 延伸至與各自的基底34和與第一表面43遠離(即，相對)的末端36。線接合32的末端36可被表徵為“自由的”，末端沒有電性連接或以其他方式連結至微電子元件22或者反過來連接到微電子元件22之微電子封裝10內的任何其他的傳導特徵。換句話說，自由末端36可用於電子連接，可直接或間接地通過傳導元件28或本文所討論的其它特徵至封裝10的外部傳導特徵。 末端36藉由例如膠封層42保持在預定的位置或以其他方式連結或電性連接另一傳導特徵的事實不意味著末端不是如本文所述的“自由的”，只要任何這樣的特徵是不電性連接到微電子元件22。相反地，基底34可能不是自由的，因為他們可以直接或間接地電性連接到微電子元件22，如本文所述。 如圖10所示，基底34可以在形狀上變圓，而從定義在基底34和末端36之間的線接合32的邊緣表面向外延伸。基底34的具體尺寸和形狀可以根據用於形成線接合32的材料類型、在線接合32和傳導元件28之間的連接所要求的強度、或者在特定處理中用以形成線接合32而有所不同。
線接合32藉由在線接合表面處接合銅、金、鎳、焊料、鋁或金屬合金的金屬線所形成，並執行一個或多個其他的步驟，以便形成具有遠離(例如，相對)之基底和未膠封表面的線接合，導線的長度於基底和未膠封表面之間延伸。此外，線接合32可以由材料的組合所製成，諸如從如銅或鋁的傳導材料的芯，例如，以塗層應用於芯上。該塗層可以是第二傳導材料，如鋁、鎳、鉑或鈀等等。另外，該塗層可以是一種絕緣材料，如絕緣套。在一個實施例中，用於形成線接合32的線可以具有約15μm至150μm之間的厚度，即，在線長度的橫向尺寸中。在一般情況下，線接合32可以形成在金屬接合表面上，即，使用線接合工具的結構的表面的第一 金屬接合表面。在包括如下面描述的用於楔形接合的其他實施例中，線接合32可以具有高達約500μm的厚度。線區段的引線末端被加熱並對線區段所接合的接收表面加壓，通常形成連結傳導元件28的表面的球或球狀基底34。線區段用以形成線接合的所需長度被從接合工具拉出，接合工具然後可以在所需的長度下切斷或切割線接合。可以用來形成鋁的線接合之楔形接合例如是線的加熱部分被拖動整個接收表面以形成位於大致平行於表面的楔形之過程。楔形接合之線接合然後可以向上彎曲，如果有必要，並在切割前延伸到所需的長度或位置。在一個特定的實施例中，用以形成線接合的線可以是橫截面為圓柱形。否則，從工具供給以形成線接合或楔形接合之線接合的線可以具有多邊形的橫截面，例如諸如矩形或梯形。
線接合32的自由末端36可以定義各自的末端表面38。末端表面38可以形成藉由複數個線接合32的各自的末端表面38所形成的如網格或陣列的圖案的至少一部分的接點。圖6和圖7示出針對藉由末端表面38所形成的接點的這樣的陣列之示範性圖案。這樣的陣列可以形成在一區域陣列配置中，陣列之變化會使用於本文所描述的結構來實施。在如所示的變化中，不需要是在圖6的網格或陣列圖案的每個位置處的線接合的末端表面。這樣的陣列可用於電性和機械性連接微電子封裝10到另一個微電子結構，如至印刷電路面板(“PCB”)，或其他經封裝的微電子元件，這個例子示於圖24。在這樣的堆疊的排列中，線接合32和傳導元件28可以攜帶穿過線接合和傳導元件的多個電子信號，每個都具有不同的信號電位，以允許針對不同的信號在單一堆疊中由不同的微電子元件進行處理。為末端表面38所設置的網格或陣列圖案在一定的位置，該位置可設置在與 基底34所設置的網格或陣列圖案相同或不同的末端表面之位置處。在如圖9所示的例子中，在線接合32一般是垂直排列之處，這樣的陣列可以是相同的。在其他排列中，例如如圖23所示的可以包括相對於膠封層542的表面545成一定角度的線接合532，使得末端表面38的陣列的間距比基底34的間距更大。這樣的排列的逆轉也是可能的。另外，如上所討論的，傳導元件28可以從末端表面35或38橫向移動至傳導元件藉由跡線31電性連接之處。這樣的排列也可以提供在表面545和544上方不同的間距或接點的其他不同的排列。
如圖24所示，這樣的封裝10A可以排列在具有其它類似封裝10B或類似的一堆疊中。雖然圖24示出了兩個這樣的微電子封裝10A、10B，但是三個、四個或甚至更多個可以被排列在這樣的堆疊中，堆疊也可以藉連結傳導元件28至電路面板90的焊料塊52與面板接點92組裝在一起。焊料塊52也可以用以在這種堆疊中互連微電子組件，例如通過電子地和機械性附接末端表面38至傳導元件28或者連接傳導元件28至其他傳導元件28。
再次參見圖10和其他圖式，膠封層42用於保護在微電子封裝件10內的其他元件，特別是線接合32。這允許更強大的結構，該結構是透過該結構之測試或運輸或裝配至其他微電子結構期間不太可能被損壞。膠封層42可由帶有絕緣特性的絕緣材料所形成。
如上所述，圖23示出具有帶有末端536的線接合532的微電子組件510的實施例，末端並不位於線接合之各自的基底534正上方。即，考慮電子組件510的第一表面545在兩個橫向方向延伸，以便大致上定義一 平面，末端536或線接合532的至少一個係從基底534的對應的橫向位置在這些橫向方向中的至少一個中位移。如圖23所示，線接合532可如圖9的實施例中沿線接合縱軸大致上是直的，具有以相對於膠封層542的表面545的角度546成一角度的縱向軸線。雖然圖23的橫截面視圖僅示出通過垂直於第一表面545的第一平面的角度546，線接合532也可以在垂直第一平面和表面545的另一平面中相對於第一表面545成一定角度。這樣的角度可以是基本上等於或不同於角度546。換言之，末端536相對於基底534的位移可以在兩個橫向方向，並且可以是在這些方向的各者中的相同或不同的距離。
在一個實施例中，不同的線接合532可以在不同的方向以不同的幅度在整個組件510位移。這樣的排列允許組件510具有與在表面545的水平上相比的表面544的水平上的不同地配置的陣列。例如，陣列可以覆蓋較小的總面積，或比在表面545的水平處的表面544上具有更小的間距。進一步，一些線接合532可以有末端536，該末端位於微電子元件522上方，以容納不同尺寸的封裝微電子元件的堆疊排列。在另一個實施例中，線接合可以藉由包括於此的彎曲部分來實現這樣的橫向位移。這樣的彎曲部分可以形成在線接合形成期間的額外的步驟中，並且可以發生於例如當線部分被拉出到所需長度時。這一步可以利用現有的線接合設備所實現，線接合設備可以包括單一機器上的使用。這樣的彎曲部可以採取各種形狀，根據需要，以達到線接合的末端的預期的位置。例如，彎曲部分可以被形成為各種形狀的S曲線。
圖1-8示出在微電子封裝製造方法的各個步驟中的微電子封 裝10。圖1和2顯示微電子封裝10在微電子元件22已被接合至包括圖案化金屬元件28'的結構的步驟處。該結構可以包括或由在第一和第二橫向方向15、17延伸的金屬或其他的電性傳導材料層所組成，以定義封裝10的通用形狀，如在圖1的平面圖中可以看出。微電子元件22可以使用未完全固化的黏著層或聚合物材料而被組裝(例如，接合)至傳導材料層28'。在一些實施例中，該結構可包括支撐層或裝置(例如，載體)，以支持在製造期間的至少一些步驟中的傳導材料層28'。這樣的支撐層可以在膠封層42形成後而移除。
圖3-5顯示微電子封裝10，該微電子封裝具有在傳導材料層28'的表面30'上的預定位置處連結的線接合32。如所討論的，線接合32可通過加熱區段的末端以軟化末端來應用，使得當壓至傳導元件時，線接合形成了接合至傳導元件28的一沉積，形成基底34。然後在被切斷以形成末端36和線接合32的末端表面38之前，將線拉出自傳導元件28，並且如果需要的話，在一指定的形狀中操作。或者，線接合32可以藉楔形接合由例如鋁線所形成。楔形接合藉由加熱鄰近末端的線的一部分並帶有施加於線的壓力將線沿著傳導元件28拖動。
在圖6-8中，膠封層42藉由塗敷在傳導材料層28'的表面30'上而已被添加到微電子封裝10，膠封層從表面30'向上延伸，並沿著線接合32的邊緣表面。膠封層42也可以沿著微電子元件22的至少一部分延伸，包括微電子元件之前表面、後表面或邊緣表面中至少一個上。在其他實施例中，所述膠封層42可以形成，使得膠封層並沒有接觸微電子元件22的任何部分，例如透過自微電子元件橫向地分隔。膠封層42可藉由沉積膠封劑 而形成，例如，於圖5所示在微電子封裝10的階段上的樹脂。在一個範例中，這可以透過放置封裝10在一具有所希望的膠封層42的形狀的腔室之適當配置的模具中所實現，其中該模具可以接收封裝10。這種模具和與該模具形成膠封層的方法可以如圖所示。另外，膠封層42可以由至少部分順應性(compliant)材料預製成所希望的形狀。在此配置中，介電材料的順應特性允許膠封層42被壓入在線接合32和微電子元件22上方的位置。在這樣一個步驟中，線接合32沿膠封層42接觸邊緣表面之處滲入順應性材料於此形成各自的孔。進一步，微電子元件22可變形該順應性材料，以便微電子元件可以被容納在順應性材料中。該順應性介電材料可以被壓縮以暴露在外表面44上的末端表面38。另外，任何多餘的順應性介電材料可以從膠封層除去，以在線接合32的末端表面38未覆蓋之處上形成表面44。
在一個範例中，膠封層42可形成，使得最初膠封層之表面44是在線接合32的末端表面38上方隔開。為了暴露末端表面38，在末端表面38上方的膠封層42的部分可以被去除，露出大致上與末端表面38齊平的新的表面44，如圖8所示。在另一種選擇，膠封層42可以形成，使得表面44已經大致與末端表面38齊平或者使得表面44定位於末端表面38的下方。如果需要，去除膠封層42的一部分可以通過研磨、乾式蝕刻、雷射蝕刻、濕式蝕刻、抹磨或類似方法來完成。如果需要的話，線接合32的末端36的一部分也可以以相同或額外的步驟除去，以實現與表面44大致齊平之大致上平面的末端表面38。在一個特定的例子中，封裝可以應用於微電子元件22、線接合34和可圖案化傳導元件28'上而不使用模具，並且在封裝應用後，可以去除多餘的膠封劑以暴露線接合的末端表面，例如，但 拋光或上述方法中的一個或多個。
在形成介電質層42之後，傳導材料層28'可以透過化學或機械蝕刻(如雷射蝕刻等)而被圖案化，由除去傳導性材料層28'的部分並留下在所希望的位置中的傳導性材料層之部分和所希望的傳導元件28或跡線31的形式以製造傳導元件28和/或跡線31，如圖9-10所示。這是可以做到去製造線接合32和微電子元件22的接點24之間的選擇性互連或者形成從各自的線接合32偏離的傳導元件28，線接合和微電子元件可以藉由跡線31連接。在一些實施例中，傳導通孔25可形成以帶有微電子接點24的墊形式連接跡線31或傳導特徵28。
如圖11所示，然後封裝10可以被薄化以平坦化表面44和線接合32的末端表面38。這可以包括將表面44上的微電子元件22的表面暴露，也可以包括微電子元件22本身變薄。另外地或可選地，傳導特徵28和/或跡線31可以在表面44上形成，如上面所述，如圖13所示。這可以透過沉積或連結表面44上的傳導層，然後圖案化該層以形成這樣的傳導元件28和跡線31。
圖16和圖17示出了微電子封裝110，該微電子封裝在結構上類似於示於圖9-10，但具有“面朝上(face-up)”的排列的微電子元件122。 在這種排列下，微電子接點124設置朝膠封層142的表面144。進一步，微電子元件122可以藉由暴露於表面144的傳導特徵128和跡線131而與線接合132的圖案連接。如於圖16和17所示，這樣的跡線131和傳導元件128可藉由從表面144延伸到接點124的金屬化通孔125而與微電子接點124連接。
如圖16所示，由暴露在表面144上的跡線131和傳導元件128所實現的路由可以是在封裝110中的唯一的路由，具有經研磨以除去傳導材料層128'(圖15)的表面145，也可以移除進一步的封裝材料、基底134和附著層120的一部分或全部。或者，如圖17所示。電性傳導路由元件也可包括在表面145上，可以是表面145上以陣列排列的可濕性接點的用途或重新分配。在其他例子中，指定的線接合可藉由在表面144上的路由與微電子元件122連接，也可以藉由表面145上的路由依次連接至其他線接合。
圖14和15示出在處理步驟中的微電子封裝110，該微電子封裝可導致於圖16和17所示的完成封裝110的任一者。具體而言，圖14和15示出了具有面朝上接合在傳導材料層128'上的微電子元件122之封裝110。同樣，線接合132已被加入到傳導材料層128'的表面130'，並根據上述處理中的任何一個所形成。另外，膠封層142被沉積在表面130'的露出部分上，以及線接合132和微電子元件122之上，根據上述描述的各種處理中的任何一者。以傳導元件128和跡線131的形式的路由電路然後形成在膠封層142的表面144上以將微電子元件122與線接合132連接，如圖16所示。
在這樣一個點，封裝110可以藉過如上所述的研磨、拋光、抹磨或其他技術而被進一步處理而去除材料導致示於圖16中的封裝110。另外，附加的路由可以透過圖案化傳導材料層128'形成，以形成所希望的配置中的傳導元件128和跡線131，如關於圖9和10的上述描述。
圖18至22示出了如上所述的那些相似的通常結構的封裝之各種排列，但利用複數個微電子元件。在一個實施例中，圖18和圖19示出 微電子封裝210具有以面朝下排列嵌入在膠封層242內的一個微電子元件222A和以面朝上排列的其他微電子元件222B。這樣的封裝210可以利用以在膠封層242的兩個表面244和表面245上相互連接的傳導元件228和跡線231的形式之電性傳導路由電路。此外，指定的線接合232可用於藉連接在每個末端表面35和38上指定的線接合之路由電路電連接微電子元件222A與微電子元件222B，並分別連接至互相微電子元件222A和222B的至少一個接點224。這樣的封裝210可以通過類似關於圖1-17的上述描述之方法所製造。
圖20和圖21示出類似於圖18和19所示的微電子封裝310的排列，但具有在微電子元件322B的面上面朝上排列接合的額外的微電子元件322C。為了便於將微電子元件322B連接至在表面344上的電性傳導路由電路，微電子元件322C可以是小於微電子元件322B或可以從中偏移，使得微電子元件322B的接點324未藉由微電子元件322C所覆蓋。這樣的連接可以通過連接元件接點324的金屬化通孔325或連結至微電子元件322B的接點324且未被在表面344上的膠封層342所覆蓋之額外的線接合362所實現。正如上面所討論，在任何微電子元件322A、322B、322C之間的路由可以透過指定的線接合332以及與線接合332連接的適當配置路由電路331而實現。
在進一步於圖22的例子中，一種微電子封裝件可以是類似於圖18和19所示，但是具有在微電子元件422B的一個或多個接點424之間連接的額外的線接合466(接點配置朝向膠封層442的表面444)和膠封層442的表面445上的路由電路的一部分。在所示的例子中，這樣的線接合 466可以用來實現微電子元件422B和微電子元件422A之間的連接，該連接具有配置朝向膠封層442的表面445的接點424。如圖所示，線接合466可以連結跡線431(或傳導元件，如果需要的話)，跡線進一步連接到電連接微電子元件422A的元件接點424之金屬化通孔425。
雖然於此的本發明參考特定實施例進行了描述，但是應當理解，這些實施例僅僅是本發明的原理和應用之說明。因此，應當理解許多修改可以執行在說明性實施例，而在不脫離由所附申請專利範圍所限定的本發明的精神和範圍的情況下可以設計出其他排列。
10‧‧‧微電子封裝
22‧‧‧微電子元件
31‧‧‧跡線
32‧‧‧線接合
44‧‧‧表面

Claims (30)

  1. 一種用於製造一微電子單元的方法，其包括以下步驟：形成複數個線接合在一第一表面上，該第一表面是包括一可圖案化金屬元件的一結構之一傳導層的一傳導接合表面，該線接合具有連結到該第一表面的基底及遠離該基底且遠離該第一表面的末端表面，該線接合進一步具有在該基底和該末端表面之間延伸的邊緣表面；形成一介電質膠封層在該傳導層的該第一表面的至少一部分上方與該線接合的部分上方，使得該線接合的未膠封的部分藉由末端表面或未由該介電質膠封層所覆蓋的邊緣表面的部分的至少一個所定義；以及然後選擇性圖案化該可圖案化金屬元件以形成藉由至少部分的該介電質膠封層彼此絕緣的第一傳導元件，其中，該線接合中的至少一些設置在該第一傳導元件的頂上。
  2. 根據申請專利範圍第1項的方法，其中，一微電子元件係包含在該微電子單元中且當執行除去部分的該傳導層的步驟時與該傳導層電性連接。
  3. 根據申請專利範圍第2項的方法，其中，形成該介電質膠封層的步驟係與偕同該傳導層電性連接的該微電子元件完成，使得該介電質膠封層至少部分地覆蓋該微電子元件之至少一個表面。
  4. 根據申請專利範圍第2項的方法，其中，該第一傳導元件中的至少一些在該線接合的各自者和該微電子元件之間電性連接。
  5. 根據申請專利範圍第1項的方法，進一步包括形成一再分佈層於該介電質膠封層的該第二表面上方之步驟，該再分佈層包括從該線接合的未 暴露部分的至少一個橫向方向位移之傳導接點。
  6. 根據申請專利範圍第1項的方法，其中，該線接合中的至少一些係形成，使得該線接合的末端表面在從該線接合的基底的一個或多個橫向方向位移。
  7. 根據申請專利範圍第1項的方法，其中，該基底被佈置在具有一第一最小間距的一第一圖案中，其中，該線接合的該未膠封部分係佈置在具有大於該第一最小間距的一第二最小間距的一圖案中。
  8. 根據申請專利範圍第1項的方法，其中，該基底被佈置在具有一第一最小間距的一第一圖案中，其中，該線接合的該未膠封的部分係佈置在具有小於該第一最小間距的一第二最小間距的一圖案中。
  9. 根據申請專利範圍第1項的方法，其中，該線接合的該基底係以球形接合的形式。
  10. 根據申請專利範圍第1項的方法，其中，在該基底與該末端表面之間延伸的該線接合的該邊緣表面為第一邊緣表面部分，其中，該線接合的該基底是沿該第一傳導元件延伸的該邊緣表面的第二部分。
  11. 根據申請專利範圍第1項的方法，進一步包括形成覆蓋該第二介電質層的該第二表面的第二傳導元件，該第二傳導元件中的至少一些係與該線接合的該未膠封部分中的至少一些的個別者連接。
  12. 根據申請專利範圍第1項的方法，其中，選擇性除去部分的該傳導層的步驟包括形成至少一些第一傳導元件，作為接觸墊以電性連接至沒有與該單元中的其他元件電性連接的線接合的基底。
  13. 根據申請專利範圍第1項的方法，進一步包括藉由研磨或拋光中的 一者使該單元變薄之步驟。
  14. 根據申請專利範圍第13項的方法，其中，該介電質膠封層係形成以具有初始厚度，使得該線接合的該末端表面基本上被覆蓋，其中，使該單元變薄的步驟包括：去除部分的該介電質膠封層，使得該末端表面未藉由該介電質膠封層所膠封。
  15. 根據申請專利範圍第1項的方法，其中，形成該介電質膠封層的步驟包括分配一膠封劑到該傳導層的該第一表面和該線接合的至少邊緣表面。
  16. 根據申請專利範圍第2項的方法，其中，形成該介電質膠封層的步驟包括模制一膠封劑以與該傳導層、該線接合的至少邊緣表面以及該微電子元件的至少表面接觸。
  17. 根據申請專利範圍第1項的方法，進一步包括：在執行選擇性去除部分的該傳導層的步驟之前，從相對於該線接合的該傳導層的表面去除一載體。
  18. 根據申請專利範圍第17項的方法，其中，該傳導層具有小於20微米的厚度。
  19. 一種用於製造一微電子封裝的方法，其包括以下步驟：形成複數個線接合在一處理中單元的一傳導層的一第一表面上，該處理中單元具有連結至該處理中單元且電性連接該處理中單元之部分的至少一個微電子元件，該線接合係形成以具有連結到該第一表面的基底和遠離該基底且遠離該第一表面的末端表面，該線接合進一步具有在該基底和該末端表面之間延伸的邊緣表面； 形成介電質膠封層在該傳導層的該第一表面的至少一部分上方，在至少一個該微電子元件的至少一部分的上方，以及在該線接合的部分上方，使得該線接合的未膠封的部分藉由該末端表面或未藉由該介電質膠封層所覆蓋的該線接合之邊緣表面的部分中的至少一個所定義；以及選擇性除去部分的該傳導層，以形成第一傳導元件，其中，該第一傳導元件中的至少一些電性連接該線接合中的至少一些以及該第一傳導元件中的至少一些包括與該微電子元件電性連接的該傳導層的部分中的至少一些。
  20. 一種用於製造一微電子單元的方法，其包括以下步驟：形成複數個線接合在一第一表面上，該第一表面是包括一可圖案化金屬元件的一結構之一傳導層的一傳導接合表面，該線接合具有連結到該第一表面的基底及遠離該基底且遠離該第一表面的末端表面，該線接合進一步具有在該基底和該末端表面之間延伸的邊緣表面，其中，當形成該線接合時，該傳導層包括在至少一些邊緣處的複數個彼此附接的區域；形成一介電質膠封層在該傳導層的該第一表面的至少一部分上方與該線接合的部分上方，使得該線接合的未膠封的部分藉由該末端表面或未由該介電質膠封層所覆蓋的該線接合的邊緣表面的部分的至少一個所定義，其中，當執行選擇性去除部分的該介電質膠封層的步驟時，複數個微電子元件連結到該傳導層，以具有電性連接該傳導層的該區域中的至少一些的每一個的至少一個微電子元件之一處理中單元的形式；然後選擇性圖案化該可圖案化金屬元件以形成藉由至少部分的該介電質膠封層彼此絕緣的第一傳導元件，其中，該線接合中的至少一些設置在 該第一傳導元件的頂上；以及然後該處理中單元分割成複數個微電子單元，各個微電子單元包括該傳導層的該區域的該第一傳導元件和與該第一傳導元件電性連接的至少一個微電子元件。
  21. 一種用於製造一微電子組件的方法，其包括：製造一第一微電子封裝的步驟，包括：形成複數個線接合在一處理中單元的一傳導層的一第一表面上，該處理中單元具有至少一個微電子元件，該微電子元件被連結並且該微電子元件之部分被電性連接，該線接合係形成以具有連結該第一表面的基底和遠離該基底且遠離該第一表面的末端表面，該線接合進一步具有在該基極和該末端表面之間延伸的邊緣表面；形成介電質膠封層在該傳導層的該第一表面的至少一部分上方，在該至少一個微電子元件的至少部分上方，以及該線接合的部分上方，使得該線接合的未膠封的部分藉由該末端表面或未由該介電質膠封層所覆蓋的該線接合之邊緣表面的部分的至少一個所定義；選擇性除去部分的該傳導層，以形成第一傳導元件，其中，該第一傳導元件中的至少一些電性連接該線接合中的至少一些以及該第一傳導元件中的至少一些包括與該微電子元件電性連接的該傳導層的部分中的至少一些；以及連結該第一微電子封裝與覆蓋該第一微電子封裝的該介電質膠封層的該第二表面的第二微電子封裝，該第二微電子封裝包括在該第二微電子封裝之一第一表面處暴露的複數個接點； 其中連結該第一微電子封裝與該第二微電子封裝包括電性連接該第一微電子封裝的該線接合的該未膠封的部分與該第二微電子封裝的該接點。
  22. 一種微電子封裝，包括：至少一個微電子元件；第一傳導元件，包括在該封裝的一安裝表面處暴露的端子，該第一傳導元件中的至少一些透過與該第一傳導元件一體地形成的通孔電性連接到至少一個該微電子元件；線接合，具有連結到該傳導元件的個別者且鄰近一介電質膠封層的該第一表面之基底，以及遠離該基底的末端表面，各個線接合定義在該基底和該末端表面之間延伸的一邊緣表面；該介電質膠封層，具有一第一表面和遠離該第一表面的一第二表面，該第一表面的至少一部分被暴露在該封裝的該安裝表面處，該介電質膠封層填充在該線接合之間的空間，使得該線接合藉由該介電質膠封層彼此分開，其中，該線接合的未膠封的部分藉由在該第二表面處未被該介電質膠封層所覆蓋的該線接合的該邊緣表面的至少一部分所定義。
  23. 根據申請專利範圍第22項的微電子封裝，其中，該線接合的該未膠封的部分中的至少一些係在從該線接合之個別的基底的至少一個橫向方向中位移。
  24. 根據申請專利範圍第22項的微電子封裝，進一步包括一第二微電子元件，其中，該第一微電子元件包括暴露在朝向該介電質層的該第一表面設置之正面的接點，其中，該第二微電子元件包括暴露在朝向該介電質層的該第二表面設置之正面的接點。
  25. 根據申請專利範圍第22項的微電子封裝，進一步包括暴露在該介電質膠封層的該第二表面處的第二傳導元件，其中，該第二傳導元件中的至少一些係在該第二微電子元件的該接點的個別者與該未膠封線接合部分的個別者之間連接。
  26. 根據申請專利範圍第25項的微電子封裝，其中，該第一和第二微電子元件係藉由與該第一微電子元件的至少一個接點和該第二微電子元件的至少一個接點電性連接的至少一個線接合所電性連接。
  27. 根據申請專利範圍第25項的微電子封裝，其中，該第二微電子元件藉由連結在該第二微電子元件的該接點的一者和該第二微電子元件的個別一者之間的一線接合連接該第二傳導元件的一者。
  28. 根據申請專利範圍第22項的微電子封裝，其中，該第一和第二微電子元件藉由連結至該第二微電子元件的一接點與暴露在該介電質膠封層的該第一表面處的該傳導元件的個別一者的線接合電性連接。
  29. 一種微電子組件，包括：一第一微電子封裝，其具有如申請專利範圍第22項的微電子封裝之結構；以及一第二微電子封裝，其包括一微電子元件和暴露於該第二微電子封裝的一表面處的端子，該端子電性連接該微電子元件；其中，該第二微電子封裝覆蓋該第一微電子封裝，且以電性連接到該第一微電子封裝的該線接合的該未膠封的部分中的至少一些的該第二微電子封裝之端子與該第一微電子封裝接合。
  30. 一種微電子系統，包括如申請專利範圍第22項的微電子封裝以及 一個或多個電子構件。
TW102117978A 2012-05-22 2013-05-22 具有線接合互連之無基板可堆疊封裝、製造微電子單元的方法、製造微電子封裝的方法以及製造微電子組件的方法 TWI528477B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/477,532 US8835228B2 (en) 2012-05-22 2012-05-22 Substrate-less stackable package with wire-bond interconnect

Publications (2)

Publication Number Publication Date
TW201401398A TW201401398A (zh) 2014-01-01
TWI528477B true TWI528477B (zh) 2016-04-01

Family

ID=48483250

Family Applications (2)

Application Number Title Priority Date Filing Date
TW104144364A TWI560788B (en) 2012-05-22 2013-05-22 Substrate-less stackable package with wire-bond interconnect, method for making a microelectronic unit, method for making a microelectronic package and method for making a microelectronic assembly
TW102117978A TWI528477B (zh) 2012-05-22 2013-05-22 具有線接合互連之無基板可堆疊封裝、製造微電子單元的方法、製造微電子封裝的方法以及製造微電子組件的方法

Family Applications Before (1)

Application Number Title Priority Date Filing Date
TW104144364A TWI560788B (en) 2012-05-22 2013-05-22 Substrate-less stackable package with wire-bond interconnect, method for making a microelectronic unit, method for making a microelectronic package and method for making a microelectronic assembly

Country Status (7)

Country Link
US (5) US8835228B2 (zh)
EP (1) EP2852974B1 (zh)
JP (1) JP2015517745A (zh)
KR (1) KR20150012285A (zh)
CN (1) CN104520987B (zh)
TW (2) TWI560788B (zh)
WO (1) WO2013177134A1 (zh)

Families Citing this family (62)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101053079A (zh) 2004-11-03 2007-10-10 德塞拉股份有限公司 堆叠式封装的改进
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US7994622B2 (en) * 2007-04-16 2011-08-09 Tessera, Inc. Microelectronic packages having cavities for receiving microelectric elements
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US20120146206A1 (en) 2010-12-13 2012-06-14 Tessera Research Llc Pin attachment
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US8836136B2 (en) 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9653442B2 (en) * 2014-01-17 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and methods of forming same
US9735134B2 (en) 2014-03-12 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with through-vias having tapered ends
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9412806B2 (en) 2014-06-13 2016-08-09 Invensas Corporation Making multilayer 3D capacitors using arrays of upstanding rods or ridges
US9373585B2 (en) 2014-09-17 2016-06-21 Invensas Corporation Polymer member based interconnect
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9570385B2 (en) 2015-01-22 2017-02-14 Invensas Corporation Method for fabrication of interconnection circuitry with electrically conductive features passing through a support and comprising core portions formed using nanoparticle-containing inks
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9666514B2 (en) 2015-04-14 2017-05-30 Invensas Corporation High performance compliant substrate
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
JP6690142B2 (ja) * 2015-07-09 2020-04-28 大日本印刷株式会社 貫通電極基板、貫通電極基板の製造方法及び貫通電極基板を用いたインターポーザ
CN105140213B (zh) * 2015-09-24 2019-01-11 中芯长电半导体（江阴）有限公司 一种芯片封装结构及封装方法
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10332854B2 (en) * 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
DE102015118664B4 (de) * 2015-10-30 2024-06-27 Infineon Technologies Ag Verfahren zur herstellung eines leistungshalbleitermoduls
US10043779B2 (en) 2015-11-17 2018-08-07 Invensas Corporation Packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9852994B2 (en) * 2015-12-14 2017-12-26 Invensas Corporation Embedded vialess bridges
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
KR102576085B1 (ko) 2016-10-10 2023-09-06 삼성전자주식회사 반도체 패키지
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
CN106898557B (zh) * 2017-03-03 2019-06-18 中芯长电半导体（江阴）有限公司 集成有供电传输***的封装件的封装方法
IT201700055983A1 (it) 2017-05-23 2018-11-23 St Microelectronics Srl Procedimento per produrre dispositivi a semiconduttore, dispositivo a semiconduttore e circuito corrispondenti
CN108962868B (zh) * 2017-05-25 2020-07-03 矽品精密工业股份有限公司 封装结构及其制法
US10943869B2 (en) * 2017-06-09 2021-03-09 Apple Inc. High density interconnection using fanout interposer chiplet
US10515912B2 (en) * 2017-09-24 2019-12-24 Intel Corporation Integrated circuit packages
US10742217B2 (en) 2018-04-12 2020-08-11 Apple Inc. Systems and methods for implementing a scalable system
FR3083920A1 (fr) * 2018-07-13 2020-01-17 Linxens Holding Procede de fabrication de boitiers de composant electronique et boitier de composant electronique obtenu par ce procede
US11348863B2 (en) 2018-12-12 2022-05-31 Stmicroelectronics, Inc. Semiconductor package having a semiconductor die on a plated conductive layer
US11328995B2 (en) * 2019-03-04 2022-05-10 Kabushiki Kaisha Toshiba Semiconductor device
TWI685066B (zh) * 2019-03-26 2020-02-11 力成科技股份有限公司 無基板半導體封裝結構及其製法
TWI791881B (zh) * 2019-08-16 2023-02-11 矽品精密工業股份有限公司 電子封裝件及其組合式基板與製法
US11158608B2 (en) * 2019-09-25 2021-10-26 Powertech Technology Inc. Semiconductor package including offset stack of semiconductor dies between first and second redistribution structures, and manufacturing method therefor

Family Cites Families (815)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2230663A (en) 1940-01-18 1941-02-04 Alden Milton Electric contact and wire assembly mechanism
DE1439262B2 (de) 1963-07-23 1972-03-30 Siemens AG, 1000 Berlin u. 8000 München Verfahren zum kontaktieren von halbleiterbauelementen durch thermokompression
US3358897A (en) 1964-03-31 1967-12-19 Tempress Res Co Electric lead wire bonding tools
US3430835A (en) 1966-06-07 1969-03-04 Westinghouse Electric Corp Wire bonding apparatus for microelectronic components
US3623649A (en) 1969-06-09 1971-11-30 Gen Motors Corp Wedge bonding tool for the attachment of semiconductor leads
DE2119567C2 (de) 1970-05-05 1983-07-14 International Computers Ltd., London Elektrische Verbindungsvorrichtung und Verfahren zu ihrer Herstellung
DE2228703A1 (de) 1972-06-13 1974-01-10 Licentia Gmbh Verfahren zum herstellen einer vorgegebenen lotschichtstaerke bei der fertigung von halbleiterbauelementen
JPS5150661Y2 (zh) 1972-11-22 1976-12-06
JPS5150661A (zh) 1974-10-30 1976-05-04 Hitachi Ltd
US4072816A (en) 1976-12-13 1978-02-07 International Business Machines Corporation Integrated circuit package
US4067104A (en) 1977-02-24 1978-01-10 Rockwell International Corporation Method of fabricating an array of flexible metallic interconnects for coupling microelectronics components
US4213556A (en) 1978-10-02 1980-07-22 General Motors Corporation Method and apparatus to detect automatic wire bonder failure
US4327860A (en) 1980-01-03 1982-05-04 Kulicke And Soffa Ind. Inc. Method of making slack free wire interconnections
US4422568A (en) 1981-01-12 1983-12-27 Kulicke And Soffa Industries, Inc. Method of making constant bonding wire tail lengths
US4437604A (en) 1982-03-15 1984-03-20 Kulicke & Soffa Industries, Inc. Method of making fine wire interconnections
JPS59189069A (ja) 1983-04-12 1984-10-26 Alps Electric Co Ltd 電気部品の端子のハンダ塗布装置
JPS61125062A (ja) 1984-11-22 1986-06-12 Hitachi Ltd ピン取付け方法およびピン取付け装置
US4667267A (en) 1985-01-22 1987-05-19 Rogers Corporation Decoupling capacitor for pin grid array package
US4604644A (en) 1985-01-28 1986-08-05 International Business Machines Corporation Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making
US4642889A (en) 1985-04-29 1987-02-17 Amp Incorporated Compliant interconnection and method therefor
JPS61269345A (ja) 1985-05-24 1986-11-28 Hitachi Ltd 半導体装置
JP2608701B2 (ja) 1985-09-19 1997-05-14 三菱電機株式会社 保護装置の点検回路
US5917707A (en) 1993-11-16 1999-06-29 Formfactor, Inc. Flexible contact structure with an electrically conductive shell
US5476211A (en) 1993-11-16 1995-12-19 Form Factor, Inc. Method of manufacturing electrical contacts, using a sacrificial member
US4716049A (en) 1985-12-20 1987-12-29 Hughes Aircraft Company Compressive pedestal for microminiature connections
US4924353A (en) 1985-12-20 1990-05-08 Hughes Aircraft Company Connector system for coupling to an integrated circuit chip
JPS62158338A (ja) 1985-12-28 1987-07-14 Tanaka Denshi Kogyo Kk 半導体装置
US4793814A (en) 1986-07-21 1988-12-27 Rogers Corporation Electrical circuit board interconnect
US4695870A (en) 1986-03-27 1987-09-22 Hughes Aircraft Company Inverted chip carrier
JPS62226307A (ja) 1986-03-28 1987-10-05 Toshiba Corp ロボツト装置
US4771930A (en) 1986-06-30 1988-09-20 Kulicke And Soffa Industries Inc. Apparatus for supplying uniform tail lengths
JPS6397941A (ja) 1986-10-14 1988-04-28 Fuji Photo Film Co Ltd 感光材料
US4955523A (en) 1986-12-17 1990-09-11 Raychem Corporation Interconnection of electronic components
DE3703694A1 (de) 1987-02-06 1988-08-18 Dynapert Delvotec Gmbh Ball-bondverfahren und vorrichtung zur durchfuehrung derselben
JP2642359B2 (ja) 1987-09-11 1997-08-20 株式会社日立製作所 半導体装置
US5138438A (en) 1987-06-24 1992-08-11 Akita Electronics Co. Ltd. Lead connections means for stacked tab packaged IC chips
KR970003915B1 (ko) 1987-06-24 1997-03-22 미다 가쓰시게 반도체 기억장치 및 그것을 사용한 반도체 메모리 모듈
JPS6412769A (en) 1987-07-07 1989-01-17 Sony Corp Correction circuit for image distortion
US4804132A (en) 1987-08-28 1989-02-14 Difrancesco Louis Method for cold bonding
US4867267A (en) 1987-10-14 1989-09-19 Industrial Research Products, Inc. Hearing aid transducer
US4845354A (en) 1988-03-08 1989-07-04 International Business Machines Corporation Process control for laser wire bonding
JPH01313969A (ja) 1988-06-13 1989-12-19 Hitachi Ltd 半導体装置
US4998885A (en) 1989-10-27 1991-03-12 International Business Machines Corporation Elastomeric area array interposer
US5077598A (en) 1989-11-08 1991-12-31 Hewlett-Packard Company Strain relief flip-chip integrated circuit assembly with test fixturing
US5095187A (en) 1989-12-20 1992-03-10 Raychem Corporation Weakening wire supplied through a wire bonder
CA2034703A1 (en) 1990-01-23 1991-07-24 Masanori Nishiguchi Substrate for packaging a semiconductor device
AU637874B2 (en) 1990-01-23 1993-06-10 Sumitomo Electric Industries, Ltd. Substrate for packaging a semiconductor device
US5948533A (en) 1990-02-09 1999-09-07 Ormet Corporation Vertically interconnected electronic assemblies and compositions useful therefor
US5376403A (en) 1990-02-09 1994-12-27 Capote; Miguel A. Electrically conductive compositions and methods for the preparation and use thereof
US5083697A (en) 1990-02-14 1992-01-28 Difrancesco Louis Particle-enhanced joining of metal surfaces
US4975079A (en) 1990-02-23 1990-12-04 International Business Machines Corp. Connector assembly for chip testing
US4999472A (en) 1990-03-12 1991-03-12 Neinast James E Electric arc system for ablating a surface coating
US5241456A (en) 1990-07-02 1993-08-31 General Electric Company Compact high density interconnect structure
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
US5679977A (en) 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5148266A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
US5067382A (en) 1990-11-02 1991-11-26 Cray Computer Corporation Method and apparatus for notching a lead wire attached to an IC chip to facilitate severing the wire
KR940001149B1 (ko) 1991-04-16 1994-02-14 삼성전자 주식회사 반도체 장치의 칩 본딩 방법
JPH04346436A (ja) 1991-05-24 1992-12-02 Fujitsu Ltd バンプ製造方法とバンプ製造装置
US5316788A (en) 1991-07-26 1994-05-31 International Business Machines Corporation Applying solder to high density substrates
US5203075A (en) 1991-08-12 1993-04-20 Inernational Business Machines Method of bonding flexible circuit to cicuitized substrate to provide electrical connection therebetween using different solders
US5133495A (en) 1991-08-12 1992-07-28 International Business Machines Corporation Method of bonding flexible circuit to circuitized substrate to provide electrical connection therebetween
WO1993004375A1 (en) 1991-08-23 1993-03-04 Nchip, Inc. Burn-in technologies for unpackaged integrated circuits
US5220489A (en) 1991-10-11 1993-06-15 Motorola, Inc. Multicomponent integrated circuit package
JP3137134B2 (ja) 1991-11-19 2001-02-19 ノードバーグ日本株式会社 移動式クラッシャ
US5238173A (en) 1991-12-04 1993-08-24 Kaijo Corporation Wire bonding misattachment detection apparatus and that detection method in a wire bonder
JP2931936B2 (ja) 1992-01-17 1999-08-09 株式会社日立製作所 半導体装置用リードフレームの製造方法及び半導体装置用リードフレーム並びに樹脂封止型半導体装置
US5241454A (en) 1992-01-22 1993-08-31 International Business Machines Corporation Mutlilayered flexible circuit package
US5831836A (en) 1992-01-30 1998-11-03 Lsi Logic Power plane for semiconductor device
US5222014A (en) 1992-03-02 1993-06-22 Motorola, Inc. Three-dimensional multi-chip pad array carrier
US5438224A (en) 1992-04-23 1995-08-01 Motorola, Inc. Integrated circuit package having a face-to-face IC chip arrangement
US5494667A (en) 1992-06-04 1996-02-27 Kabushiki Kaisha Hayahibara Topically applied hair restorer containing pine extract
AU4782293A (en) 1992-07-24 1994-02-14 Tessera, Inc. Semiconductor connection components and methods with releasable lead support
US5977618A (en) 1992-07-24 1999-11-02 Tessera, Inc. Semiconductor connection components and methods with releasable lead support
US6054756A (en) 1992-07-24 2000-04-25 Tessera, Inc. Connection components with frangible leads and bus
US20050062492A1 (en) 2001-08-03 2005-03-24 Beaman Brian Samuel High density integrated circuit apparatus, test probe and methods of use thereof
US6295729B1 (en) 1992-10-19 2001-10-02 International Business Machines Corporation Angled flying lead wire bonding process
US5371654A (en) 1992-10-19 1994-12-06 International Business Machines Corporation Three dimensional high performance interconnection package
JP2716336B2 (ja) 1993-03-10 1998-02-18 日本電気株式会社 集積回路装置
JPH06268101A (ja) 1993-03-17 1994-09-22 Hitachi Ltd 半導体装置及びその製造方法、電子装置、リ−ドフレ−ム並びに実装基板
US5340771A (en) 1993-03-18 1994-08-23 Lsi Logic Corporation Techniques for providing high I/O count connections to semiconductor dies
US7368924B2 (en) 1993-04-30 2008-05-06 International Business Machines Corporation Probe structure having a plurality of discrete insulated probe tips projecting from a support surface, apparatus for use thereof and methods of fabrication thereof
US5811982A (en) 1995-11-27 1998-09-22 International Business Machines Corporation High density cantilevered probe for electronic devices
US20030048108A1 (en) 1993-04-30 2003-03-13 Beaman Brian Samuel Structural design and processes to control probe position accuracy in a wafer test probe assembly
JPH06333931A (ja) 1993-05-20 1994-12-02 Nippondenso Co Ltd 半導体装置における微細電極の製造方法
JP2981385B2 (ja) 1993-09-06 1999-11-22 シャープ株式会社 チップ部品型ｌｅｄの構造及びその製造方法
US5346118A (en) 1993-09-28 1994-09-13 At&T Bell Laboratories Surface mount solder assembly of leadless integrated circuit packages to substrates
US6835898B2 (en) 1993-11-16 2004-12-28 Formfactor, Inc. Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures
US6741085B1 (en) 1993-11-16 2004-05-25 Formfactor, Inc. Contact carriers (tiles) for populating larger substrates with spring contacts
US5455390A (en) 1994-02-01 1995-10-03 Tessera, Inc. Microelectronics unit mounting with multiple lead bonding
EP1213754A3 (en) 1994-03-18 2005-05-25 Hitachi Chemical Co., Ltd. Fabrication process of semiconductor package and semiconductor package
US5578869A (en) 1994-03-29 1996-11-26 Olin Corporation Components for housing an integrated circuit device
US5615824A (en) 1994-06-07 1997-04-01 Tessera, Inc. Soldering with resilient contacts
US5802699A (en) 1994-06-07 1998-09-08 Tessera, Inc. Methods of assembling microelectronic assembly with socket for engaging bump leads
JPH07335783A (ja) 1994-06-13 1995-12-22 Fujitsu Ltd 半導体装置及び半導体装置ユニット
US5468995A (en) 1994-07-05 1995-11-21 Motorola, Inc. Semiconductor device having compliant columnar electrical connections
US6828668B2 (en) 1994-07-07 2004-12-07 Tessera, Inc. Flexible lead structures and methods of making same
US5518964A (en) 1994-07-07 1996-05-21 Tessera, Inc. Microelectronic mounting with multiple lead deformation and bonding
US6117694A (en) 1994-07-07 2000-09-12 Tessera, Inc. Flexible lead structures and methods of making same
US6177636B1 (en) 1994-12-29 2001-01-23 Tessera, Inc. Connection components with posts
US5989936A (en) 1994-07-07 1999-11-23 Tessera, Inc. Microelectronic assembly fabrication with terminal formation from a conductive layer
US5688716A (en) 1994-07-07 1997-11-18 Tessera, Inc. Fan-out semiconductor chip assembly
US5656550A (en) 1994-08-24 1997-08-12 Fujitsu Limited Method of producing a semicondutor device having a lead portion with outer connecting terminal
US5659952A (en) 1994-09-20 1997-08-26 Tessera, Inc. Method of fabricating compliant interface for semiconductor chip
US5541567A (en) 1994-10-17 1996-07-30 International Business Machines Corporation Coaxial vias in an electronic substrate
US5495667A (en) 1994-11-07 1996-03-05 Micron Technology, Inc. Method for forming contact pins for semiconductor dice and interconnects
DE69535629T2 (de) 1994-11-15 2008-07-31 Formfactor, Inc., Livermore Montage von elektronischen komponenten auf einer leiterplatte
US6826827B1 (en) 1994-12-29 2004-12-07 Tessera, Inc. Forming conductive posts by selective removal of conductive material
JP2833522B2 (ja) 1995-04-27 1998-12-09 日本電気株式会社 半導体装置
US5736074A (en) 1995-06-30 1998-04-07 Micro Fab Technologies, Inc. Manufacture of coated spheres
US5971253A (en) 1995-07-31 1999-10-26 Tessera, Inc. Microelectronic component mounting with deformable shell terminals
US5872051A (en) 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate
US5886412A (en) 1995-08-16 1999-03-23 Micron Technology, Inc. Angularly offset and recessed stacked die multichip device
US5874781A (en) 1995-08-16 1999-02-23 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
US5810609A (en) 1995-08-28 1998-09-22 Tessera, Inc. Socket for engaging bump leads on a microelectronic device and methods therefor
US5766987A (en) 1995-09-22 1998-06-16 Tessera, Inc. Microelectronic encapsulation methods and equipment
US6211572B1 (en) 1995-10-31 2001-04-03 Tessera, Inc. Semiconductor chip package with fan-in leads
JPH09134934A (ja) 1995-11-07 1997-05-20 Sumitomo Metal Ind Ltd 半導体パッケージ及び半導体装置
JP3332308B2 (ja) 1995-11-07 2002-10-07 新光電気工業株式会社 半導体装置及びその製造方法
US5718361A (en) 1995-11-21 1998-02-17 International Business Machines Corporation Apparatus and method for forming mold for metallic material
US5731709A (en) 1996-01-26 1998-03-24 Motorola, Inc. Method for testing a ball grid array semiconductor device and a device for such testing
US7166495B2 (en) 1996-02-20 2007-01-23 Micron Technology, Inc. Method of fabricating a multi-die semiconductor package assembly
US5994152A (en) 1996-02-21 1999-11-30 Formfactor, Inc. Fabricating interconnects and tips using sacrificial substrates
JP3146345B2 (ja) 1996-03-11 2001-03-12 アムコー テクノロジー コリア インコーポレーティド バンプチップスケール半導体パッケージのバンプ形成方法
US6000126A (en) 1996-03-29 1999-12-14 General Dynamics Information Systems, Inc. Method and apparatus for connecting area grid arrays to printed wire board
US6821821B2 (en) 1996-04-18 2004-11-23 Tessera, Inc. Methods for manufacturing resistors using a sacrificial layer
DE19618227A1 (de) 1996-05-07 1997-11-13 Herbert Streckfus Gmbh Verfahren und Vorrichtung zum Verlöten von elektronischen Bauelementen auf einer Leiterplatte
KR100186333B1 (ko) 1996-06-20 1999-03-20 문정환 칩 사이즈 반도체 패키지 및 그 제조방법
EP2270845A3 (en) 1996-10-29 2013-04-03 Invensas Corporation Integrated circuits and methods for their fabrication
JPH10135220A (ja) 1996-10-29 1998-05-22 Taiyo Yuden Co Ltd バンプ形成方法
JPH10135221A (ja) 1996-10-29 1998-05-22 Taiyo Yuden Co Ltd バンプ形成方法
US6492719B2 (en) 1999-07-30 2002-12-10 Hitachi, Ltd. Semiconductor device
US5976913A (en) 1996-12-12 1999-11-02 Tessera, Inc. Microelectronic mounting with multiple lead deformation using restraining straps
US6133072A (en) 1996-12-13 2000-10-17 Tessera, Inc. Microelectronic connector with planar elastomer sockets
US6054337A (en) 1996-12-13 2000-04-25 Tessera, Inc. Method of making a compliant multichip package
US6225688B1 (en) 1997-12-11 2001-05-01 Tessera, Inc. Stacked microelectronic assembly and method therefor
US6121676A (en) 1996-12-13 2000-09-19 Tessera, Inc. Stacked microelectronic assembly and method therefor
US5736785A (en) 1996-12-20 1998-04-07 Industrial Technology Research Institute Semiconductor package for improving the capability of spreading heat
JP3400279B2 (ja) 1997-01-13 2003-04-28 株式会社新川 バンプ形成方法
US5898991A (en) 1997-01-16 1999-05-04 International Business Machines Corporation Methods of fabrication of coaxial vias and magnetic devices
US5839191A (en) 1997-01-24 1998-11-24 Unisys Corporation Vibrating template method of placing solder balls on the I/O pads of an integrated circuit package
JPH1118364A (ja) 1997-06-27 1999-01-22 Matsushita Electric Ind Co Ltd キャプスタンモータ
KR100543836B1 (ko) 1997-08-19 2006-01-23 가부시키가이샤 히타치세이사쿠쇼 멀티칩 모듈 구조체 및 그 제작 방법
CA2213590C (en) 1997-08-21 2006-11-07 Keith C. Carroll Flexible circuit connector and method of making same
JP3859318B2 (ja) 1997-08-29 2006-12-20 シチズン電子株式会社 電子回路のパッケージ方法
US6525414B2 (en) 1997-09-16 2003-02-25 Matsushita Electric Industrial Co., Ltd. Semiconductor device including a wiring board and semiconductor elements mounted thereon
JP3937265B2 (ja) 1997-09-29 2007-06-27 エルピーダメモリ株式会社 半導体装置
JP3262531B2 (ja) 1997-10-02 2002-03-04 インターナショナル・ビジネス・マシーンズ・コーポレーション 曲げられたフライング・リード・ワイヤ・ボンデイング・プロセス
JP2978861B2 (ja) 1997-10-28 1999-11-15 九州日本電気株式会社 モールドｂｇａ型半導体装置及びその製造方法
US6038136A (en) 1997-10-29 2000-03-14 Hestia Technologies, Inc. Chip package with molded underfill
JP3393800B2 (ja) 1997-11-05 2003-04-07 新光電気工業株式会社 半導体装置の製造方法
JPH11219984A (ja) 1997-11-06 1999-08-10 Sharp Corp 半導体装置パッケージおよびその製造方法ならびにそのための回路基板
US6222136B1 (en) 1997-11-12 2001-04-24 International Business Machines Corporation Printed circuit board with continuous connective bumps
US6002168A (en) 1997-11-25 1999-12-14 Tessera, Inc. Microelectronic component with rigid interposer
US6038133A (en) 1997-11-25 2000-03-14 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module and method for producing the same
JPH11163022A (ja) 1997-11-28 1999-06-18 Sony Corp 半導体装置、その製造方法及び電子機器
US6124546A (en) 1997-12-03 2000-09-26 Advanced Micro Devices, Inc. Integrated circuit chip package and method of making the same
US6260264B1 (en) 1997-12-08 2001-07-17 3M Innovative Properties Company Methods for making z-axis electrical connections
US6052287A (en) 1997-12-09 2000-04-18 Sandia Corporation Silicon ball grid array chip carrier
US5973391A (en) 1997-12-11 1999-10-26 Read-Rite Corporation Interposer with embedded circuitry and method for using the same to package microelectronic units
JPH11220082A (ja) 1998-02-03 1999-08-10 Oki Electric Ind Co Ltd 半導体装置
JP3536650B2 (ja) 1998-02-27 2004-06-14 富士ゼロックス株式会社 バンプ形成方法および装置
JPH11260856A (ja) 1998-03-11 1999-09-24 Matsushita Electron Corp 半導体装置及びその製造方法並びに半導体装置の実装構造
US5933713A (en) 1998-04-06 1999-08-03 Micron Technology, Inc. Method of forming overmolded chip scale package and resulting product
US6222276B1 (en) 1998-04-07 2001-04-24 International Business Machines Corporation Through-chip conductors for low inductance chip-to-chip integration and off-chip connections
KR100260997B1 (ko) 1998-04-08 2000-07-01 마이클 디. 오브라이언 반도체패키지
US6329224B1 (en) 1998-04-28 2001-12-11 Tessera, Inc. Encapsulation of microelectronic assemblies
US6180881B1 (en) 1998-05-05 2001-01-30 Harlan Ruben Isaak Chip stack and method of making same
JPH11330134A (ja) 1998-05-12 1999-11-30 Hitachi Ltd ワイヤボンディング方法およびその装置並びに半導体装置
KR100266693B1 (ko) 1998-05-30 2000-09-15 김영환 적층가능한 비지에이 반도체 칩 패키지 및 그 제조방법
US5977640A (en) 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
KR100265563B1 (ko) 1998-06-29 2000-09-15 김영환 볼 그리드 어레이 패키지 및 그의 제조 방법
US6414391B1 (en) 1998-06-30 2002-07-02 Micron Technology, Inc. Module assembly for stacked BGA packages with a common bus bar in the assembly
US6164523A (en) 1998-07-01 2000-12-26 Semiconductor Components Industries, Llc Electronic component and method of manufacture
US5854507A (en) 1998-07-21 1998-12-29 Hewlett-Packard Company Multiple chip assembly
US6399426B1 (en) 1998-07-21 2002-06-04 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
US6515355B1 (en) 1998-09-02 2003-02-04 Micron Technology, Inc. Passivation layer for packaged integrated circuits
JP2000091383A (ja) 1998-09-07 2000-03-31 Ngk Spark Plug Co Ltd 配線基板
US6194250B1 (en) 1998-09-14 2001-02-27 Motorola, Inc. Low-profile microelectronic package
US6158647A (en) 1998-09-29 2000-12-12 Micron Technology, Inc. Concave face wire bond capillary
US6684007B2 (en) 1998-10-09 2004-01-27 Fujitsu Limited Optical coupling structures and the fabrication processes
JP2000311915A (ja) 1998-10-14 2000-11-07 Texas Instr Inc <Ti> 半導体デバイス及びボンディング方法
JP3407275B2 (ja) 1998-10-28 2003-05-19 インターナショナル・ビジネス・マシーンズ・コーポレーション バンプ及びその形成方法
US6332270B2 (en) 1998-11-23 2001-12-25 International Business Machines Corporation Method of making high density integral test probe
US6255126B1 (en) 1998-12-02 2001-07-03 Formfactor, Inc. Lithographic contact elements
EP1156520A4 (en) 1999-01-29 2004-08-25 Matsushita Electric Ind Co Ltd METHOD AND DEVICE FOR MOUNTING ELECTRONIC PARTS
US6206273B1 (en) 1999-02-17 2001-03-27 International Business Machines Corporation Structures and processes to create a desired probetip contact geometry on a wafer test probe
KR100319609B1 (ko) 1999-03-09 2002-01-05 김영환 와이어 어래이드 칩 사이즈 패키지 및 그 제조방법
US6177729B1 (en) 1999-04-03 2001-01-23 International Business Machines Corporation Rolling ball connector
US6211574B1 (en) 1999-04-16 2001-04-03 Advanced Semiconductor Engineering Inc. Semiconductor package with wire protection and method therefor
JP2000323516A (ja) * 1999-05-14 2000-11-24 Fujitsu Ltd 配線基板の製造方法及び配線基板及び半導体装置
US6258625B1 (en) 1999-05-18 2001-07-10 International Business Machines Corporation Method of interconnecting electronic components using a plurality of conductive studs
US6376769B1 (en) 1999-05-18 2002-04-23 Amerasia International Technology, Inc. High-density electronic package, and method for making same
JP3398721B2 (ja) 1999-05-20 2003-04-21 アムコー テクノロジー コリア インコーポレーティド 半導体パッケージ及びその製造方法
US6238949B1 (en) 1999-06-18 2001-05-29 National Semiconductor Corporation Method and apparatus for forming a plastic chip on chip package module
JP4367730B2 (ja) 1999-06-25 2009-11-18 株式会社エンプラス Ｉｃソケット及び該ｉｃソケットのバネ手段
US6228687B1 (en) 1999-06-28 2001-05-08 Micron Technology, Inc. Wafer-level package and methods of fabricating
TW417839U (en) 1999-07-30 2001-01-01 Shen Ming Tung Stacked memory module structure and multi-layered stacked memory module structure using the same
JP2010192928A (ja) 1999-08-12 2010-09-02 Fujitsu Semiconductor Ltd 半導体装置及びその製造方法
US6168965B1 (en) 1999-08-12 2001-01-02 Tower Semiconductor Ltd. Method for making backside illuminated image sensor
JP4526651B2 (ja) 1999-08-12 2010-08-18 富士通セミコンダクター株式会社 半導体装置
US6319764B1 (en) 1999-08-25 2001-11-20 Micron Technology, Inc. Method of forming haze-free BST films
US6724638B1 (en) 1999-09-02 2004-04-20 Ibiden Co., Ltd. Printed wiring board and method of producing the same
US6867499B1 (en) 1999-09-30 2005-03-15 Skyworks Solutions, Inc. Semiconductor packaging
JP3513444B2 (ja) 1999-10-20 2004-03-31 株式会社新川 ピン状ワイヤ等の形成方法
JP2001127246A (ja) 1999-10-29 2001-05-11 Fujitsu Ltd 半導体装置
US6362525B1 (en) 1999-11-09 2002-03-26 Cypress Semiconductor Corp. Circuit structure including a passive element formed within a grid array substrate and method for making the same
JP3619410B2 (ja) 1999-11-18 2005-02-09 株式会社ルネサステクノロジ バンプ形成方法およびそのシステム
JP3798597B2 (ja) 1999-11-30 2006-07-19 富士通株式会社 半導体装置
JP3566156B2 (ja) 1999-12-02 2004-09-15 株式会社新川 ピン状ワイヤ等の形成方法
US6790757B1 (en) 1999-12-20 2004-09-14 Agere Systems Inc. Wire bonding method for copper interconnects in semiconductor devices
KR100426494B1 (ko) 1999-12-20 2004-04-13 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 이것의 제조방법
KR20010061849A (ko) 1999-12-29 2001-07-07 박종섭 웨이퍼 레벨 패키지
JP2001196407A (ja) 2000-01-14 2001-07-19 Seiko Instruments Inc 半導体装置および半導体装置の形成方法
US6710454B1 (en) 2000-02-16 2004-03-23 Micron Technology, Inc. Adhesive layer for an electronic apparatus having multiple semiconductor devices
JP2001319992A (ja) 2000-02-28 2001-11-16 Shinko Electric Ind Co Ltd 配線基板、半導体装置及びそれらの製造方法
JP2001339011A (ja) 2000-03-24 2001-12-07 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
JP3980807B2 (ja) 2000-03-27 2007-09-26 株式会社東芝 半導体装置及び半導体モジュール
JP2001274196A (ja) 2000-03-28 2001-10-05 Rohm Co Ltd 半導体装置
US6581276B2 (en) 2000-04-04 2003-06-24 Amerasia International Technology, Inc. Fine-pitch flexible connector, and method for making same
KR100583491B1 (ko) 2000-04-07 2006-05-24 앰코 테크놀로지 코리아 주식회사 반도체패키지 및 그 제조방법
US6578754B1 (en) 2000-04-27 2003-06-17 Advanpack Solutions Pte. Ltd. Pillar connections for semiconductor chips and method of manufacture
US6531335B1 (en) 2000-04-28 2003-03-11 Micron Technology, Inc. Interposers including upwardly protruding dams, semiconductor device assemblies including the interposers, and methods
JP2001326236A (ja) 2000-05-12 2001-11-22 Nec Kyushu Ltd 半導体装置の製造方法
JP2001326304A (ja) 2000-05-15 2001-11-22 Toshiba Corp 半導体装置及びその製造方法
US6522018B1 (en) 2000-05-16 2003-02-18 Micron Technology, Inc. Ball grid array chip packages having improved testing and stacking characteristics
US6647310B1 (en) 2000-05-30 2003-11-11 Advanced Micro Devices, Inc. Temperature control of an integrated circuit
US6531784B1 (en) 2000-06-02 2003-03-11 Amkor Technology, Inc. Semiconductor package with spacer strips
US6717245B1 (en) 2000-06-02 2004-04-06 Micron Technology, Inc. Chip scale packages performed by wafer level processing
US6395199B1 (en) 2000-06-07 2002-05-28 Graftech Inc. Process for providing increased conductivity to a material
US6560117B2 (en) 2000-06-28 2003-05-06 Micron Technology, Inc. Packaged microelectronic die assemblies and methods of manufacture
US6525413B1 (en) 2000-07-12 2003-02-25 Micron Technology, Inc. Die to die connection method and assemblies and packages including dice so connected
US6476583B2 (en) 2000-07-21 2002-11-05 Jomahip, Llc Automatic battery charging system for a battery back-up DC power supply
JP2002050871A (ja) * 2000-08-02 2002-02-15 Casio Comput Co Ltd ビルドアップ回路基板およびその製造方法
SE517086C2 (sv) 2000-08-08 2002-04-09 Ericsson Telefon Ab L M Förfarande för säkring av lodkulor och eventuella komponenter, vilka är fästa på en och samma sida av ett substrat
US20020020898A1 (en) 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US6462575B1 (en) 2000-08-28 2002-10-08 Micron Technology, Inc. Method and system for wafer level testing and burning-in semiconductor components
JP2002076250A (ja) 2000-08-29 2002-03-15 Nec Corp 半導体装置
US6614103B1 (en) 2000-09-01 2003-09-02 General Electric Company Plastic packaging of LED arrays
JP3874062B2 (ja) 2000-09-05 2007-01-31 セイコーエプソン株式会社 半導体装置
US6507104B2 (en) 2000-09-07 2003-01-14 Siliconware Precision Industries Co., Ltd. Semiconductor package with embedded heat-dissipating device
US7009297B1 (en) 2000-10-13 2006-03-07 Bridge Semiconductor Corporation Semiconductor chip assembly with embedded metal particle
US6423570B1 (en) * 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
US6538336B1 (en) 2000-11-14 2003-03-25 Rambus Inc. Wirebond assembly for high-speed integrated circuits
JP4505983B2 (ja) 2000-12-01 2010-07-21 日本電気株式会社 半導体装置
JP3798620B2 (ja) 2000-12-04 2006-07-19 富士通株式会社 半導体装置の製造方法
US6734539B2 (en) 2000-12-27 2004-05-11 Lucent Technologies Inc. Stacked module package
TW511405B (en) 2000-12-27 2002-11-21 Matsushita Electric Ind Co Ltd Device built-in module and manufacturing method thereof
KR100393102B1 (ko) 2000-12-29 2003-07-31 앰코 테크놀로지 코리아 주식회사 스택형 반도체패키지
AUPR244801A0 (en) 2001-01-10 2001-02-01 Silverbrook Research Pty Ltd A method and apparatus (WSM01)
US6388322B1 (en) 2001-01-17 2002-05-14 Aralight, Inc. Article comprising a mechanically compliant bump
US6653170B1 (en) 2001-02-06 2003-11-25 Charles W. C. Lin Semiconductor chip assembly with elongated wire ball bonded to chip and electrolessly plated to support circuit
US6472743B2 (en) 2001-02-22 2002-10-29 Siliconware Precision Industries, Co., Ltd. Semiconductor package with heat dissipating structure
KR100401020B1 (ko) 2001-03-09 2003-10-08 앰코 테크놀로지 코리아 주식회사 반도체칩의 스택킹 구조 및 이를 이용한 반도체패키지
JP2002280414A (ja) 2001-03-22 2002-09-27 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2002289769A (ja) 2001-03-26 2002-10-04 Matsushita Electric Ind Co Ltd 積層型半導体装置およびその製造方法
JP2008118152A (ja) * 2001-03-26 2008-05-22 Nec Electronics Corp 半導体装置および積層型半導体装置
SG108245A1 (en) 2001-03-30 2005-01-28 Micron Technology Inc Ball grid array interposer, packages and methods
DE60137972D1 (de) 2001-04-12 2009-04-23 Matsushita Electric Works Ltd Lichtquellenbauelement mit led und verfahren zu seiner herstellung
US7115986B2 (en) 2001-05-02 2006-10-03 Micron Technology, Inc. Flexible ball grid array chip scale packages
US6825552B2 (en) * 2001-05-09 2004-11-30 Tessera, Inc. Connection components with anisotropic conductive material interconnection
TW544826B (en) 2001-05-18 2003-08-01 Nec Electronics Corp Flip-chip-type semiconductor device and manufacturing method thereof
US6930256B1 (en) 2002-05-01 2005-08-16 Amkor Technology, Inc. Integrated circuit substrate having laser-embedded conductive patterns and method therefor
US6900528B2 (en) 2001-06-21 2005-05-31 Micron Technology, Inc. Stacked mass storage flash memory package
US6754407B2 (en) 2001-06-26 2004-06-22 Intel Corporation Flip-chip package integrating optical and electrical devices and coupling to a waveguide on a board
US20030006494A1 (en) 2001-07-03 2003-01-09 Lee Sang Ho Thin profile stackable semiconductor package and method for manufacturing
US6486545B1 (en) 2001-07-26 2002-11-26 Amkor Technology, Inc. Pre-drilled ball grid array package
US6765287B1 (en) 2001-07-27 2004-07-20 Charles W. C. Lin Three-dimensional stacked semiconductor package
US6451626B1 (en) 2001-07-27 2002-09-17 Charles W.C. Lin Three-dimensional stacked semiconductor package
JP4023159B2 (ja) 2001-07-31 2007-12-19 ソニー株式会社 半導体装置の製造方法及び積層半導体装置の製造方法
US6550666B2 (en) 2001-08-21 2003-04-22 Advanpack Solutions Pte Ltd Method for forming a flip chip on leadframe semiconductor package
US7605479B2 (en) 2001-08-22 2009-10-20 Tessera, Inc. Stacked chip assembly with encapsulant layer
US7176506B2 (en) 2001-08-28 2007-02-13 Tessera, Inc. High frequency chip packages with connecting elements
SG117395A1 (en) 2001-08-29 2005-12-29 Micron Technology Inc Wire bonded microelectronic device assemblies and methods of manufacturing same
US6864166B1 (en) 2001-08-29 2005-03-08 Micron Technology, Inc. Method of manufacturing wire bonded microelectronic device assemblies
US6787926B2 (en) 2001-09-05 2004-09-07 Taiwan Semiconductor Manufacturing Co., Ltd Wire stitch bond on an integrated circuit bond pad and method of making the same
US20030057544A1 (en) 2001-09-13 2003-03-27 Nathan Richard J. Integrated assembly protocol
US6476506B1 (en) 2001-09-28 2002-11-05 Motorola, Inc. Packaged semiconductor with multiple rows of bond pads and method therefor
AU2002337834A1 (en) 2001-10-09 2003-04-22 Tessera, Inc. Stacked packages
US6977440B2 (en) 2001-10-09 2005-12-20 Tessera, Inc. Stacked packages
JP2003122611A (ja) 2001-10-11 2003-04-25 Oki Electric Ind Co Ltd データ提供方法及びサーバ装置
JP4257771B2 (ja) 2001-10-16 2009-04-22 シンジーテック株式会社 導電性ブレード
JP3875077B2 (ja) 2001-11-16 2007-01-31 富士通株式会社 電子デバイス及びデバイス接続方法
US20030094666A1 (en) 2001-11-16 2003-05-22 R-Tec Corporation Interposer
JP2003174124A (ja) 2001-12-04 2003-06-20 Sainekkusu:Kk 半導体装置の外部電極形成方法
KR100435813B1 (ko) 2001-12-06 2004-06-12 삼성전자주식회사 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법
JP2003197668A (ja) 2001-12-10 2003-07-11 Senmao Koochii Kofun Yugenkoshi 半導体パッケージ用のボンディングワイヤ及びその製造方法
JP3507059B2 (ja) 2002-06-27 2004-03-15 沖電気工業株式会社 積層マルチチップパッケージ
JP2003197669A (ja) 2001-12-28 2003-07-11 Seiko Epson Corp ボンディング方法及びボンディング装置
TW584950B (en) 2001-12-31 2004-04-21 Megic Corp Chip packaging structure and process thereof
TW548816B (en) 2002-01-23 2003-08-21 Via Tech Inc Formation method of conductor pillar
JP3935370B2 (ja) 2002-02-19 2007-06-20 セイコーエプソン株式会社 バンプ付き半導体素子の製造方法、半導体装置及びその製造方法、回路基板並びに電子機器
SG115456A1 (en) 2002-03-04 2005-10-28 Micron Technology Inc Semiconductor die packages with recessed interconnecting structures and methods for assembling the same
DE10209922A1 (de) 2002-03-07 2003-10-02 Infineon Technologies Ag Elektronisches Modul, Nutzen mit zu vereinzelnden elektronischen Modulen und Verfahren zu deren Herstellung
US6653723B2 (en) 2002-03-09 2003-11-25 Fujitsu Limited System for providing an open-cavity low profile encapsulated semiconductor package
KR100452819B1 (ko) 2002-03-18 2004-10-15 삼성전기주식회사 칩 패키지 및 그 제조방법
US6979230B2 (en) 2002-03-20 2005-12-27 Gabe Cherian Light socket
JP2003318327A (ja) 2002-04-22 2003-11-07 Mitsui Chemicals Inc プリント配線板および積層パッケージ
US7323767B2 (en) 2002-04-25 2008-01-29 Micron Technology, Inc. Standoffs for centralizing internals in packaging process
US7633765B1 (en) 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
US7078822B2 (en) 2002-06-25 2006-07-18 Intel Corporation Microelectronic device interconnects
US6906415B2 (en) 2002-06-27 2005-06-14 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor devices and methods
JP4601892B2 (ja) 2002-07-04 2010-12-22 ラムバス・インコーポレーテッド 半導体装置および半導体チップのバンプ製造方法
JP2004047702A (ja) 2002-07-11 2004-02-12 Toshiba Corp 半導体装置積層モジュール
US6756252B2 (en) 2002-07-17 2004-06-29 Texas Instrument Incorporated Multilayer laser trim interconnect method
US6987032B1 (en) 2002-07-19 2006-01-17 Asat Ltd. Ball grid array package and process for manufacturing same
US7943436B2 (en) 2002-07-29 2011-05-17 Synopsys, Inc. Integrated circuit devices and methods and apparatuses for designing integrated circuit devices
JP4072816B2 (ja) * 2002-08-08 2008-04-09 太陽誘電株式会社 複合モジュール及びその製造方法
TW549592U (en) 2002-08-16 2003-08-21 Via Tech Inc Integrated circuit package with a balanced-part structure
US7053485B2 (en) 2002-08-16 2006-05-30 Tessera, Inc. Microelectronic packages with self-aligning features
US6740546B2 (en) 2002-08-21 2004-05-25 Micron Technology, Inc. Packaged microelectronic devices and methods for assembling microelectronic devices
US6964881B2 (en) 2002-08-27 2005-11-15 Micron Technology, Inc. Multi-chip wafer level system packages and methods of forming same
JP3765778B2 (ja) 2002-08-29 2006-04-12 ローム株式会社 ワイヤボンディング用キャピラリ及びこれを用いたワイヤボンディング方法
JP2004095799A (ja) 2002-08-30 2004-03-25 Toshiba Corp 半導体装置およびその製造方法
US20040041757A1 (en) 2002-09-04 2004-03-04 Ming-Hsiang Yang Light emitting diode display module with high heat-dispersion and the substrate thereof
US7294928B2 (en) 2002-09-06 2007-11-13 Tessera, Inc. Components, methods and assemblies for stacked packages
US7246431B2 (en) 2002-09-06 2007-07-24 Tessera, Inc. Methods of making microelectronic packages including folded substrates
US7071547B2 (en) 2002-09-11 2006-07-04 Tessera, Inc. Assemblies having stacked semiconductor chips and methods of making same
US7229906B2 (en) 2002-09-19 2007-06-12 Kulicke And Soffa Industries, Inc. Method and apparatus for forming bumps for semiconductor interconnections using a wire bonding machine
AU2003273342A1 (en) 2002-09-30 2004-04-23 Advanced Interconnect Technologies Limited Thermal enhanced package for block mold assembly
US7045884B2 (en) 2002-10-04 2006-05-16 International Rectifier Corporation Semiconductor device package
US7061088B2 (en) 2002-10-08 2006-06-13 Chippac, Inc. Semiconductor stacked multi-package module having inverted second package
US6989122B1 (en) 2002-10-17 2006-01-24 National Semiconductor Corporation Techniques for manufacturing flash-free contacts on a semiconductor package
TW567601B (en) 2002-10-18 2003-12-21 Siliconware Precision Industries Co Ltd Module device of stacked semiconductor package and method for fabricating the same
TWI221664B (en) 2002-11-07 2004-10-01 Via Tech Inc Structure of chip package and process thereof
JP2004172157A (ja) 2002-11-15 2004-06-17 Shinko Electric Ind Co Ltd 半導体パッケージおよびパッケージスタック半導体装置
US20050176233A1 (en) 2002-11-15 2005-08-11 Rajeev Joshi Wafer-level chip scale package and method for fabricating and using the same
JP2004172477A (ja) 2002-11-21 2004-06-17 Kaijo Corp ワイヤループ形状、そのワイヤループ形状を備えた半導体装置、ワイヤボンディング方法及び半導体製造装置
JP4464041B2 (ja) 2002-12-13 2010-05-19 キヤノン株式会社 柱状構造体、柱状構造体を有する電極、及びこれらの作製方法
JP2004200316A (ja) 2002-12-17 2004-07-15 Shinko Electric Ind Co Ltd 半導体装置
US20050161814A1 (en) 2002-12-27 2005-07-28 Fujitsu Limited Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus
KR100621991B1 (ko) 2003-01-03 2006-09-13 삼성전자주식회사 칩 스케일 적층 패키지
JP2004221257A (ja) 2003-01-14 2004-08-05 Seiko Epson Corp ワイヤボンディング方法及びワイヤボンディング装置
WO2004077525A2 (en) 2003-02-25 2004-09-10 Tessera, Inc. Ball grid array with bumps
TW583757B (en) 2003-02-26 2004-04-11 Advanced Semiconductor Eng A structure of a flip-chip package and a process thereof
US20040217471A1 (en) 2003-02-27 2004-11-04 Tessera, Inc. Component and assemblies with ends offset downwardly
JP3885747B2 (ja) 2003-03-13 2007-02-28 株式会社デンソー ワイヤボンディング方法
SG137651A1 (en) * 2003-03-14 2007-12-28 Micron Technology Inc Microelectronic devices and methods for packaging microelectronic devices
JP2004343030A (ja) 2003-03-31 2004-12-02 North:Kk 配線回路基板とその製造方法とその配線回路基板を備えた回路モジュール
JP2004319892A (ja) 2003-04-18 2004-11-11 Renesas Technology Corp 半導体装置の製造方法
JP2004327855A (ja) 2003-04-25 2004-11-18 Nec Electronics Corp 半導体装置およびその製造方法
JP4199588B2 (ja) 2003-04-25 2008-12-17 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド 配線回路基板の製造方法、及び、この配線回路基板を用いた半導体集積回路装置の製造方法
DE10320646A1 (de) 2003-05-07 2004-09-16 Infineon Technologies Ag Elektronisches Bauteil, sowie Systemträger und Nutzen zur Herstellung desselben
JP4145730B2 (ja) 2003-06-17 2008-09-03 松下電器産業株式会社 半導体内蔵モジュール
US20040262728A1 (en) 2003-06-30 2004-12-30 Sterrett Terry L. Modular device assemblies
KR100604821B1 (ko) 2003-06-30 2006-07-26 삼성전자주식회사 적층형 볼 그리드 어레이 패키지 및 그 제조방법
JP2005033141A (ja) 2003-07-11 2005-02-03 Sony Corp 半導体装置及びその製造方法、疑似ウェーハ及びその製造方法、並びに半導体装置の実装構造
US7227095B2 (en) 2003-08-06 2007-06-05 Micron Technology, Inc. Wire bonders and methods of wire-bonding
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
KR100546374B1 (ko) 2003-08-28 2006-01-26 삼성전자주식회사 센터 패드를 갖는 적층형 반도체 패키지 및 그 제조방법
US7372151B1 (en) 2003-09-12 2008-05-13 Asat Ltd. Ball grid array package and process for manufacturing same
JP2005093551A (ja) 2003-09-12 2005-04-07 Genusion:Kk 半導体装置のパッケージ構造およびパッケージ化方法
JP3999720B2 (ja) 2003-09-16 2007-10-31 沖電気工業株式会社 半導体装置およびその製造方法
US7061096B2 (en) 2003-09-24 2006-06-13 Silicon Pipe, Inc. Multi-surface IC packaging structures and methods for their manufacture
US7224056B2 (en) 2003-09-26 2007-05-29 Tessera, Inc. Back-face and edge interconnects for lidded package
US7462936B2 (en) 2003-10-06 2008-12-09 Tessera, Inc. Formation of circuitry with modification of feature height
US7495179B2 (en) 2003-10-06 2009-02-24 Tessera, Inc. Components with posts and pads
JP4272968B2 (ja) 2003-10-16 2009-06-03 エルピーダメモリ株式会社 半導体装置および半導体チップ制御方法
JP4167965B2 (ja) 2003-11-07 2008-10-22 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド 配線回路用部材の製造方法
KR100564585B1 (ko) 2003-11-13 2006-03-28 삼성전자주식회사 이중 스택된 ｂｇａ 패키지 및 다중 스택된 ｂｇａ 패키지
TWI227555B (en) 2003-11-17 2005-02-01 Advanced Semiconductor Eng Structure of chip package and the process thereof
KR100621992B1 (ko) 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
JP2005183923A (ja) 2003-11-28 2005-07-07 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US7345361B2 (en) 2003-12-04 2008-03-18 Intel Corporation Stackable integrated circuit packaging
JP2005175019A (ja) 2003-12-08 2005-06-30 Sharp Corp 半導体装置及び積層型半導体装置
US8970049B2 (en) 2003-12-17 2015-03-03 Chippac, Inc. Multiple chip package module having inverted package stacked over die
DE10360708B4 (de) 2003-12-19 2008-04-10 Infineon Technologies Ag Halbleitermodul mit einem Halbleiterstapel, Umverdrahtungsplatte, und Verfahren zur Herstellung derselben
JP4334996B2 (ja) 2003-12-24 2009-09-30 株式会社フジクラ 多層配線板用基材、両面配線板およびそれらの製造方法
US7495644B2 (en) 2003-12-26 2009-02-24 Semiconductor Energy Laboratory Co., Ltd. Display device and method for manufacturing display device
JP3917133B2 (ja) 2003-12-26 2007-05-23 株式会社東芝 インターフェイスモジュール付ｌｓｉパッケージ及びそれに用いるインターポーザ、インターフェイスモジュール、接続モニタ回路、信号処理ｌｓｉ
US6900530B1 (en) 2003-12-29 2005-05-31 Ramtek Technology, Inc. Stacked IC
US6917098B1 (en) 2003-12-29 2005-07-12 Texas Instruments Incorporated Three-level leadframe for no-lead packages
US8207604B2 (en) 2003-12-30 2012-06-26 Tessera, Inc. Microelectronic package comprising offset conductive posts on compliant layer
US7709968B2 (en) 2003-12-30 2010-05-04 Tessera, Inc. Micro pin grid array with pin motion isolation
US7176043B2 (en) 2003-12-30 2007-02-13 Tessera, Inc. Microelectronic packages and methods therefor
JP2005203497A (ja) 2004-01-14 2005-07-28 Toshiba Corp 半導体装置およびその製造方法
US20050173807A1 (en) 2004-02-05 2005-08-11 Jianbai Zhu High density vertically stacked semiconductor device
US8399972B2 (en) 2004-03-04 2013-03-19 Skyworks Solutions, Inc. Overmolded semiconductor package with a wirebond cage for EMI shielding
US7198987B1 (en) 2004-03-04 2007-04-03 Skyworks Solutions, Inc. Overmolded semiconductor package with an integrated EMI and RFI shield
US7095105B2 (en) 2004-03-23 2006-08-22 Texas Instruments Incorporated Vertically stacked semiconductor device
JP4484035B2 (ja) 2004-04-06 2010-06-16 セイコーエプソン株式会社 半導体装置の製造方法
US8092734B2 (en) 2004-05-13 2012-01-10 Aptina Imaging Corporation Covers for microelectronic imagers and methods for wafer-level packaging of microelectronics imagers
US7629695B2 (en) 2004-05-20 2009-12-08 Kabushiki Kaisha Toshiba Stacked electronic component and manufacturing method thereof
US6962864B1 (en) 2004-05-26 2005-11-08 National Chung Cheng University Wire-bonding method for chips with copper interconnects by introducing a thin layer
US7233057B2 (en) 2004-05-28 2007-06-19 Nokia Corporation Integrated circuit package with optimized mold shape
TWI255022B (en) 2004-05-31 2006-05-11 Via Tech Inc Circuit carrier and manufacturing process thereof
US7453157B2 (en) 2004-06-25 2008-11-18 Tessera, Inc. Microelectronic packages and methods therefor
TWI250596B (en) 2004-07-23 2006-03-01 Ind Tech Res Inst Wafer-level chip scale packaging method
JP3956965B2 (ja) 2004-09-07 2007-08-08 日立エーアイシー株式会社 チップ部品型発光装置及びそのための配線基板
US7290448B2 (en) 2004-09-10 2007-11-06 Yamaha Corporation Physical quantity sensor, lead frame, and manufacturing method therefor
CN1755929B (zh) 2004-09-28 2010-08-18 飞思卡尔半导体（中国）有限公司 形成半导体封装及其结构的方法
JP4385329B2 (ja) 2004-10-08 2009-12-16 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
US7595548B2 (en) 2004-10-08 2009-09-29 Yamaha Corporation Physical quantity sensor and manufacturing method therefor
JP4671802B2 (ja) 2004-10-18 2011-04-20 富士通株式会社 めっき方法、半導体装置の製造方法及び回路基板の製造方法
US20060087013A1 (en) 2004-10-21 2006-04-27 Etron Technology, Inc. Stacked multiple integrated circuit die package assembly
EP2039460A3 (de) 2004-11-02 2014-07-02 HID Global GmbH Verlegevorrichtung, Kontaktiervorrichtung, Zustellsystem, Verlege- und Kontaktiereinheit, herstellungsanlage, Verfahren zur Herstellung und eine Transpondereinheit
CN101053079A (zh) 2004-11-03 2007-10-10 德塞拉股份有限公司 堆叠式封装的改进
TW200631111A (en) 2004-11-04 2006-09-01 Koninkl Philips Electronics Nv Nanotube-based circuit connection approach
US7750483B1 (en) 2004-11-10 2010-07-06 Bridge Semiconductor Corporation Semiconductor chip assembly with welded metal pillar and enlarged plated contact terminal
US7268421B1 (en) 2004-11-10 2007-09-11 Bridge Semiconductor Corporation Semiconductor chip assembly with welded metal pillar that includes enlarged ball bond
JP4917257B2 (ja) 2004-11-12 2012-04-18 浜松ホトニクス株式会社 レーザ加工方法
KR100674926B1 (ko) 2004-12-08 2007-01-26 삼성전자주식회사 메모리 카드 및 그 제조 방법
US7301770B2 (en) 2004-12-10 2007-11-27 International Business Machines Corporation Cooling apparatus, cooled electronic module, and methods of fabrication thereof employing thermally conductive, wire-bonded pin fins
JP4504798B2 (ja) 2004-12-16 2010-07-14 パナソニック株式会社 多段構成半導体モジュール
JP2006186086A (ja) 2004-12-27 2006-07-13 Itoo:Kk プリント基板のはんだ付け方法およびブリッジ防止用ガイド板
KR100843137B1 (ko) 2004-12-27 2008-07-02 삼성전자주식회사 반도체 소자 패키지
DE102005006333B4 (de) 2005-02-10 2007-10-18 Infineon Technologies Ag Halbleiterbauteil mit mehreren Bondanschlüssen und gebondeten Kontaktelementen unterschiedlicher Metallzusammensetzung und Verfahren zur Herstellung desselben
DE102005006995B4 (de) 2005-02-15 2008-01-24 Infineon Technologies Ag Halbleiterbauteil mit Kunstoffgehäuse und Außenanschlüssen sowie Verfahren zur Herstellung desselben
KR100867038B1 (ko) 2005-03-02 2008-11-04 삼성전기주식회사 커패시터 내장형 인쇄회로기판 및 그 제조방법
KR100630741B1 (ko) 2005-03-04 2006-10-02 삼성전자주식회사 다중 몰딩에 의한 적층형 반도체 패키지 및 그 제조방법
US7939934B2 (en) 2005-03-16 2011-05-10 Tessera, Inc. Microelectronic packages and methods therefor
US20060216868A1 (en) 2005-03-25 2006-09-28 Advanced Semiconductor Engineering Inc. Package structure and fabrication thereof
US7582963B2 (en) 2005-03-29 2009-09-01 Texas Instruments Incorporated Vertically integrated system-in-a-package
US7371676B2 (en) 2005-04-08 2008-05-13 Micron Technology, Inc. Method for fabricating semiconductor components with through wire interconnects
US7815323B2 (en) 2005-05-04 2010-10-19 Lang-Mekra North America, Llc Mirror stabilizer arm connector assembly
TWI284394B (en) 2005-05-12 2007-07-21 Advanced Semiconductor Eng Lid used in package structure and the package structure of having the same
JP2006324553A (ja) 2005-05-20 2006-11-30 Renesas Technology Corp 半導体装置及びその製造方法
US7528474B2 (en) 2005-05-31 2009-05-05 Stats Chippac Ltd. Stacked semiconductor package assembly having hollowed substrate
US7216794B2 (en) 2005-06-09 2007-05-15 Texas Instruments Incorporated Bond capillary design for ribbon wire bonding
JP4322844B2 (ja) 2005-06-10 2009-09-02 シャープ株式会社 半導体装置および積層型半導体装置
CN100550367C (zh) 2005-07-01 2009-10-14 皇家飞利浦电子股份有限公司 电子器件
TWI294757B (en) 2005-07-06 2008-03-11 Delta Electronics Inc Circuit board with a through hole wire, and forming method thereof
US7476608B2 (en) 2005-07-14 2009-01-13 Hewlett-Packard Development Company, L.P. Electrically connecting substrate with electrical device
JP4787559B2 (ja) 2005-07-26 2011-10-05 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US7355289B2 (en) 2005-07-29 2008-04-08 Freescale Semiconductor, Inc. Packaged integrated circuit with enhanced thermal dissipation
TWI263313B (en) 2005-08-15 2006-10-01 Phoenix Prec Technology Corp Stack structure of semiconductor component embedded in supporting board
SG130055A1 (en) 2005-08-19 2007-03-20 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
SG130066A1 (en) 2005-08-26 2007-03-20 Micron Technology Inc Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices
JP5522561B2 (ja) 2005-08-31 2014-06-18 マイクロン テクノロジー， インク． マイクロ電子デバイスパッケージ、積重ね型マイクロ電子デバイスパッケージ、およびマイクロ電子デバイスを製造する方法
US7485969B2 (en) 2005-09-01 2009-02-03 Micron Technology, Inc. Stacked microelectronic devices and methods for manufacturing microelectronic devices
US7675152B2 (en) 2005-09-01 2010-03-09 Texas Instruments Incorporated Package-on-package semiconductor assembly
US20070080360A1 (en) 2005-10-06 2007-04-12 Url Mirsky Microelectronic interconnect substrate and packaging techniques
KR101241650B1 (ko) 2005-10-19 2013-03-08 엘지이노텍 주식회사 엘이디 패키지
US7504716B2 (en) 2005-10-26 2009-03-17 Texas Instruments Incorporated Structure and method of molded QFN device suitable for miniaturization, multiple rows and stacking
US8810031B2 (en) 2005-10-26 2014-08-19 Industrial Technology Research Institute Wafer-to-wafer stack with supporting pedestal
JP2007123595A (ja) 2005-10-28 2007-05-17 Nec Corp 半導体装置及びその実装構造
TW200733272A (en) 2005-11-01 2007-09-01 Koninkl Philips Electronics Nv Methods of packaging a semiconductor die and die package formed by the methods
JP4530975B2 (ja) 2005-11-14 2010-08-25 株式会社新川 ワイヤボンディング方法
JP2007142042A (ja) 2005-11-16 2007-06-07 Sharp Corp 半導体パッケージとその製造方法，半導体モジュール，および電子機器
US7344917B2 (en) 2005-11-30 2008-03-18 Freescale Semiconductor, Inc. Method for packaging a semiconductor device
US7307348B2 (en) 2005-12-07 2007-12-11 Micron Technology, Inc. Semiconductor components having through wire interconnects (TWI)
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US7378726B2 (en) 2005-12-28 2008-05-27 Intel Corporation Stacked packages with interconnecting pins
JP4530984B2 (ja) 2005-12-28 2010-08-25 株式会社新川 ワイヤボンディング装置、ボンディング制御プログラム及びボンディング方法
JP2007194436A (ja) 2006-01-19 2007-08-02 Elpida Memory Inc 半導体パッケージ、導電性ポスト付き基板、積層型半導体装置、半導体パッケージの製造方法及び積層型半導体装置の製造方法
US20070190747A1 (en) 2006-01-23 2007-08-16 Tessera Technologies Hungary Kft. Wafer level packaging to lidded chips
JP2007201254A (ja) * 2006-01-27 2007-08-09 Ibiden Co Ltd 半導体素子内蔵基板、半導体素子内蔵型多層回路基板
JP2007208159A (ja) 2006-02-06 2007-08-16 Hitachi Ltd 半導体装置
SG135074A1 (en) 2006-02-28 2007-09-28 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
JP2007214238A (ja) * 2006-02-08 2007-08-23 Toshiba Corp 半導体装置およびその製造方法
TWI295115B (en) 2006-02-13 2008-03-21 Ind Tech Res Inst Encapsulation and methods thereof
JP2007234845A (ja) 2006-03-01 2007-09-13 Nec Corp 半導体装置
US7876180B2 (en) 2006-03-09 2011-01-25 Kyocera Corporation Waveguide forming apparatus, dielectric waveguide forming apparatus, pin structure, and high frequency circuit
JP4949719B2 (ja) 2006-04-07 2012-06-13 ラピスセミコンダクタ株式会社 半導体装置及びその製造方法
US7390700B2 (en) 2006-04-07 2008-06-24 Texas Instruments Incorporated Packaged system of semiconductor chips having a semiconductor interposer
US7759782B2 (en) 2006-04-07 2010-07-20 Tessera, Inc. Substrate for a microelectronic package and method of fabricating thereof
WO2007116544A1 (ja) 2006-04-10 2007-10-18 Murata Manufacturing Co., Ltd. 複合基板及び複合基板の製造方法
JP5598787B2 (ja) 2006-04-17 2014-10-01 マイクロンメモリジャパン株式会社 積層型半導体装置の製造方法
US7242081B1 (en) 2006-04-24 2007-07-10 Advanced Semiconductor Engineering Inc. Stacked package structure
US7659612B2 (en) 2006-04-24 2010-02-09 Micron Technology, Inc. Semiconductor components having encapsulated through wire interconnects (TWI)
DE102006022360B4 (de) 2006-05-12 2009-07-09 Infineon Technologies Ag Abschirmvorrichtung
US7910385B2 (en) 2006-05-12 2011-03-22 Micron Technology, Inc. Method of fabricating microelectronic devices
US7780064B2 (en) 2006-06-02 2010-08-24 Asm Technology Singapore Pte Ltd Wire bonding method for forming low-loop profiles
JP4961848B2 (ja) 2006-06-12 2012-06-27 日本電気株式会社 金属ポストを有する配線基板、半導体装置及び半導体装置モジュールの製造方法
US7967062B2 (en) 2006-06-16 2011-06-28 International Business Machines Corporation Thermally conductive composite interface, cooled electronic assemblies employing the same, and methods of fabrication thereof
US20070290325A1 (en) 2006-06-16 2007-12-20 Lite-On Semiconductor Corporation Surface mounting structure and packaging method thereof
TWM303516U (en) 2006-06-23 2006-12-21 Advanced Connectek Inc Card connector
TWM306727U (en) 2006-06-26 2007-02-21 Hon Hai Prec Ind Co Ltd Electrical card connector
WO2008014633A1 (en) 2006-06-29 2008-02-07 Intel Corporation Apparatus, system, and method for wireless connection in integrated circuit packages
KR100792352B1 (ko) 2006-07-06 2008-01-08 삼성전기주식회사 패키지 온 패키지의 바텀기판 및 그 제조방법
US7612638B2 (en) 2006-07-14 2009-11-03 Taiwan Semiconductor Manufacturing Co., Ltd. Waveguides in integrated circuits
SG139573A1 (en) 2006-07-17 2008-02-29 Micron Technology Inc Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods
KR100800478B1 (ko) 2006-07-18 2008-02-04 삼성전자주식회사 적층형 반도체 패키지 및 그의 제조방법
US20080023805A1 (en) 2006-07-26 2008-01-31 Texas Instruments Incorporated Array-Processed Stacked Semiconductor Packages
JP5132101B2 (ja) 2006-07-27 2013-01-30 新光電気工業株式会社 スタックパッケージ構造体及びその製造に用いる単体パッケージと、それらの製造方法
US8048479B2 (en) 2006-08-01 2011-11-01 Qimonda Ag Method for placing material onto a target board by means of a transfer board
JP2008039502A (ja) 2006-08-03 2008-02-21 Alps Electric Co Ltd 接触子およびその製造方法
US7486525B2 (en) 2006-08-04 2009-02-03 International Business Machines Corporation Temporary chip attach carrier
KR100809696B1 (ko) 2006-08-08 2008-03-06 삼성전자주식회사 사이즈가 상이한 복수의 반도체 칩이 적층된 멀티 칩패키지 및 그 제조방법
US20080042265A1 (en) 2006-08-15 2008-02-21 Merilo Leo A Chip scale module package in bga semiconductor package
US7425758B2 (en) 2006-08-28 2008-09-16 Micron Technology, Inc. Metal core foldover package structures
US7560360B2 (en) 2006-08-30 2009-07-14 International Business Machines Corporation Methods for enhancing trench capacitance and trench capacitor
KR20080020069A (ko) 2006-08-30 2008-03-05 삼성전자주식회사 반도체 패키지 및 그 제조방법
KR100891516B1 (ko) 2006-08-31 2009-04-06 주식회사 하이닉스반도체 적층 가능한 에프비지에이 타입 반도체 패키지와 이를이용한 적층 패키지
US7683460B2 (en) 2006-09-22 2010-03-23 Infineon Technologies Ag Module with a shielding and/or heat dissipating element
KR100770934B1 (ko) 2006-09-26 2007-10-26 삼성전자주식회사 반도체 패키지와 그를 이용한 반도체 시스템 패키지
TWI336502B (en) 2006-09-27 2011-01-21 Advanced Semiconductor Eng Semiconductor package and semiconductor device and the method of making the same
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
TWI312561B (en) 2006-10-27 2009-07-21 Advanced Semiconductor Eng Structure of package on package and method for fabricating the same
KR100817073B1 (ko) 2006-11-03 2008-03-26 삼성전자주식회사 휨방지용 보강부재가 기판에 연결된 반도체 칩 스택 패키지
US8174119B2 (en) * 2006-11-10 2012-05-08 Stats Chippac, Ltd. Semiconductor package with embedded die
US8193034B2 (en) 2006-11-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure using stud bumps
WO2008065896A1 (fr) 2006-11-28 2008-06-05 Kyushu Institute Of Technology Procédé de fabrication d'un dispositif semi-conducteur ayant une structure d'électrode à double face et dispositif semi-conducteur fabriqué par le procédé
US7659617B2 (en) 2006-11-30 2010-02-09 Tessera, Inc. Substrate for a flexible microelectronic assembly and a method of fabricating thereof
US7537962B2 (en) 2006-12-22 2009-05-26 Stats Chippac Ltd. Method of fabricating a shielded stacked integrated circuit package system
US8598717B2 (en) 2006-12-27 2013-12-03 Spansion Llc Semiconductor device and method for manufacturing the same
JP2008166439A (ja) 2006-12-27 2008-07-17 Spansion Llc 半導体装置およびその製造方法
DE102007062787A1 (de) 2006-12-29 2008-07-17 Qimonda Ag Kupferdrahtbonden auf organischen Lötschutzmaterialien
KR100757345B1 (ko) 2006-12-29 2007-09-10 삼성전자주식회사 플립 칩 패키지 및 그의 제조 방법
US20080156518A1 (en) 2007-01-03 2008-07-03 Tessera, Inc. Alignment and cutting of microelectronic substrates
TWI332702B (en) 2007-01-09 2010-11-01 Advanced Semiconductor Eng Stackable semiconductor package and the method for making the same
JP5347222B2 (ja) 2007-01-10 2013-11-20 富士通株式会社 半導体装置の製造方法
US7719122B2 (en) 2007-01-11 2010-05-18 Taiwan Semiconductor Manufacturing Co., Ltd. System-in-package packaging for minimizing bond wire contamination and yield loss
KR100827667B1 (ko) 2007-01-16 2008-05-07 삼성전자주식회사 기판 내에 반도체 칩을 갖는 반도체 패키지 및 이를제조하는 방법
JP5120266B6 (ja) 2007-01-31 2018-06-27 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP4823089B2 (ja) 2007-01-31 2011-11-24 株式会社東芝 積層型半導体装置の製造方法
US8685792B2 (en) 2007-03-03 2014-04-01 Stats Chippac Ltd. Integrated circuit package system with interposer
CN101675516B (zh) 2007-03-05 2012-06-20 数字光学欧洲有限公司 具有通过过孔连接到前侧触头的后侧触头的芯片
US20080217708A1 (en) 2007-03-09 2008-09-11 Skyworks Solutions, Inc. Integrated passive cap in a system-in-package
JP5010316B2 (ja) 2007-03-16 2012-08-29 日本電気株式会社 金属ポストを有する配線基板、半導体装置
US7517733B2 (en) 2007-03-22 2009-04-14 Stats Chippac, Ltd. Leadframe design for QFN package with top terminal leads
US8183684B2 (en) 2007-03-23 2012-05-22 Semiconductor Components Industries, Llc Semiconductor device and method of manufacturing the same
US8198716B2 (en) 2007-03-26 2012-06-12 Intel Corporation Die backside wire bond technology for single or stacked die package
US20100103634A1 (en) 2007-03-30 2010-04-29 Takuo Funaya Functional-device-embedded circuit board, method for manufacturing the same, and electronic equipment
JP4926787B2 (ja) 2007-03-30 2012-05-09 アオイ電子株式会社 半導体装置の製造方法
US20080246126A1 (en) 2007-04-04 2008-10-09 Freescale Semiconductor, Inc. Stacked and shielded die packages with interconnects
US7589394B2 (en) 2007-04-10 2009-09-15 Ibiden Co., Ltd. Interposer
JP5003260B2 (ja) 2007-04-13 2012-08-15 日本電気株式会社 半導体装置およびその製造方法
US7994622B2 (en) 2007-04-16 2011-08-09 Tessera, Inc. Microelectronic packages having cavities for receiving microelectric elements
KR20080094251A (ko) 2007-04-19 2008-10-23 삼성전자주식회사 웨이퍼 레벨 패키지 및 그 제조방법
JP5601751B2 (ja) 2007-04-26 2014-10-08 スパンション エルエルシー 半導体装置
US20080280393A1 (en) 2007-05-09 2008-11-13 Taiwan Semiconductor Manufacturing Co., Ltd. Methods for forming package structures
US20080284045A1 (en) 2007-05-18 2008-11-20 Texas Instruments Incorporated Method for Fabricating Array-Molded Package-On-Package
TWI371809B (en) 2007-06-04 2012-09-01 Advanced Semiconductor Eng Wafer structure and method for fabricating the same
US7872335B2 (en) 2007-06-08 2011-01-18 Broadcom Corporation Lead frame-BGA package with enhanced thermal performance and I/O counts
JP2008306128A (ja) 2007-06-11 2008-12-18 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
KR100865125B1 (ko) 2007-06-12 2008-10-24 삼성전기주식회사 반도체 패키지 및 그 제조방법
US7576415B2 (en) 2007-06-15 2009-08-18 Advanced Semiconductor Engineering, Inc. EMI shielded semiconductor package
US20080308305A1 (en) 2007-06-15 2008-12-18 Ngk Spark Plug Co., Ltd. Wiring substrate with reinforcing member
US7944034B2 (en) 2007-06-22 2011-05-17 Texas Instruments Incorporated Array molded package-on-package having redistribution lines
JP5179787B2 (ja) 2007-06-22 2013-04-10 ラピスセミコンダクタ株式会社 半導体装置及びその製造方法
US7911805B2 (en) 2007-06-29 2011-03-22 Tessera, Inc. Multilayer wiring element having pin interface
SG148901A1 (en) 2007-07-09 2009-01-29 Micron Technology Inc Packaged semiconductor assemblies and methods for manufacturing such assemblies
KR20090007120A (ko) 2007-07-13 2009-01-16 삼성전자주식회사 봉지부를 통하여 재배선을 달성하는 웨이퍼 레벨 적층형패키지 및 그 제조방법
US7781877B2 (en) 2007-08-07 2010-08-24 Micron Technology, Inc. Packaged integrated circuit devices with through-body conductive vias, and methods of making same
JP2009044110A (ja) 2007-08-13 2009-02-26 Elpida Memory Inc 半導体装置及びその製造方法
SG150396A1 (en) 2007-08-16 2009-03-30 Micron Technology Inc Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods
KR101329355B1 (ko) 2007-08-31 2013-11-20 삼성전자주식회사 적층형 반도체 패키지, 그 형성방법 및 이를 구비하는전자장치
KR101365621B1 (ko) 2007-09-04 2014-02-24 서울반도체 주식회사 열 방출 슬러그들을 갖는 발광 다이오드 패키지
JP2009064966A (ja) * 2007-09-06 2009-03-26 Shinko Electric Ind Co Ltd 多層配線基板及びその製造方法ならびに半導体装置
US7808439B2 (en) 2007-09-07 2010-10-05 University Of Tennessee Reserch Foundation Substrate integrated waveguide antenna array
US9330945B2 (en) * 2007-09-18 2016-05-03 Stats Chippac Ltd. Integrated circuit package system with multi-chip module
US8039960B2 (en) 2007-09-21 2011-10-18 Stats Chippac, Ltd. Solder bump with inner core pillar in semiconductor package
KR100902128B1 (ko) 2007-09-28 2009-06-09 삼성전기주식회사 방열 인쇄회로기판 및 반도체 칩 패키지
US8558379B2 (en) 2007-09-28 2013-10-15 Tessera, Inc. Flip chip interconnection with double post
JP2009088254A (ja) * 2007-09-28 2009-04-23 Toshiba Corp 電子部品パッケージ及び電子部品パッケージの製造方法
KR20090033605A (ko) 2007-10-01 2009-04-06 삼성전자주식회사 적층형 반도체 패키지, 그 형성방법 및 이를 구비하는전자장치
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
US20090091009A1 (en) 2007-10-03 2009-04-09 Corisis David J Stackable integrated circuit package
US8008183B2 (en) 2007-10-04 2011-08-30 Texas Instruments Incorporated Dual capillary IC wirebonding
US7834464B2 (en) 2007-10-09 2010-11-16 Infineon Technologies Ag Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device
TWI389220B (zh) 2007-10-22 2013-03-11 矽品精密工業股份有限公司 半導體封裝件及其製法
TWI360207B (en) 2007-10-22 2012-03-11 Advanced Semiconductor Eng Chip package structure and method of manufacturing
FR2923081B1 (fr) 2007-10-26 2009-12-11 3D Plus Procede d'interconnexion verticale de modules electroniques 3d par des vias.
GB0721957D0 (en) 2007-11-08 2007-12-19 Photonstar Led Ltd Ultra high thermal performance packaging for optoelectronics devices
JP2009123863A (ja) 2007-11-14 2009-06-04 Tessera Interconnect Materials Inc バンプ構造形成方法及びバンプ構造
WO2009067556A2 (en) 2007-11-19 2009-05-28 Nexxus Lighting, Inc. Apparatus and methods for thermal management of light emitting diodes
US20090127686A1 (en) 2007-11-21 2009-05-21 Advanced Chip Engineering Technology Inc. Stacking die package structure for semiconductor devices and method of the same
KR100886100B1 (ko) 2007-11-29 2009-02-27 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
JP2009135398A (ja) 2007-11-29 2009-06-18 Ibiden Co Ltd 組合せ基板
US7902644B2 (en) 2007-12-07 2011-03-08 Stats Chippac Ltd. Integrated circuit package system for electromagnetic isolation
US7964956B1 (en) 2007-12-10 2011-06-21 Oracle America, Inc. Circuit packaging and connectivity
US7696631B2 (en) 2007-12-10 2010-04-13 International Business Machines Corporation Wire bonding personalization and discrete component attachment on wirebond pads
US8390117B2 (en) 2007-12-11 2013-03-05 Panasonic Corporation Semiconductor device and method of manufacturing the same
US7706144B2 (en) 2007-12-17 2010-04-27 Lynch Thomas W Heat dissipation system and related method
JP2009158593A (ja) 2007-12-25 2009-07-16 Tessera Interconnect Materials Inc バンプ構造およびその製造方法
US20090170241A1 (en) 2007-12-26 2009-07-02 Stats Chippac, Ltd. Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
US20090166873A1 (en) 2007-12-27 2009-07-02 Advanced Chip Engineering Technology Inc. Inter-connecting structure for semiconductor device package and method of the same
JP4989614B2 (ja) 2007-12-28 2012-08-01 サムソン エルイーディー カンパニーリミテッド． 高出力ｌｅｄパッケージの製造方法
WO2009096950A1 (en) 2008-01-30 2009-08-06 Kulicke And Soffa Industries, Inc. Wire loop and method of forming the wire loop
US20090194829A1 (en) 2008-01-31 2009-08-06 Shine Chung MEMS Packaging Including Integrated Circuit Dies
US8120186B2 (en) 2008-02-15 2012-02-21 Qimonda Ag Integrated circuit and method
US8258015B2 (en) 2008-02-22 2012-09-04 Stats Chippac Ltd. Integrated circuit package system with penetrable film adhesive
US7956456B2 (en) 2008-02-27 2011-06-07 Texas Instruments Incorporated Thermal interface material design for enhanced thermal performance and improved package structural integrity
US8018065B2 (en) 2008-02-28 2011-09-13 Atmel Corporation Wafer-level integrated circuit package with top and bottom side electrical connections
KR101501739B1 (ko) 2008-03-21 2015-03-11 삼성전자주식회사 반도체 패키지 제조 방법
US7919871B2 (en) 2008-03-21 2011-04-05 Stats Chippac Ltd. Integrated circuit package system for stackable devices
US8525214B2 (en) 2008-03-25 2013-09-03 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader with thermal via
US8072079B2 (en) 2008-03-27 2011-12-06 Stats Chippac, Ltd. Through hole vias at saw streets including protrusions or recesses for interconnection
JP5195903B2 (ja) 2008-03-31 2013-05-15 株式会社村田製作所 電子部品モジュール及び該電子部品モジュールの製造方法
JP5043743B2 (ja) 2008-04-18 2012-10-10 ラピスセミコンダクタ株式会社 半導体装置の製造方法
US7741156B2 (en) 2008-05-27 2010-06-22 Stats Chippac, Ltd. Semiconductor device and method of forming through vias with reflowed conductive material
KR20090123680A (ko) 2008-05-28 2009-12-02 주식회사 하이닉스반도체 적층 반도체 패키지
US8093704B2 (en) 2008-06-03 2012-01-10 Intel Corporation Package on package using a bump-less build up layer (BBUL) package
US8021907B2 (en) 2008-06-09 2011-09-20 Stats Chippac, Ltd. Method and apparatus for thermally enhanced semiconductor package
JP5639052B2 (ja) 2008-06-16 2014-12-10 テッセラ，インコーポレイテッド ウェハレベルでの縁部の積重ね
US7932170B1 (en) 2008-06-23 2011-04-26 Amkor Technology, Inc. Flip chip bump structure and fabrication method
JP5511155B2 (ja) * 2008-06-25 2014-06-04 パナソニック株式会社 インターポーザ基板とその製造方法
DE102008048420A1 (de) 2008-06-27 2010-01-28 Qimonda Ag Chip-Anordnung und Verfahren zum Herstellen einer Chip-Anordnung
US7969009B2 (en) 2008-06-30 2011-06-28 Qualcomm Incorporated Through silicon via bridge interconnect
TWI473553B (zh) 2008-07-03 2015-02-11 Advanced Semiconductor Eng 晶片封裝結構
US7859033B2 (en) 2008-07-09 2010-12-28 Eastman Kodak Company Wafer level processing for backside illuminated sensors
JP5339800B2 (ja) 2008-07-10 2013-11-13 三菱電機株式会社 半導体装置の製造方法
TWI372453B (en) 2008-09-01 2012-09-11 Advanced Semiconductor Eng Copper bonding wire, wire bonding structure and method for processing and bonding a wire
SG10201505279RA (en) 2008-07-18 2015-10-29 Utac Headquarters Pte Ltd Packaging structural member
JP5276169B2 (ja) 2008-07-31 2013-08-28 スカイワークス ソリューションズ，インコーポレイテッド 一体化された干渉シールドを備えた半導体パッケージおよびその製造方法
US8923004B2 (en) 2008-07-31 2014-12-30 Micron Technology, Inc. Microelectronic packages with small footprints and associated methods of manufacturing
US8004093B2 (en) 2008-08-01 2011-08-23 Stats Chippac Ltd. Integrated circuit package stacking system
US7800810B2 (en) 2008-08-06 2010-09-21 Spatial Photonics, Inc. Packaging and testing of multiple MEMS devices on a wafer
TW201007924A (en) 2008-08-07 2010-02-16 Advanced Semiconductor Eng Chip package structure
US20100044860A1 (en) 2008-08-21 2010-02-25 Tessera Interconnect Materials, Inc. Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer
KR100997793B1 (ko) 2008-09-01 2010-12-02 주식회사 하이닉스반도체 반도체 패키지 및 이의 제조 방법
KR20100033012A (ko) 2008-09-19 2010-03-29 주식회사 하이닉스반도체 반도체 패키지 및 이를 갖는 적층 반도체 패키지
US7842541B1 (en) 2008-09-24 2010-11-30 Amkor Technology, Inc. Ultra thin package and fabrication method
US8237257B2 (en) 2008-09-25 2012-08-07 King Dragon International Inc. Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same
US8063475B2 (en) 2008-09-26 2011-11-22 Stats Chippac Ltd. Semiconductor package system with through silicon via interposer
US8569892B2 (en) 2008-10-10 2013-10-29 Nec Corporation Semiconductor device and manufacturing method thereof
JP5185062B2 (ja) 2008-10-21 2013-04-17 パナソニック株式会社 積層型半導体装置及び電子機器
MY149251A (en) 2008-10-23 2013-07-31 Carsem M Sdn Bhd Wafer-level package using stud bump coated with solder
KR101461630B1 (ko) 2008-11-06 2014-11-20 삼성전자주식회사 실장 높이는 축소되나, 솔더 접합 신뢰도는 개선되는 웨이퍼 레벨 칩 온 칩 패키지와, 패키지 온 패키지 및 그 제조방법
TW201023308A (en) 2008-12-01 2010-06-16 Advanced Semiconductor Eng Package-on-package device, semiconductor package and method for manufacturing the same
KR101011863B1 (ko) 2008-12-02 2011-01-31 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
KR101015651B1 (ko) * 2008-12-05 2011-02-22 삼성전기주식회사 칩 내장 인쇄회로기판 및 그 제조방법
JP2010135671A (ja) 2008-12-08 2010-06-17 Panasonic Corp 半導体装置及びその製造方法
US7642128B1 (en) 2008-12-12 2010-01-05 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US7898083B2 (en) 2008-12-17 2011-03-01 Texas Instruments Incorporated Method for low stress flip-chip assembly of fine-pitch semiconductor devices
TWI499024B (zh) 2009-01-07 2015-09-01 Advanced Semiconductor Eng 堆疊式多封裝構造裝置、半導體封裝構造及其製造方法
US8012797B2 (en) 2009-01-07 2011-09-06 Advanced Semiconductor Engineering, Inc. Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries
JP2010199528A (ja) 2009-01-27 2010-09-09 Tatsuta System Electronics Kk ボンディングワイヤ
JP2010177597A (ja) 2009-01-30 2010-08-12 Sanyo Electric Co Ltd 半導体モジュールおよび携帯機器
US20100200981A1 (en) 2009-02-09 2010-08-12 Advanced Semiconductor Engineering, Inc. Semiconductor package and method of manufacturing the same
US9142586B2 (en) 2009-02-24 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for backside illuminated image sensor
JP2010206007A (ja) 2009-03-04 2010-09-16 Nec Corp 半導体装置及びその製造方法
JP5471605B2 (ja) 2009-03-04 2014-04-16 日本電気株式会社 半導体装置及びその製造方法
US8115283B1 (en) 2009-07-14 2012-02-14 Amkor Technology, Inc. Reversible top/bottom MEMS package
US8106498B2 (en) 2009-03-05 2012-01-31 Stats Chippac Ltd. Integrated circuit packaging system with a dual board-on-chip structure and method of manufacture thereof
DE102009001461A1 (de) 2009-03-11 2010-09-16 Robert Bosch Gmbh Verfahren zur Herstellung einer elektronischen Baugruppe
US8258010B2 (en) 2009-03-17 2012-09-04 Stats Chippac, Ltd. Making a semiconductor device having conductive through organic vias
US20100244276A1 (en) 2009-03-25 2010-09-30 Lsi Corporation Three-dimensional electronics package
US20110068478A1 (en) 2009-03-26 2011-03-24 Reza Argenty Pagaila Integrated circuit packaging system with package stacking and method of manufacture thereof
US8194411B2 (en) 2009-03-31 2012-06-05 Hong Kong Applied Science and Technology Research Institute Co. Ltd Electronic package with stacked modules with channels passing through metal layers of the modules
US8053814B2 (en) 2009-04-08 2011-11-08 International Business Machines Corporation On-chip embedded thermal antenna for chip cooling
US8039316B2 (en) 2009-04-14 2011-10-18 Stats Chippac Ltd. Integrated circuit packaging system with stacked integrated circuit and heat spreader with openings and method of manufacture thereof
JP2010251483A (ja) 2009-04-14 2010-11-04 Renesas Electronics Corp 半導体装置およびその製造方法
US20100289142A1 (en) 2009-05-15 2010-11-18 Il Kwon Shim Integrated circuit packaging system with coin bonded interconnects and method of manufacture thereof
US8020290B2 (en) 2009-06-14 2011-09-20 Jayna Sheats Processes for IC fabrication
TWI379367B (en) 2009-06-15 2012-12-11 Kun Yuan Technology Co Ltd Chip packaging method and structure thereof
US20120153444A1 (en) 2009-06-18 2012-06-21 Rohm Co., Ltd Semiconductor device
US20100327419A1 (en) 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
JP5214554B2 (ja) 2009-07-30 2013-06-19 ラピスセミコンダクタ株式会社 半導体チップ内蔵パッケージ及びその製造方法、並びに、パッケージ・オン・パッケージ型半導体装置及びその製造方法
US8183678B2 (en) 2009-08-04 2012-05-22 Amkor Technology Korea, Inc. Semiconductor device having an interposer
US20110209908A1 (en) 2009-08-06 2011-09-01 Advanced Chip Engineering Technology Inc. Conductor package structure and method of the same
KR101124102B1 (ko) 2009-08-24 2012-03-21 삼성전기주식회사 발광 소자 패키지용 기판 및 이를 포함하는 발광 소자 패키지
EP2290686A3 (en) 2009-08-28 2011-04-20 STMicroelectronics S.r.l. Method to perform electrical testing and assembly of electronic devices
US7923304B2 (en) 2009-09-10 2011-04-12 Stats Chippac Ltd. Integrated circuit packaging system with conductive pillars and method of manufacture thereof
US8264091B2 (en) 2009-09-21 2012-09-11 Stats Chippac Ltd. Integrated circuit packaging system with encapsulated via and method of manufacture thereof
US8008121B2 (en) 2009-11-04 2011-08-30 Stats Chippac, Ltd. Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate
US8390108B2 (en) 2009-12-16 2013-03-05 Stats Chippac Ltd. Integrated circuit packaging system with stacking interconnect and method of manufacture thereof
US8169065B2 (en) 2009-12-22 2012-05-01 Epic Technologies, Inc. Stackable circuit structures and methods of fabrication thereof
TW201123387A (en) 2009-12-25 2011-07-01 xiang-hua Wang Thermal-electric separated metal PCB with a chip carrier.
TWI392066B (zh) 2009-12-28 2013-04-01 矽品精密工業股份有限公司 封裝結構及其製法
TWI395312B (zh) * 2010-01-20 2013-05-01 矽品精密工業股份有限公司 具微機電元件之封裝結構及其製法
JP5550369B2 (ja) 2010-02-03 2014-07-16 新日鉄住金マテリアルズ株式会社 半導体用銅ボンディングワイヤとその接合構造
CN102153045B (zh) * 2010-02-12 2015-03-11 矽品精密工业股份有限公司 具微机电元件的封装结构及其制法
JP2011166051A (ja) 2010-02-15 2011-08-25 Panasonic Corp 半導体装置及び半導体装置の製造方法
US7990711B1 (en) 2010-02-24 2011-08-02 International Business Machines Corporation Double-face heat removal of vertically integrated chip-stacks utilizing combined symmetric silicon carrier fluid cavity and micro-channel cold plate
US9496152B2 (en) 2010-03-12 2016-11-15 STATS ChipPAC Pte. Ltd. Carrier system with multi-tier conductive posts and method of manufacture thereof
US7928552B1 (en) 2010-03-12 2011-04-19 Stats Chippac Ltd. Integrated circuit packaging system with multi-tier conductive interconnects and method of manufacture thereof
KR101667656B1 (ko) 2010-03-24 2016-10-20 삼성전자주식회사 패키지-온-패키지 형성방법
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US8564141B2 (en) 2010-05-06 2013-10-22 SK Hynix Inc. Chip unit and stack package having the same
US8558392B2 (en) 2010-05-14 2013-10-15 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulant
US8288854B2 (en) 2010-05-19 2012-10-16 Advanced Semiconductor Engineering, Inc. Semiconductor package and method for making the same
US8217502B2 (en) 2010-06-08 2012-07-10 Stats Chippac Ltd. Integrated circuit packaging system with multipart conductive pillars and method of manufacture thereof
US20120001336A1 (en) 2010-07-02 2012-01-05 Texas Instruments Incorporated Corrosion-resistant copper-to-aluminum bonds
US8330272B2 (en) 2010-07-08 2012-12-11 Tessera, Inc. Microelectronic packages with dual or multiple-etched flip-chip connectors
KR20120007839A (ko) 2010-07-15 2012-01-25 삼성전자주식회사 적층형 반도체 패키지의 제조방법
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
JP5713598B2 (ja) 2010-07-20 2015-05-07 新光電気工業株式会社 ソケット及びその製造方法
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8847376B2 (en) 2010-07-23 2014-09-30 Tessera, Inc. Microelectronic elements with post-assembly planarization
KR101683814B1 (ko) 2010-07-26 2016-12-08 삼성전자주식회사 관통 전극을 구비하는 반도체 장치
US8580607B2 (en) 2010-07-27 2013-11-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
US8304900B2 (en) 2010-08-11 2012-11-06 Stats Chippac Ltd. Integrated circuit packaging system with stacked lead and method of manufacture thereof
US8076184B1 (en) 2010-08-16 2011-12-13 Stats Chippac, Ltd. Semiconductor device and method of forming wafer-level multi-row etched leadframe with base leads and embedded semiconductor die
US8518746B2 (en) 2010-09-02 2013-08-27 Stats Chippac, Ltd. Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die
US8354297B2 (en) 2010-09-03 2013-01-15 Stats Chippac, Ltd. Semiconductor device and method of forming different height conductive pillars to electrically interconnect stacked laterally offset semiconductor die
US8080445B1 (en) 2010-09-07 2011-12-20 Stats Chippac, Ltd. Semiconductor device and method of forming WLP with semiconductor die embedded within penetrable encapsulant between TSV interposers
US20120063090A1 (en) 2010-09-09 2012-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Cooling mechanism for stacked die package and method of manufacturing the same
US8409922B2 (en) 2010-09-14 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect
US9431275B2 (en) * 2010-09-17 2016-08-30 Pfg Ip Llc Wire bond through-via structure and method
US8415704B2 (en) 2010-09-22 2013-04-09 Ut-Battelle, Llc Close-packed array of light emitting devices
US8349735B2 (en) 2010-09-22 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming conductive TSV with insulating annular ring
US9224647B2 (en) 2010-09-24 2015-12-29 Stats Chippac, Ltd. Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer
JP5616739B2 (ja) 2010-10-01 2014-10-29 新日鉄住金マテリアルズ株式会社 複層銅ボンディングワイヤの接合構造
US20120080787A1 (en) 2010-10-05 2012-04-05 Qualcomm Incorporated Electronic Package and Method of Making an Electronic Package
JP2012104790A (ja) 2010-10-12 2012-05-31 Elpida Memory Inc 半導体装置
CN102024782B (zh) 2010-10-12 2012-07-25 北京大学 三维垂直互联结构及其制作方法
US8618646B2 (en) 2010-10-12 2013-12-31 Headway Technologies, Inc. Layered chip package and method of manufacturing same
JP5591653B2 (ja) 2010-10-27 2014-09-17 東和精工株式会社 ラベル剥離機
US8263435B2 (en) 2010-10-28 2012-09-11 Stats Chippac, Ltd. Semiconductor device and method of stacking semiconductor die in mold laser package interconnected by bumps and conductive vias
US8697492B2 (en) 2010-11-02 2014-04-15 Tessera, Inc. No flow underfill
US8525318B1 (en) 2010-11-10 2013-09-03 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
KR101075241B1 (ko) 2010-11-15 2011-11-01 테세라, 인코포레이티드 유전체 부재에 단자를 구비하는 마이크로전자 패키지
WO2012067177A1 (ja) 2010-11-17 2012-05-24 株式会社フジクラ 配線板及びその製造方法
KR20120056052A (ko) 2010-11-24 2012-06-01 삼성전자주식회사 반도체 패키지
US8502387B2 (en) 2010-12-09 2013-08-06 Stats Chippac Ltd. Integrated circuit packaging system with vertical interconnection and method of manufacture thereof
US8853558B2 (en) 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
US8772817B2 (en) 2010-12-22 2014-07-08 Cree, Inc. Electronic device submounts including substrates with thermally conductive vias
US8736065B2 (en) 2010-12-22 2014-05-27 Intel Corporation Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the same
KR101215271B1 (ko) 2010-12-29 2012-12-26 앰코 테크놀로지 코리아 주식회사 반도체 패키지 구조물 및 반도체 패키지 구조물의 제조 방법
US20120184116A1 (en) 2011-01-18 2012-07-19 Tyco Electronics Corporation Interposer
US8766436B2 (en) 2011-03-01 2014-07-01 Lsi Corporation Moisture barrier for a wire bond
US8508045B2 (en) 2011-03-03 2013-08-13 Broadcom Corporation Package 3D interconnection and method of making same
US8841765B2 (en) 2011-04-22 2014-09-23 Tessera, Inc. Multi-chip module with stacked face-down connected dies
US9508622B2 (en) 2011-04-28 2016-11-29 Freescale Semiconductor, Inc. Method for protecting copper wire bonds on aluminum pads of a semiconductor device from corrosion
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US8476115B2 (en) 2011-05-03 2013-07-02 Stats Chippac, Ltd. Semiconductor device and method of mounting cover to semiconductor die and interposer with adhesive material
US8633059B2 (en) 2011-05-11 2014-01-21 Stats Chippac Ltd. Integrated circuit packaging system with interconnect and method of manufacture thereof
US8669646B2 (en) 2011-05-31 2014-03-11 Broadcom Corporation Apparatus and method for grounding an IC package lid for EMI reduction
US9128123B2 (en) 2011-06-03 2015-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Interposer test structures and methods
US9117811B2 (en) 2011-06-13 2015-08-25 Tessera, Inc. Flip chip assembly and process with sintering material on metal bumps
US9006031B2 (en) 2011-06-23 2015-04-14 Stats Chippac, Ltd. Semiconductor device and method of forming EWLB package with standoff conductive layer over encapsulant bumps
KR20130007049A (ko) 2011-06-28 2013-01-18 삼성전자주식회사 쓰루 실리콘 비아를 이용한 패키지 온 패키지
US9449941B2 (en) 2011-07-07 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Connecting function chips to a package to form package-on-package
US8476770B2 (en) 2011-07-07 2013-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and methods for forming through vias
US8816505B2 (en) 2011-07-29 2014-08-26 Tessera, Inc. Low stress vias
US8487421B2 (en) 2011-08-01 2013-07-16 Tessera, Inc. Microelectronic package with stacked microelectronic elements and method for manufacture thereof
US8937309B2 (en) 2011-08-08 2015-01-20 Micron Technology, Inc. Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication
US20130037929A1 (en) 2011-08-09 2013-02-14 Kay S. Essig Stackable wafer level packages and related methods
US20130040423A1 (en) 2011-08-10 2013-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of Multi-Chip Wafer Level Packaging
US8988895B2 (en) 2011-08-23 2015-03-24 Tessera, Inc. Interconnection elements with encased interconnects
KR101800440B1 (ko) 2011-08-31 2017-11-23 삼성전자주식회사 다수의 반도체 칩들을 가진 반도체 패키지 및 그 형성 방법
US20130049218A1 (en) 2011-08-31 2013-02-28 Zhiwei Gong Semiconductor device packaging having pre-encapsulation through via formation
US8816404B2 (en) 2011-09-16 2014-08-26 Stats Chippac, Ltd. Semiconductor device and method of forming stacked semiconductor die and conductive interconnect structure through an encapsulant
US9177832B2 (en) 2011-09-16 2015-11-03 Stats Chippac, Ltd. Semiconductor device and method of forming a reconfigured stackable wafer level package with vertical interconnect
KR101900423B1 (ko) 2011-09-19 2018-09-21 삼성전자주식회사 반도체 메모리 장치
TWI501254B (zh) 2011-10-03 2015-09-21 Invensas Corp 用於具有正交窗之多晶粒導線結合總成之短線最小化
KR101906408B1 (ko) 2011-10-04 2018-10-11 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US20130087915A1 (en) 2011-10-10 2013-04-11 Conexant Systems, Inc. Copper Stud Bump Wafer Level Package
US8836136B2 (en) 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias
US9105552B2 (en) 2011-10-31 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
KR101297015B1 (ko) 2011-11-03 2013-08-14 주식회사 네패스 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법, 이에 의한 반도체 패키지 및 패키지 온 패키지
US9196588B2 (en) 2011-11-04 2015-11-24 Invensas Corporation EMI shield
US8916781B2 (en) 2011-11-15 2014-12-23 Invensas Corporation Cavities containing multi-wiring structures and devices
US8552556B1 (en) 2011-11-22 2013-10-08 Amkor Technology, Inc. Wafer level fan out package
US8912651B2 (en) 2011-11-30 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) structure including stud bulbs and method
TWI464031B (zh) 2011-12-14 2014-12-11 Univ Yuan Ze 抑制柯肯達爾孔洞形成於銲料與銅銲墊之間的方法
KR101924388B1 (ko) 2011-12-30 2018-12-04 삼성전자주식회사 재배선 구조를 갖는 반도체 패키지
US8680684B2 (en) 2012-01-09 2014-03-25 Invensas Corporation Stackable microelectronic package structures
US9258922B2 (en) 2012-01-18 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. PoP structures including through-assembly via modules
US8686570B2 (en) 2012-01-20 2014-04-01 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-dimensional integrated circuit structures and methods of forming the same
KR20130090143A (ko) 2012-02-03 2013-08-13 삼성전자주식회사 패키지-온-패키지 타입의 반도체 패키지 및 그 제조방법
US8742576B2 (en) 2012-02-15 2014-06-03 Oracle International Corporation Maintaining alignment in a multi-chip module using a compressible structure
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
DE102012203293B4 (de) 2012-03-02 2021-12-02 Robert Bosch Gmbh Halbleitermodul mit integriertem Wellenleiter für Radarsignale
US20130234317A1 (en) 2012-03-09 2013-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging Methods and Packaged Semiconductor Devices
US9082763B2 (en) 2012-03-15 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Joint structure for substrates and methods of forming
US9842798B2 (en) 2012-03-23 2017-12-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a PoP device with embedded vertical interconnect units
KR20130111780A (ko) 2012-04-02 2013-10-11 삼성전자주식회사 Ｅｍｉ 차폐부를 갖는 반도체 장치
US9405064B2 (en) 2012-04-04 2016-08-02 Texas Instruments Incorporated Microstrip line of different widths, ground planes of different distances
US8922005B2 (en) 2012-04-11 2014-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for package on package devices with reversed stud bump through via interconnections
US8978247B2 (en) 2012-05-22 2015-03-17 Invensas Corporation TSV fabrication using a removable handling structure
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9171790B2 (en) 2012-05-30 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
US20130323409A1 (en) 2012-05-31 2013-12-05 Skyworks Solutions, Inc. Systems and methods for controlling electromagnetic interference for integrated circuit modules
US8948712B2 (en) 2012-05-31 2015-02-03 Skyworks Solutions, Inc. Via density and placement in radio frequency shielding applications
US8981559B2 (en) 2012-06-25 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
US8742597B2 (en) 2012-06-29 2014-06-03 Intel Corporation Package substrates with multiple dice
US8653626B2 (en) 2012-07-18 2014-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures including a capacitor and methods of forming the same
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US10115671B2 (en) 2012-08-03 2018-10-30 Snaptrack, Inc. Incorporation of passives and fine pitch through via for package on package
US8642393B1 (en) 2012-08-08 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of forming same
US8828860B2 (en) 2012-08-30 2014-09-09 International Business Machines Corporation Double solder bumps on substrates for low temperature flip chip bonding
US9443797B2 (en) 2012-09-14 2016-09-13 STATS ChipPAC Pte. Ltd. Semiconductor device having wire studs as vertical interconnect in FO-WLP
US8963339B2 (en) 2012-10-08 2015-02-24 Qualcomm Incorporated Stacked multi-chip integrated circuit package
US8975726B2 (en) 2012-10-11 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. POP structures and methods of forming the same
KR101419597B1 (ko) 2012-11-06 2014-07-14 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9418971B2 (en) 2012-11-08 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure including a thermal isolation material and method of forming the same
US9412661B2 (en) 2012-11-21 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming package-on-package structure
US9401338B2 (en) 2012-11-29 2016-07-26 Freescale Semiconductor, Inc. Electronic devices with embedded die interconnect structures, and methods of manufacture thereof
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US20140175657A1 (en) 2012-12-21 2014-06-26 Mihir A. Oka Methods to improve laser mark contrast on die backside film in embedded die packages
US8729714B1 (en) 2012-12-31 2014-05-20 Intel Mobile Communications GmbH Flip-chip wafer level package and methods thereof
US9378982B2 (en) 2013-01-31 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US8940630B2 (en) 2013-02-01 2015-01-27 Invensas Corporation Method of making wire bond vias and microelectronic package having wire bond vias
US8907500B2 (en) 2013-02-04 2014-12-09 Invensas Corporation Multi-die wirebond packages with elongated windows
US20140225248A1 (en) 2013-02-13 2014-08-14 Qualcomm Incorporated Power distribution and thermal solution for direct stacked integrated circuits
US9209081B2 (en) 2013-02-21 2015-12-08 Freescale Semiconductor, Inc. Semiconductor grid array package
US20140239490A1 (en) 2013-02-26 2014-08-28 Unimicron Technology Corporation Packaging substrate and fabrication method thereof
US20140239479A1 (en) 2013-02-26 2014-08-28 Paul R Start Microelectronic package including an encapsulated heat spreader
US9461025B2 (en) 2013-03-12 2016-10-04 Taiwan Semiconductor Manfacturing Company, Ltd. Electric magnetic shielding structure in packages
US9299670B2 (en) 2013-03-14 2016-03-29 Freescale Semiconductor, Inc. Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
US9788466B2 (en) 2013-04-16 2017-10-10 Skyworks Solutions, Inc. Apparatus and methods related to ground paths implemented with surface mount devices
KR20140126598A (ko) 2013-04-23 2014-10-31 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US9663353B2 (en) 2013-06-28 2017-05-30 Intel IP Corporation Microelectromechanical system (MEMS) on application specific integrated circuit (ASIC)
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
KR102161173B1 (ko) 2013-08-29 2020-09-29 삼성전자주식회사 패키지 온 패키지 장치 및 이의 제조 방법
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9012263B1 (en) 2013-10-31 2015-04-21 Freescale Semiconductor, Inc. Method for treating a bond pad of a package substrate
US9379078B2 (en) 2013-11-07 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. 3D die stacking structure with fine pitches
KR101631934B1 (ko) 2013-11-13 2016-06-21 앰코 테크놀로지 코리아 주식회사 반도체 패키지 구조물 및 그 제작 방법
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9653442B2 (en) 2014-01-17 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and methods of forming same
KR20150091932A (ko) 2014-02-04 2015-08-12 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
US9224709B2 (en) 2014-02-13 2015-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device including an embedded surface mount device and method of forming the same
US9362161B2 (en) 2014-03-20 2016-06-07 Stats Chippac, Ltd. Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package
US9318452B2 (en) 2014-03-21 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US9437459B2 (en) 2014-05-01 2016-09-06 Freescale Semiconductor, Inc. Aluminum clad copper structure of an electronic component package and a method of making an electronic component package with an aluminum clad copper structure
US20150340305A1 (en) 2014-05-20 2015-11-26 Freescale Semiconductor, Inc. Stacked die package with redistribution layer
US10325876B2 (en) 2014-06-25 2019-06-18 Nxp Usa, Inc. Surface finish for wirebonding
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
KR101640341B1 (ko) 2015-02-04 2016-07-15 앰코 테크놀로지 코리아 주식회사 반도체 패키지
US9653428B1 (en) 2015-04-14 2017-05-16 Amkor Technology, Inc. Semiconductor package and fabricating method thereof
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out

Also Published As

Publication number Publication date
US10170412B2 (en) 2019-01-01
US20160163639A1 (en) 2016-06-09
US10510659B2 (en) 2019-12-17
WO2013177134A1 (en) 2013-11-28
US20190096803A1 (en) 2019-03-28
KR20150012285A (ko) 2015-02-03
EP2852974A1 (en) 2015-04-01
TW201401398A (zh) 2014-01-01
US20180233448A1 (en) 2018-08-16
TW201613001A (en) 2016-04-01
US9263413B2 (en) 2016-02-16
JP2015517745A (ja) 2015-06-22
US20130313716A1 (en) 2013-11-28
US8835228B2 (en) 2014-09-16
EP2852974B1 (en) 2018-08-01
US9953914B2 (en) 2018-04-24
US20150069639A1 (en) 2015-03-12
TWI560788B (en) 2016-12-01
CN104520987B (zh) 2017-08-11
CN104520987A (zh) 2015-04-15

Similar Documents

Publication Publication Date Title
TWI528477B (zh) 具有線接合互連之無基板可堆疊封裝、製造微電子單元的方法、製造微電子封裝的方法以及製造微電子組件的方法
US11990382B2 (en) Fine pitch BVA using reconstituted wafer with area array accessible for testing
TWI467732B (zh) 具有線接合至囊封表面的疊層封裝總成
US10297582B2 (en) BVA interposer
TWI588949B (zh) 具有整合式承載表面的微電子封裝
JP4505983B2 (ja) 半導体装置
JP5170134B2 (ja) 半導体装置及びその製造方法
US7750450B2 (en) Stacked die package with stud spacers
KR20120125148A (ko) 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees