JP5120266B6 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP5120266B6 JP5120266B6 JP2008555983A JP2008555983A JP5120266B6 JP 5120266 B6 JP5120266 B6 JP 5120266B6 JP 2008555983 A JP2008555983 A JP 2008555983A JP 2008555983 A JP2008555983 A JP 2008555983A JP 5120266 B6 JP5120266 B6 JP 5120266B6
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- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims description 316
- 238000004519 manufacturing process Methods 0.000 title claims description 55
- 239000011347 resin Substances 0.000 claims description 135
- 229920005989 resin Polymers 0.000 claims description 135
- 238000007789 sealing Methods 0.000 claims description 112
- 238000000034 method Methods 0.000 claims description 78
- 239000000758 substrate Substances 0.000 claims description 67
- 239000000853 adhesive Substances 0.000 claims description 46
- 230000001070 adhesive effect Effects 0.000 claims description 44
- 229910000679 solder Inorganic materials 0.000 claims description 18
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000000926 separation method Methods 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 description 31
- 239000002184 metal Substances 0.000 description 31
- 239000010949 copper Substances 0.000 description 14
- 239000000463 material Substances 0.000 description 14
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 8
- 229910052709 silver Inorganic materials 0.000 description 8
- 239000004332 silver Substances 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010931 gold Substances 0.000 description 7
- 239000004020 conductor Substances 0.000 description 6
- 238000005520 cutting process Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 230000017525 heat dissipation Effects 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000748 compression moulding Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000007650 screen-printing Methods 0.000 description 3
- 238000001721 transfer moulding Methods 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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Description
32 配線基板
33 半導体素子
36 樹脂
38、38A、38B 接地用電極
39 シールド部材
40 接着部材
41 配線回路基板
88 ダイシングソー
89 接着剤
91 砥石
1.半導体装置の第1の実施態様
本発明による半導体装置の第1の実施態様を図2に示す。また、当該半導体装置の断面を図3に示す。当該断面は、図2に示す線A−A'に於ける断面である。
本発明による半導体装置の第2の実施態様を図6に示す。また、当該半導体装置の断面を図7に示す。当該断面は、図6に示す線A−A'に於ける断面である。
3.半導体装置の第3の実施態様
本発明による半導体装置の第3の実施態様を図10に示す。また、当該半導体装置の断面を図11に示す。当該断面は、図10に示す線A−A'に於ける断面である。
尚、前記第1の実施態様に於ける半導体装置30、並びに第3の実施態様に於ける半導体装置70に於いては、半導体素子の回路構成及び/或いは機能によっては、接地電極用電極パッド37を、ボンディングワイヤ34が接続されるに電極パッド列と同一線上に並べて配置することもできる。(図示せず)
かかる電極パッド配置構成であれば、半導体素子の小形化を可能とし、もって半導体装置として小形化を図ることができる。
次いで、上述の本発明の実施態様にかかる半導体装置30、50及び70の製造方法について説明する。尚、以下の説明において参照する図面にあっては、配線基板32及び配線回路基板(マザーボード)41の詳細な構成を示すことを省略している。
前記本発明による半導体装置の第1の実施態様に於ける半導体装置の製造方法について、図14乃至図23を参照して説明する。
当該基板83上には、複数個の半導体素子が搭載・固着される。
このとき、当該基板83の上面の、前記ボンディングワイヤ34が接続されている電極パッドよりも外側の領域、即ち半導体素子33から遠い位置に於いて、接地配線パターン35に接続された電極パッド(図示せず)と、隣り合う他の半導体素子33の搭載領域に於いて接地配線パターン35に接続された電極パッド(図示せず)との間を接続して、ボンディングワイヤ84Aをループ状に配設する。(図15−(c)参照)
当該ループ状ボンディングワイヤ84Aが、前記ボンディングワイヤ34と同一径、同一材料である場合には、同一のワイヤボンディング工程に於いて接続することができる。
何れの場合も、前記ボンディングワイヤ34の径は例えば約18μmΦ乃至30μmΦであるのに対し、接地用電極38の径は、当該ボンディングワイヤ34の径と同一、或いはそれ以上の太さ、例えば約100μmΦ乃至500μmΦとされる。
次いで、当該基板83の一方の主面にあって封止用樹脂36Aにより樹脂封止された半導体素子33、及び当該半導体素子33に接続されたボンディングワイヤ34等を1つの単位として、前記ループ状ボンディングワイヤ84A(或いは、略コの字形を有する金属棒或いは金属板等の導電性部材85)の長さ方向の略中央部に於いて、前記基板83及び封止用樹脂36Aを、その厚さ方向に切断する。(図17−(f)参照)
切断・分離手段としては、ダイシングソー88を用いたブレードダイシング法を適用することができる。また、所謂レーザーダイシング法を適用することもできる。
当該半導体装置30にあっては、封止用樹脂36の側面に、ボンディングワイヤ84Aが切断された結果である接地用電極38の端部38−1が表出している。一方、配線基板32の他方の主面には、外部接続端子たる半田ボール31が配設されている。
次いで、前記封止用樹脂36を覆って、箱形(断面が略コの字型)の金属からなるシールド部材39を配設する。(図18−(i)参照)このとき、シールド部材39の内側底面に予め接着剤89を配設しておくことにより、当該接着剤89によりシールド部材39は封止用樹脂36に固着される。
ここで、加熱方法としては、一つに、シールド部材39の側面に於いて接地用電極38の端部38−1が位置する箇所に対して選択的に加熱を施す方法を採ることができる。また、接着剤40が半田からなる場合には、リフローにより加熱してもよく、接着部剤40が銀(Ag)ペースト等の導電性接着剤からなる場合には、高温槽を用いて加熱硬化させてもよい。
次いで、半導体装置の封止用樹脂36の上面に、略十字形を有する板状或いは箔状の金属製シールド部材39Aを配置する。(図20−(i)'参照)この時、封止用樹脂36の上面に接するシールド部材39Aには、予め接着剤89を選択的に配設しておくことにより、シールド部材39Aは当該接着剤89を介して、封止用樹脂36の上面に固着される。
このとき、当該シールド部材39の内側面であって、封止用樹脂36の側面において露出している接地用電極38の端面38−1に対応する箇所には、接続用突起部39Bが設けられている。また、対向する接続用突起部39B間の距離Lは、半導体装置30の外形寸法Pと略同一又は若干短く設定されている。更に、シールド部材39の内側底面には、接着部剤40が配設されている。
尚、本例では、接地用電極38の端部38−1と、シールド部材39の内側面に設けられた接続用突起部39Bとを機械的に接触させているが、これに加え、接地用電極38の端部38−1に、半田又は銀(Ag)ペースト等の導電性接着剤等の接着部材40を、ディスペンス法又はスクリーン印刷法等により配設しておき、当該接着部材40をもって接続を強化することもできる。
次いで、前記本発明による半導体装置の第2の実施態様に於ける半導体装置の製造方法について、図24乃至図27を参照して説明する。
当該基板83上には、複数個の半導体素子が搭載・固着される。
このとき、当該基板83の上面の、前記ボンディングワイヤ34が接続されている電極パッド以外よりも外側の領域、即ち半導体素子33から遠い位置に於いて、配線基板32の四辺それぞれに平行して、接地配線パターン35に接続された二つの電極パッド(図示せず)間を結んで、ボンディングワイヤ84Aをループ状に配設する。(図24−(b)−1参照)
即ち、当該ループ状ボンディングワイヤ84Aは、配線基板32の四辺に対応して、且つ隣り合う他の半導体素子33の搭載領域との境界上に位置し、当該境界に平行して延在するよう配設される。(図24−(b)−2参照)
当該ループ状ボンディングワイヤ84Aが、前記ボンディングワイヤ34と同一径、同一材料である場合には、同一のワイヤボンディング工程に於いて接続することができる。
次いで、当該基板83の一方の主面にあって封止用樹脂により樹脂封止された半導体素子33、及び当該半導体素子33に接続されたボンディングワイヤ34等を1つの単位として、前記基板83及び封止用樹脂36Aをその厚さ方向に切断する。(図26−(e)参照)
切断・分離手段としては、ダイシングソー88を用いたブレードダイシング法を適用することができる。また、所謂レーザーダイシング法を適用することもできる。
当該半導体装置50にあっては、封止用樹脂36の側面部に、前記ボンディングワイヤ84Aがその長さ方向に切断された結果である接地用電極38が、その幅(径)断面をループ状に露出して配置されている。一方、配線基板32の他方の主面には、外部接続端子たる半田ボール31が配設されている。
この様にして、封止用樹脂36を被覆してシールド部材39が配設された半導体装置50Sが形成される。
次いで、前記本発明による半導体装置の第3の実施態様に於ける半導体装置の製造方法について、図28乃至図32を参照して説明する。
当該基板83上には、複数個の半導体素子が搭載・固着される。
このとき、当該基板83の上面の、前記ボンディングワイヤ34が接続されている電極パッドよりも外側の領域、即ち半導体素子33から遠い位置に於いて、接地配線パターン35に接続された電極パッド(図示せず)に、ボンディングツール90を用いて、略垂直方向に伸びるボンディングワイヤ84Cを配設する。(図29−(c)参照)
当該垂直方向に伸びるボンディングワイヤ84Cが、前記ボンディングワイヤ34と同一径、同一材料である場合には、同じワイヤボンディング工程に於いて配設することができる。即ち、電極パッド37(例えば図3参照)に対し、周知のボンディングツールを適用してワイヤボンディングを行い、当該ボンディングツールを垂直方向に引き上げ、前記ボンディングワイヤ34のワイヤーループの最上部よりも高い位置に於いて、当該ワイヤを切断することにより形成する。
何れの場合も、接地用電極38の高さ(長さ)は、当該半導体装置に於ける封止用樹脂36の外表面に表出する高さに設定される。
このとき、基板83の主面上に搭載・固着された複数個の半導体素子33、当該半導体素子33に接続されたボンディングワイヤ34、並びに接地用電極部31等を一括して樹脂封止する。
当該研削処理は、砥石91を用いて行うことができる。
次いで、当該基板83の一方の主面にあって封止用樹脂により樹脂封止された半導体素子33、及び当該半導体素子33に接続されたボンディングワイヤ34等を1つの単位として、前記基板83及び封止用樹脂36Aをその厚さ方向に切断する。(図31−(g)参照)
切断・分離手段としては、ダイシングソー88を用いたブレードダイシング法を適用することができる。また、所謂レーザーダイシング法を適用することもできる。
当該半導体装置70にあっては、前記封止用樹脂36の上面に、接地用電極38がその端部38−1を表出している。一方、配線基板32の他方の主面には、外部接続端子たる半田ボール31が配設されている。(図31−(h)参照)
次いで、前記封止用樹脂36を覆って、箱形(断面が略コの字型)の金属からなるシールド部材39を配設する。
この様にして、封止用樹脂36を被覆してシールド部材39が配設された半導体装置70Sが形成される。
Claims (7)
- 基板と、
当該基板上に搭載された半導体素子と、
当該半導体素子を被覆する封止用樹脂と、
一端が前記基板の配線層に接続され、且つその一部が前記封止用樹脂の表面に露出された接地用電極と、
前記封止用樹脂の上及び側壁上を被覆し、且つ前記接地用電極に接続されたシールド部材と
を有し、
前記シールド部材の下端が、前記基板の上面より低いか同じ高さの位置にあり、
前記シールド部材は突起部を有し、
前記突起部と前記接地用電極の一部とが接続することを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記接地用電極は、前記基板の上面に設けられたボンディングワイヤであって、
前記接地用電極の側面が、前記封止用樹脂の前記側面において露出し、前記シールド部材と接触していることを特徴とする半導体装置。 - 請求項1または2記載の半導体装置であって、
前記シールド部材は、複数の前記半導体素子の前記封止用樹脂の上及び側壁上を被覆することを特徴とする半導体装置。 - 基板上に複数個の半導体素子を搭載する工程と、
隣り合う前記半導体素子の配線基板領域間を跨ぐように接地電極用部材を配設する工程と、
前記半導体素子並びに前記接地電極用部材を封止用樹脂により被覆する工程と、
前記基板、前記封止用樹脂並びに前記接地電極用部材を分離して前記封止用樹脂の表面に露出面を有する接地用電極を有する個片化された半導体装置を形成する工程と、
前記個片化された半導体装置の前記封止用樹脂の上及び側壁上にシールド部材を配設する工程と
を有し、
前記接地用電極の一部と接触する前記シールド部材の箇所には突起部が形成されており、
前記シールド部材を前記封止用樹脂の上及び側壁上に配設することにより、前記接地用電極の一部が前記シールド部材の前記突起部に接続することを特徴とする半導体装置の製造方法。 - 複数の半導体素子が配置された基板の、隣接する半導体素子との分離ライン上に、接地
電極用部材を設ける工程と、
前記接地電極用部材と前記半導体素子とを、樹脂を用いて封止する工程と、
前記基板、前記封止用樹脂並びに前記接地電極用部材を、前記分離ラインに沿って分離して前記封止用樹脂の表面に露出面を有する接地用電極を有する個片化された半導体装置を形成する工程と、
前記個片化された半導体装置の前記封止用樹脂の上及び側壁上にシールド部材を配設して、前記接地用電極と前記シールド部材とを接触させる工程と
を有し、
前記接地用電極の一部と接触する前記シールド部材の箇所には突起部が形成されており、
前記シールド部材を前記封止用樹脂の上及び側壁上に配設することにより、前記接地用電極の一部が前記シールド部材の前記突起部に接続することを特徴とする半導体装置の製造方法。 - 請求項5記載の半導体装置の製造方法であって、
前記接地用電極の一部に半田又は導電性接着剤を設け、
前記シールド部材を、前記導電接着剤を介して前記接地用電極の一部と接触させ、
前記シールド部材を加熱することにより、前記シールド部材と前記接地用電極の一部とを接続することを特徴とする半導体装置の製造方法。 - 請求項4乃至6のいずれか1項に記載の半導体装置の製造方法であって、
前記シールド部材の下端が、前記基板の上面より低いか同じ高さの位置にあることを特徴とする半導体装置の製造方法。
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-
2007
- 2007-01-31 CN CN200780049019A patent/CN101617400A/zh active Pending
- 2007-01-31 JP JP2008555983A patent/JP5120266B6/ja not_active Expired - Fee Related
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2009
- 2009-06-08 US US12/479,915 patent/US8018033B2/en not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
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JP5120266B2 (ja) | 2013-01-16 |
KR101057368B1 (ko) | 2011-08-18 |
US8497156B2 (en) | 2013-07-30 |
KR20090087076A (ko) | 2009-08-14 |
JPWO2008093414A1 (ja) | 2010-05-20 |
US8018033B2 (en) | 2011-09-13 |
WO2008093414A1 (ja) | 2008-08-07 |
US20110294261A1 (en) | 2011-12-01 |
US20090236700A1 (en) | 2009-09-24 |
CN101617400A (zh) | 2009-12-30 |
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