CN1755929B - 形成半导体封装及其结构的方法 - Google Patents

形成半导体封装及其结构的方法 Download PDF

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Publication number
CN1755929B
CN1755929B CN2004100120851A CN200410012085A CN1755929B CN 1755929 B CN1755929 B CN 1755929B CN 2004100120851 A CN2004100120851 A CN 2004100120851A CN 200410012085 A CN200410012085 A CN 200410012085A CN 1755929 B CN1755929 B CN 1755929B
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Prior art keywords
lead
layer
sealant
conductive layer
dice
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CN1755929A (zh
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王志杰
刘建勇
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Freescale Carle Semiconductor (china) Co Ltd
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Freescale Carle Semiconductor (china) Co Ltd
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Priority to CN2004100120851A priority Critical patent/CN1755929B/zh
Priority to KR1020077009718A priority patent/KR20070058680A/ko
Priority to JP2007533536A priority patent/JP2008515189A/ja
Priority to PCT/US2005/032678 priority patent/WO2006036548A2/en
Priority to US11/576,152 priority patent/US8138584B2/en
Priority to DE112005002369T priority patent/DE112005002369T5/de
Publication of CN1755929A publication Critical patent/CN1755929A/zh
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Abstract

本发明的形成半导体封装及其结构的方法，通过在一个密封剂(32)上形成一个导电层(34，46)，形成一个电磁干涉(EMI)和/或电磁辐射屏蔽。导电层包括一导电胶(38，48，52)和一个金属涂漆(36，50)的组合。一个线环(30)耦合导电层和一个引线框架(10)。

Description

形成半导体封装及其结构的方法
技术领域
本发明总体上涉及半导体器件封装，尤其涉及射频屏蔽的半导体器件封装。
背景技术
半导体器件外壳或集成电路芯片载体用于高密度电子应用中。通过对器件用环氧材料密封或用热塑树脂传递模塑，来保护集成电路或半导体器件免于接触外部环境。然而，塑料密封剂不能提供对射线的屏蔽，例如射频干涉(RFI)或电磁干涉(EMI)。
当电路变得越来越小、更密集，并且工作于更高频率和更苛刻环境，在屏蔽电路免于辐射例如射频干涉(RFI)和电磁干涉(EMI)存在增长的需求。例如，蜂窝电话和其它移动设备需要受到保护免于这种辐射。安装在火花塞附近的汽车电路例如微型控制器需要屏蔽。传统封装不能保护装在其中的半导体器件免于这种电磁波。
传统屏蔽***使用一个导电金属外壳围绕需要屏蔽的电路。这种外壳保护内部电路免受EMI和RFI以及阻止由电路产生的EMI或RFI的漏出。另一种解决方法是在模塑封装前在半导体器件上放置一块金属帽。这种解决方法可应用于具有大的半导体单元片(die)(例如，至少一平方英寸)的球球栅阵列(BGA)封装。还有另外一种解决方案是在密封器件上提供一个金属镀层。然而，所有这些解决方案都有一些缺点。例如，使用导电金属外壳增加了封装的整体尺寸，并且需要额外的焊接步骤来给器件贴上金属屏蔽物，由额外的焊接工艺产生的热潜在地危害器件。
因此，存在节省成本的元件级的屏蔽的需求，能够应用于对任何半导体单元片尺寸的各种封装。
发明内容
本发明是一个半导体封装，含有一个铺垫层(flag)和一个引线指(lead finger)的引线框架，一个半导体单元片贴在铺垫层上并电学地耦合到引线指，一种在半导体单元片上的密封剂，在密封剂上的一个导电层，一个导线将引线框架电学地耦合到导电层。导电层包括一个屏蔽金属和一种导电胶的组合。导电胶和屏蔽金属的组合阻止了导电层从模塑密封剂上剥落。
本发明还提供了一个形成半导体外壳的方法，包括步骤：
提供一个含有一个铺垫层和多个引线指的引线框架；
将一个半导体单元片贴在铺垫层上；
将半导体单元片电学地耦合到引线指；
形成一个电学地连接到引线框架的线环；
将半导体单元片和至少一部分线环用密封剂密封；以及
在密封剂上形成一个导电层，其中导电层包括一个屏蔽金属和一种导电胶的组合，线环接触导电层，由此电学上将引线框架耦合到导电层。
本发明进一步提供一个形成半导体封装的方法，包括步骤：
提供一个含有第一和第二引线框架的引线框架面板，第一和第二引线框架的每一个包括一个铺垫层和多个引线指。
第一和第二半导体单元片分别贴在第一和第二引线框架的铺垫层上；
将第一和第二半导体单元片电学地分别耦合到第一和第二引线框架的引线指上；
提供一个含有第一端和第二端的引线键合；
引线键合的第一端电学上耦合到第一引线框架的引线指，并且引线键合的第二端耦合到第二引线框架的引线指；
在密封剂和线环上形成一个导电层，其中导电层电学地耦合到线环的暴露部分，并且其中导电层包括一个屏蔽金属和一种导电胶的组合；以及
切割引线框架面板，形成第一和第二封装器件。
附图说明
下面结合附图阅读将更好地理解本发明一个优选实施例的详细描述。本发明通过实例来示例说明，且不局限于附图，其中相似参考代表相似单元。
图1是根据本发明一个实施例的切割前多个器件的放大的横切面图；
图2是根据本发明另一个实施例的切割前多个器件前的放大的横切面图；
图3是本发明一个实施例的用于封装工艺中的掩模的顶部平面图；
图4示例说明了根据本发明形成一个半导体封装方法的流程图。
本领域的技术人员将会理解，图中单元是为了简化和清晰的图示，并不必按比例尺画出。例如，图中某些单元的尺寸相对于其他单元会相对夸大，以有助于提高本发明实施例的理解。
具体实施方式
下面联系附图提出的详细描述，目的是用来描述本发明目前优选实施例，但并不是用来代表本发明实现的唯一形式。需要要理解的是，相同或相等功能可以由围绕本发明的精神和范围的不同的实施例实现。
本发明是一个半导体封装，含有一个铺垫层(flag)和一个引线指(lead finger)的引线框架，一个半导体单元片贴在铺垫层上并电学地耦合到引线指，一种在半导体单元片上的密封剂，在密封剂上的一个导电层，一个导线将引线框架电学地耦合到导电层。导电层包括一个屏蔽金属和一种导电胶的组合。导电胶和屏蔽金属的组合阻止了导电层从模塑密封剂上剥落。
本发明还提供了一个形成半导体外壳的方法，包括步骤：
提供一个含有一个铺垫层和多个引线指的引线框架；
将一个半导体单元片贴在铺垫层上；
将半导体单元片电学地耦合到引线指；
形成一个电学地连接到引线框架的线环；
将半导体单元片和至少一部分线环用密封剂密封；以及
在密封剂上形成一个导电层，其中导电层包括一个屏蔽金属和一种导电胶的组合，线环接触导电层，由此电学上将引线框架耦合到导电层。
本发明进一步提供一个形成半导体封装的方法，包括步骤：
提供一个含有第一和第二引线框架的引线框架面板，第一和第二引线框架的每一个包括一个铺垫层和多个引线指。
第一和第二半导体单元片分别贴在第一和第二引线框架的铺垫层上；
将第一和第二半导体单元片电学地分别耦合到第一和第二引线框架的引线指上；
提供一个含有第一端和第二端的引线键合；
引线键合的第一端电学上耦合到第一引线框架的引线指，并且引线键合的第二端耦合到第二引线框架的引线指；
在密封剂和引线键合上形成一个导电层，其中导电层电学地耦合到线环的暴露部分，并且其中导电层包括一个屏蔽金属和一种导电胶的组合；以及
切割引线框架面板，形成第一和第二封装器件。
现在参考图1，一个引线框架面板10的一部分包括第一器件部分12、第二器件部分14和第三器件部分16。引线框架面板10可以包括用于任何半导体封装的引线框架，例如四角平坦无引线(QFN)外壳，也称为微引线框架外壳(MLF)和凸点芯片载体(BCC)；一个球栅阵列封装(BGA)；方型扁平式封装(QFP)；或其它可以使用模塑工艺形成或切割形成的任何封装，如下面将更详细地解释的。引线框架面板10可以为任何导电材料，例如包括镍和铁的合金；镍钯等。引线框架面板10可以作为图形化的引线框架被支起，该引线框架含有键合焊垫和已经形成希望图形的接地焊垫。尽管仅仅三个器件部分在图1中图示说明，它还可以存在更多其它器件部分。例如，引线框架面板10可以包括任何数目的器件部分。在所示的实施例中，每个器件部分为了制作简单具有同样结构；然而，这并不是必须的。
第一、第二和第三器件部分12、14和16的每一个包括一个铺垫层18和围绕铺垫层18的多个引线指20。铺垫层18不局限于任何特殊形状。相反，铺垫层18可以为引线框架面板10中的一个开的窗口，“X形状”等。此外，相对于引线框架面板10的其它区域，铺垫层18可以上升或下凹。
如果随着期望的形成引线指20，引线框架面板10没有支起，可以通过制作布线图案和刻蚀形成引线指20，如技术上已经众所周知的。引线指20可以包括分立的接地焊垫。接地焊垫是专用于耦合EMI屏蔽、导电层或器件到接地的引线指，熟练的技术人员将认识到引线指20的数目和它们的配置仅仅是图示的表示。
铺垫层18接收一个半导体单元片或集成电路22。更具体而言，半导体单元片22从半导体晶片上切下，使用工业上已知的挑拣和放置工具放置在每个铺垫层18上。每个单元片22使用粘接剂贴在各自的每个铺垫层18上，如技术上所已知的。在一个实施例中，一个半导体单元片放置在一个铺垫层上。在另一个实施例中，多于一个半导体单元片放在一个铺垫层上。例如，一个半导体单元片相邻另一个半导体单元片放置在同一个铺垫层上，或者在同一个铺垫层上一个堆叠在另一个半导体单元片上。这样，多个单元片可以放置在一个铺垫层上，在同一个平面内或互相相对堆叠。在图1所示的实施例中，第二单元片24贴在半导体单元片22顶部。第二单元片24可以为另一个含有一个集成电路或者一个微机械元件的半导体单元片，例如微机械***(MEMS)，它是在普通硅衬底上机械元件、传感器、衰减器和电子学的集成。第二单元片24大小可以和第一单元片22一样，但是并不是必须的，如技术上已知的在一个底单元片上堆叠较大的或较小单元片。第二单元片24可以以各种方式与第一单元片22隔开，例如技术上已知的使用垫片25。
每个单元片22电学地耦合到引线指20。在本实例中，单元片22包括用第一导线26连接引线指20多个键合焊垫(未标出)。第一导线26由一种导电材料形成，例如铝或金。在一个实施例中，第一导线26直径约一英寸的1/1000-1/2000。典型地，使用球压焊将第一导线26引线键合到引线指20上，使用商业上可用的引线键合设备通过跳焊键合到单元片键合焊垫。然而，其它连接也是可能的，例如倒装芯片凸点，本发明并不局限于单元片22与引线指20耦合的方式。
第二单元片24通过第二导线28，也连接至少一个第一单元片22和引线指20。第二导线28优选与第一导线26有同样尺寸和由同样导电材料形成。如果半导体单元片22-24通过引线键合电学地耦合在一起，那么在同一个引线键合工艺中，相邻器件部分的接地焊垫也可以电学地耦合在一起。在一个实施例中，与上面描述的使用引线键合一个半导体单元片到一个接地焊垫一样，使用引线键合将接地焊垫互相引线键合来完成耦合。然而，如果导线在例如尺寸不同时，可以使用一个分立的引线键合工艺耦合接地焊垫和键合焊垫。
一个额外导线30引线键合到第二(顶部)单元片24。额外导线30优选电学地耦合到第二单元片24的一个接地焊垫上，并且通过导线28和26，耦合到引线框架的一个接地焊垫上。额外导线30具有相对较高的环高度，使得导线30延伸超过密封剂，如下面更仔细地描述。在图1中所示的实施例中，额外导线30从第二单元片24向上延伸。如果形成的器件仅仅有单个单元片，例如单元片22，那么额外导线30可以从这个单元片向上延伸。作为选择，额外导线30可以从一个器件的接地焊垫延伸到一个相邻器件的接地焊垫。既然额外导线30很细，在接下来的模塑密封工艺中它易于断裂或被破坏。模塑密封工艺中通过调整额外导线30方向为模塑密封剂将要流动方向，额外导线30更可能保持它们的形状以及不断裂。相反，如果模塑密封剂以向额外导线30九十(90)度的方向流动，那么额外导线30更容易断裂。避免了上面描述的使用细导线和模塑流向的问题，可以使用更细的导线。
额外导线30引线键合到第二单元片24上后，完成一个模塑密封工艺，在第一和第二单元片22、24和导线24、26、28和30上形成模塑混合物或模塑密封剂32。模塑密封剂32可以为一种填充氧化硅的树脂，一种陶瓷，一种无卤化物材料等，或上面材料的组合。模塑密封剂32典型地使用液体加入其中，通过在UV或环境气氛中硬化，加热形成固体。模塑密封剂32还可以是一种固体，加热形成液体，然后在单元片22和24上冷却形成固体塑模。可以使用任何其它密封工艺。额外导线30延伸超出密封剂32并且暴露出来。在单元片22和24上形成密封剂32后，完成一种去除或清洗，以暴露额外导线30。可以使用任何传统去除或清洗。去除工艺可以包括无处理，一种化学工艺，一种高压水工艺或一种机械工艺。
密封之后，一个导电层34形成在密封剂32和导线30暴露部分上。导电层34包括一个屏蔽金属层36和一个导电胶层38的组合。导电胶层38可以包括环氧树脂。屏蔽金属层36可以是一种聚合物、金属、金属合金(例如一种铁磁或铁电材料)、油墨等，或以上的组合。在一个实施例中，金属层36是铝(Al)、铜(Cu)、镍铁(NiFe)、锡(Sn)、锌(Zn)等或或以上的组合。如果金属层36是有色金属(例如Al、Cu、Sn和Zn)，那么金属层36和额外导线30用来保护器件部分免于EMI，通过半导体单元片22和24通过接地焊垫接地到金属层36。如果使用一种铁磁材料(例如NiFe)，金属层36将保护器件部分免于磁辐射，这在如果半导体单元片22和24包括一个磁随机存取存储器(MRAM)器件时是很有用的。这样，如果仅仅需要保护占主要地位的磁辐射，那么可以不存在额外导线30。然而，如果一起使用一种非铁磁材料和铁磁材料，例如一层铜层和一层NiFe层形成金属层36，那么器件部分受到电磁或宽带屏蔽的保护免于电和磁的场合，如果半导体单元片22和24包含例如MRAM器件和晶体管时，这将会很有用处。
在图1所示的实施例中，导电层34涂在密封剂32上，通过将第一层导电胶38涂在密封剂32的预定位置，例如通过一个掩模或掩模板。即，一个掩模板放置在塑模的器件上，然后一个导电胶层38涂在密封剂32的暴露部分。然后去掉掩模，一个屏蔽金属层36涂在密封剂32的新暴露部分。最后，另一个导电胶层38涂在屏蔽金属层36上。在这种方法中，屏蔽金属36和导电胶38的组合涂在密封剂32上。胶38和金属36的混合允许金属层36牢牢地固定在密封剂32上，使得当暴露在环境应力中时金属不能从密封剂上分离。
屏蔽金属层36可以通过物理气相沉积(VPD)、化学气相沉积(CVD)、原子层沉积(ALD)、电解质电镀、化学镀、火焰喷涂、导电喷漆、真空金属喷镀、焊垫印刷等方法沉积，或以上方法的组合。金属层36可以大约1-50微米厚，优选5-7微米厚。金属层36的厚度依赖于希望屏蔽的效用。金属层36的最小厚度依赖于形成金属层36的工艺，最大厚度依赖于金属层36的应力量，它至少是所使用金属的一个函数。
尽管如上面所述的，额外导线30将屏蔽金属层36电学地耦合到接地焊垫上，导线30不需要电学地耦合到接地焊垫以提供EMI保护。如果接地焊垫的布局、半导体单元片尺寸和铺垫层尺寸允许的话，导线30可以耦合任何未用的接地或将要接地的键合焊垫，而不是接地焊垫。换句话说，接地键合焊垫可以为任何未用的键合焊垫，如果当器件部分切割成一个封装并贴在印刷电路板(PBC)上时，未用的键合焊垫接地或者基本上接地。
当导电层34沉积上或涂上后，每个器件部分从另一部分切割下来。换句话说，每个器件部分可以切成或锯成单个器件部分。在器件12、14和16之间划线，图示表明器件部分切割的地方。
现在参考图2，给出了根据本发明另一个实施例在切割之前，多个器件部分40、42、44形成在一个引线框架面板上。器件部分40、42和44类似图1的器件12、14和16。即，器件部分包括堆叠的半导体单元片22和24，由一个垫片25分开，电学地互相耦合并由导线26和28耦合到引线指20。额外导线30从第二单元片24向上延伸。单元片22和24以及导线26、28和30由一种密封剂32覆盖，并且暴露部分导线30。如图1所示的实施例，图示说明了单元片22和24的数目和配置。
形成模塑密封剂32后，完成去除或清洗，以暴露额外导线30。可以使用任何传统的去除或清洗。去除工艺可以包括无处理，一种化学处理，一种高压水处理或一种机械处理。暴露一部分导线30之后，可以是上面讨论的用于导电层34的任何材料的一个导电层46，形成于密封剂32和导线30暴露部分上。导电层46和铺垫层18形成EMI或电磁屏蔽，依赖于用于导电层46的材料。这样，导线30耦合到导电层46，并且因此接地。在形成导电层46之后通过对封装切割，形成一个单个封装的半导体器件。
在该第二实施例中，导电层46由第一导电胶层48，第二屏蔽金属层50，第三导电胶层48形成。更一般而言，第一导电胶层48形成在密封剂32表面上。该第一层48应该相对较薄，在3-5微米量级。然后，第二金属屏蔽层50形成在第一层48上。第二层50优选使用掩模板或掩模进行网丝印刷或涂漆，使得未涂漆区环绕涂漆区。然后第三导电胶层52形成在模板金属层50上。在这种方式下，第一和第三层48和52互相接触，并且由于第一层48固定在密封剂32上，金属层50牢固地附着密封剂32。
现在参考图3，图示出了掩模板60的顶视图。根据第一实施例(图1)，掩模板60用于在密封剂32上形成第一导电胶层38，或者根据第二实施例(图2)在第一导电胶层48上形成第二屏蔽金属层50。掩模板60可以由坚固、相对坚硬的材料制成，例如不锈钢或其它合适材料，在上面含有以均匀图案形成的孔62。孔62可以为任何形状，例如圆形或矩形，大小和间距依赖于屏蔽条件。在一个实施例中，掩模板60制作成含有直径约250um，间距约80um。
图4示例说明了根据本发明形成一个半导体封装方法的流程图。在第一步骤70中，提供了一个含有一个铺垫层和一个引线指的引线框架，例如上面描述的。在第二步骤72中，一个半导体单元片贴在引线框架铺垫层上，第三步骤74中，单元片电学地耦合到引线框架的引线指上。然后，在步骤76中，形成一个线环并且电学地连接到引线框架上，然后在步骤78中，单元片和至少一部分线环使用塑料材料或密封剂密封起来。如果线环没有暴露出，然后完成步骤80，以暴露部分线环。在该点处，器件已经准备好屏蔽。在一个实施例中，完成步骤82，其中一个导电胶层形成在密封剂上，然后在步骤84中，使用掩膜或掩模板将一屏蔽金属层涂漆或印刷在第一胶层。然后，在步骤86中，另一个导电胶层形成在第一胶层和金属掩模层上。既然金属层不是连续的，第一和第二胶层混合在一起并在密封剂上坚固地固定金属层。另外，线环接触导电层，因此导电层电学地耦合到引线框架上。如果不完成步骤82，那么在步骤84中，使用掩膜或掩模板将第一导电胶层形成在密封剂上，然后金属层形成在掩模的胶层上。然后在步骤84中，第二导电胶层形成在第一掩模层和金属层上。第二胶层结合了第一胶层并牢固地将金属层附着着密封剂。如果同时形成多个封装，那么完成切割步骤90以形成多个分立的封装。
应当理解，已经在器件水平提供了一个EMI和/或电磁屏蔽工艺。该工艺希望尤其适合于QNF，因为可以不需要额外工艺设备就可以完成该工艺。而且，该工艺是一种在器件水平上防止EMI和/或电磁辐射的节省成本的方式。使用导线使导电层接地对列阵模塑封装例如QFN尤其有用(即，既不预先模塑也不单个模塑)。预先模塑封装，如同陶瓷无引线芯片载体(CLCC)，它使用各种陶瓷层制作，可以通过含有接地的顶金属帽并通过通孔焊接到底接地平面，来防止EMI。在引线框架暴露在第一边的QFN或其它封装中，以及在第二边模塑的多列阵封装(MAP)中，模塑化合物完全覆盖第二边。既然在MAP模塑引线框架中的单个器件互相靠近地放置，单个帽不能够给每个器件都放置，并且在模塑工艺中保持有间距。在模塑前加大相邻器件的间距并使用单个帽会非常昂贵，此外还有其它的技术挑战。放置和保持住单个帽会非常困难并且妨碍模塑工艺本身。由于无预先模塑封装的工艺流程，不能使用金属帽。此外，用于将通孔放进CLCC中的工艺不同于用于形成QFN、BGA等类型封装的模塑工艺。例如，在QFN型封装中形成通孔，通孔将不得不形成在模塑密封剂中，这能够增加制造成本和复杂性。
实现本发明的装置，在极大程度上包括本领域的技术人员已熟知的电子设备和电路。因此，没有在更大程度上说明电路的细节，该考虑的程度对于理解和评价本发明下面的概念是必须的，并且为了从本发明讲解中不会模糊或分散注意力。
在前述的说明中，本发明已经参考具体的实施例进行描述了。然而，本领域普通技术人员将理解，可以进行各种修改和变化，而不背离本发明如下面权利要求所提出的范围。因此，说明书和图形将作为一个示例，而不是一个限制因素，并且所有这些修改都要包括进本发明的范围。
上面已经描述了关于具体实施例的好处、其它优点以及问题的解决方法。然而，好处、优点以及问题的解决方法，以及可以导致任何好处、优点以及要出现的或变得更加明确的解决方法的任何要素，并不能认为是任何或所有权利要求的一个关键、必须和本质的特征或要素。如在这里使用的，术语“包括”“由...构成”或对它们任何其它的变化，目的是要覆盖一种非排它的包括，使得包括一系列要素的一个工艺、方法、条款或仪器不仅仅包括那些要素，而是要包括其它没有明显地列出或对这样的工艺、方法、条款或仪器所固有的要素。在此使用的术语“一个”或“一种”，定义为一个或多于一个。在此使用的术语“多个”定义为两个或多于两个。在此使用的术语“另一个”定义为至少的二个或更多。在此使用的术语“耦合”定义为连接，尽管不必是直接地，以及不必是机械地连接。此外，在描述中及在权利要求中的术语“前”、“后”、“顶”、“底”、“上”、“下”等，如果有，用于描述的目的，而不必用于描述永久的相对位置。可以理解，这样使用这些术语在适当的场合是可以互换的，使得在此描述的本发明的实施例，例如能够适合在其它场合工作，而不是那些在此示例或其它描述的场合。

Claims (5)

1.一种形成半导体封装的方法，包括步骤：
提供一个含有第一和第二引线框架的引线框架面板，第一和第二引线框架的每一个包括一个铺垫层和多个引线指；
将第一和第二半导体单元片分别附着在第一和第二引线框架的铺垫层上；
将第一和第二半导体单元片分别电学地耦合到第一和第二引线框架的引线指上；
提供一个具有第一端和第二端的导线；
将导线的第一端电学地耦合到第一引线框架的引线指，并且将导线的第二端耦合到第二引线框架的引线指；
在第一和第二半导体单元片与导线上形成密封剂，其中一部分导线是暴露的；
在密封剂和导线上形成一个导电层，其中导电层电学地耦合到导线的暴露部分，并且其中导电层包括一个屏蔽金属和导电胶的组合；以及
切割引线框架面板，以形成第一和第二封装器件。
2.根据权利要求1形成半导体封装的方法，其中密封剂形成步骤包括：
在第一和第二半导体单元片和导线上形成密封剂；以及
通过去掉一部分密封剂，暴露一部分导线。
3.根据权利要求1形成半导体封装的方法，其中形成一个导电层的步骤包括：
在密封剂上形成包括屏蔽金属的第一层，其中屏蔽金属通过掩模板施加在密封剂上；
在密封剂和屏蔽金属上形成包括导电胶的第二层，其中第二层接触第一层和密封剂。
4.根据权利要求1形成半导体封装的方法，其中形成一个导电层的步骤包括：
在密封剂上形成第一导电胶层；
在第一层上形成包括屏蔽金属的第二层，其中屏蔽金属通过掩模板施加在第一层上；
在第一层和第二层上形成包括导电胶的第三层，其中第三层接触并粘附第一和第二层。
5.根据权利要求1形成半导体封装的方法，其中屏蔽金属包括一种铁磁材料。
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US8138584B2 (en) 2012-03-20
CN1755929A (zh) 2006-04-05
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DE112005002369T5 (de) 2007-08-16
US20090184403A1 (en) 2009-07-23

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