KR970052338A - 반도체 소자의 제조방법 - Google Patents

반도체 소자의 제조방법 Download PDF

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Publication number
KR970052338A
KR970052338A KR1019950055134A KR19950055134A KR970052338A KR 970052338 A KR970052338 A KR 970052338A KR 1019950055134 A KR1019950055134 A KR 1019950055134A KR 19950055134 A KR19950055134 A KR 19950055134A KR 970052338 A KR970052338 A KR 970052338A
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KR
South Korea
Prior art keywords
insulating film
film
voltage
semiconductor device
manufacturing
Prior art date
Application number
KR1019950055134A
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English (en)
Inventor
신동선
이정래
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950055134A priority Critical patent/KR970052338A/ko
Priority to GB9626363A priority patent/GB2308735A/en
Priority to US08/772,169 priority patent/US5902122A/en
Priority to JP8340789A priority patent/JPH09186155A/ja
Priority to CN96123921A priority patent/CN1097303C/zh
Priority to DE19654096A priority patent/DE19654096B4/de
Publication of KR970052338A publication Critical patent/KR970052338A/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

본 발명은 SOG막을 표면 평탄화막으로 사용하는 금속층간 절연막을 형성할 때, SOG막의 수분이 하부 금속 배선으로 확산되는 것을 방지하기 위해 제1절연막을 형성하고, 제1절연막상에 SOG막을 도포하기 전에 N2또는 N2O 플라즈마 피폭 처리를 하여 제1절연막에 흡수 또는 흡착된 수분을 제거한 상태에서 SOG막을 도포 및 경화하므로써, SOG막의 들뜸현상이나 갈라지는 현상을 방지할 수 있다. 따라서, 본 발명은 SOG막의 들뜸현상이나 갈라지는 현상으로 인한 소자의 불량률과 공정실패 확률을 감소시킬 수 있어 수율을 증대시킬 수 있다.

Description

반도체 소자의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2A도 내지 제2C도는 본 발명의 실시예에 의한 반도체 소자의 제조 방법을 설명하기 위해 도시한 소자의 단면도.

Claims (5)

  1. 반도체 소자의 제조방법에 있어서, 폴리-금속 층간절연막상에 하부 금속배선이 형성된 실리콘 기판이 제공되고, 상기 하부 금속배선을 포함한 상기 폴리-금속 층간절연막상에 제1절연막이 형성되는 단계; 플라즈마 피폭을 실시하여 상기 제1절연막상에 생성되는 수분을 제거하는 단계; 및 상기 제1절연막상에 SOG막 및 제2절연막을 순차적으로 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 제조방법.
  2. 제1항에 있어서, 상기 제1절연막은 TEOS 산화막 SiH4산화막 및 실리콘 과다 산화막 중 어느 하나인 것을 특징으로 하는 반도체 소자의 제조방법.
  3. 제1항에 있어서, 상기 플라즈마 피폭은 0.5 내지 5SLM의 유량과 1내지 3Torr의 압력에서 300 내지 450℃의 온도로 웨이퍼를 가열한 상태에서 RF전압을 인가하여 N2플라즈마를 발생시켜 실시되는 것을 특징으로 하는 반도체 소자의 제조방법.
  4. 제1항에 있어서, 상기 플라즈마 피폭은 0.5 내지 5SLM의 유량과 1 내지 3Torr의 압력에서 300 내지 450℃의 온도로 웨이퍼를 가열한 상태에서 RF전압을 인가하여 N2O 플라즈마를 발생시켜 실시되는 것을 특징으로 하는 반도체 소자의 제조방법.
  5. 제3항 또는 제4항에 있어서, 상기 RF전압은 13.56MHz의 고주파수 RF전압과 400 내지 500KHz의 저주파수 RF전압을 0.2~0.9:1의 비율로 인가하는 것을 특징으로 하는 반도체 소자의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950055134A 1995-12-23 1995-12-23 반도체 소자의 제조방법 KR970052338A (ko)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019950055134A KR970052338A (ko) 1995-12-23 1995-12-23 반도체 소자의 제조방법
GB9626363A GB2308735A (en) 1995-12-23 1996-12-19 A method of manufacturing a semiconductor device
US08/772,169 US5902122A (en) 1995-12-23 1996-12-20 Method of manufacturing an ILD layer by plasma treatment before applying SOG
JP8340789A JPH09186155A (ja) 1995-12-23 1996-12-20 半導体素子の製造方法
CN96123921A CN1097303C (zh) 1995-12-23 1996-12-23 一种制造半导体器件的方法
DE19654096A DE19654096B4 (de) 1995-12-23 1996-12-23 Verfahren zur Herstellung eines Halbleiterbauelementes

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950055134A KR970052338A (ko) 1995-12-23 1995-12-23 반도체 소자의 제조방법

Publications (1)

Publication Number Publication Date
KR970052338A true KR970052338A (ko) 1997-07-29

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ID=19443602

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950055134A KR970052338A (ko) 1995-12-23 1995-12-23 반도체 소자의 제조방법

Country Status (6)

Country Link
US (1) US5902122A (ko)
JP (1) JPH09186155A (ko)
KR (1) KR970052338A (ko)
CN (1) CN1097303C (ko)
DE (1) DE19654096B4 (ko)
GB (1) GB2308735A (ko)

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KR19980055721A (ko) * 1996-12-28 1998-09-25 김영환 반도체 소자의 보호막 형성 방법
GB2322734A (en) * 1997-02-27 1998-09-02 Nec Corp Semiconductor device and a method of manufacturing the same
US6284663B1 (en) * 1998-04-15 2001-09-04 Agere Systems Guardian Corp. Method for making field effect devices and capacitors with thin film dielectrics and resulting devices
US6165897A (en) * 1998-05-29 2000-12-26 Taiwan Semiconductor Manufacturing Company Void forming method for fabricating low dielectric constant dielectric layer
US6472755B1 (en) 1999-01-05 2002-10-29 Advanced Micro Devices, Inc. Semiconductor device comprising copper interconnects with reduced in-line copper diffusion
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US6146988A (en) * 2000-01-05 2000-11-14 Advanced Micro Devices, Inc. Method of making a semiconductor device comprising copper interconnects with reduced in-line copper diffusion
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100470129B1 (ko) * 2002-01-25 2005-02-04 학교법인 포항공과대학교 계면특성이 우수한 박막 트랜지스터의 제조방법

Also Published As

Publication number Publication date
CN1160928A (zh) 1997-10-01
US5902122A (en) 1999-05-11
GB2308735A (en) 1997-07-02
DE19654096B4 (de) 2010-06-02
JPH09186155A (ja) 1997-07-15
GB9626363D0 (en) 1997-02-05
DE19654096A1 (de) 1997-06-26
CN1097303C (zh) 2002-12-25

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