CN1097303C - 一种制造半导体器件的方法 - Google Patents

一种制造半导体器件的方法 Download PDF

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CN1097303C
CN1097303C CN96123921A CN96123921A CN1097303C CN 1097303 C CN1097303 C CN 1097303C CN 96123921 A CN96123921 A CN 96123921A CN 96123921 A CN96123921 A CN 96123921A CN 1097303 C CN1097303 C CN 1097303C
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insulating barrier
layer
interlayer insulating
insulating film
semiconductor device
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CN1160928A (zh
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辛东善
李正来
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SK Hynix Inc
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Hyundai Electronics Industries Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

提供一种制造半导体器件的方法。在硅衬底上面形成下面金属层，在下面金属层上形成第1层间绝缘层。在包含下面金属层的第1层间绝缘层上形成第1绝缘层，利用N2和N2O等离子除掉包含在第1绝缘层中的水分。因此，在第1绝缘层上依次地形成SOG层和第2绝缘层。

Description

一种制造半导体器件的方法
本发明涉及制造半导体器件的方法，特别涉及能防止SOG(旋涂玻璃)层剥落和破裂的制造半导体器件的方法，该层用于平面化多层金属结构中的层间绝缘层。
在具有多层金属结构的半导体器件中，形成层间绝缘层，以便在下层金属层和上层金属层之间进行绝缘。层间绝缘层由包含SOG层的许多绝缘层组成，以便改善表面的平面化。SOG层有优良的平面化表面，但是，由于它有强的亲水性，使它包含大量的水分。因此，在形成SOG层之前，形成绝缘层以便防止在SOG层中含有的水分穿入下面的金属层。
但是按照绝缘层的形成条件，在形成绝缘层后，在大气中吸收的水分进入或进到该绝缘层。绝缘层中包含的水分，在固化SOG层时，使SOG层剥落或者破裂。
图1A和图1B是表示制造半导体器件常规方法的剖视图。
参看图1A，在硅衬底1上形成第1层间绝缘层2，利用金属布线工艺在第1层间绝缘层2上面，形成下面的金属层3，在包含下面金属层3的第1层间绝缘膜2上面形成第1绝缘层4。
通常，第1绝缘层4是利用等离子化学汽相淀积方法，由TEOS形成的氧化层，由SiH4形成的氧化层，或者额外的氧化硅层。在进行下一个工艺的中间等待时间，由于第1绝缘层4的特性，使第1绝缘层4的表面产生了微小的水滴7。即，TEOS的氧化层吸收水分，SiH4的氧化层吸收和吸附水分，特别的氧化硅层在其表面吸附水分。
参看图1B，在第1绝缘层4上面涂覆SOG层5，然后进行固化工艺。接着，在SOG层5上面，顺序地形成第2绝缘层，上面金属层和第2层间绝缘层(未表示)。在高温下，在第1绝缘层4上面产生的水滴7被蒸发掉，因此，由于蒸气压使SOG层5的部分剥落或断裂。如图1B所示，在固化工艺后，SOG层5的残缺部分6产生。
如上所述，特别是在SOG层5和下面金属层3之间的边界产生残缺的部分6。SOG层5的剥落和破裂，成为妨碍有效连续处理的因素。从完成第1绝缘层4到开始有效形成SOG层5的时间间隔越大，形成这些残留部分6的可能性越大。
因此，本发明的目的是提供一种制造半导体器件的方法，能防止用于平面化层间绝缘层的SOG层的剥落和破裂。
按照前述目的，本发明提供的制造半导体器件的方法包括下列步骤：在硅衬底上形成第一层间绝缘层；在所述第1层间绝缘层上形成下金属层；用等离子体化学汽相淀积法在所述含有所述下金属层的第一层间绝缘层上形成第一绝缘层；通过以0.5至5SLM的流速施加N2或N2O气体，同时施加13.56MHz高频射频功率和400至500KHz低频射频功率并在1至3乇的压力和300至450℃的温度下产生的等离子体以来去除去包含在所述第1绝缘层中的水份；依次形成SOG层和第二绝缘层；再在所述第2绝缘层上形成上金属层。
通过参看附图阅读关于实施例的详细说明，会理解本发明的其它目的和优点。
图1A和图1B是表示形成半导体器件已有技术方法的剖视图。
图2A、2B和2C是表示形成本发明半导体器件方法的剖视图。
下面参看附图对本发明进行详细地的说明。
参看图2A，在硅衬底11上面，形成第1层间绝缘层12，利用金属布线工艺，在第1层间绝缘层12上面形成下面金属层13。在包含下面金属层13的第1层间绝缘层12上面形成第1绝缘层14。
第1绝缘层14是利用等离子化学汽相淀积方法形成的TEOS的氧化层，SiH4的氧化层或者特别的氧化硅层。在等待进行下步工艺期间，由于第1绝缘层14的亲水特性，在第1绝缘层14的表面上产生微小水滴17。也就是，TEOS的氧化层吸收水分，SiH4的氧化层吸收和吸附水分，额外的氧化硅层在其表面吸附水分。
参看图2B，把N2或N2O等离子加到第1绝缘层14上，则由N2或者N2O等离子，把第1绝缘层14上面产生的微小水滴17蒸发掉。N2或N2O等离子和H2O反应，由Si-O键或Si-N键代替第1绝缘层14中的Si-OH键，于是除掉OH基。
用于蒸发工艺的处理室的优选条件，如上所述，是气压为1到3乇，温度在300至450℃之间(该温度与第1绝缘层的淀积温度相同)。在此条件下，把N2或N2O气体输入到处理室，流速为0.5到5SLM，然后加射频(RF)功率。于是，产生N2或者N2O等离子，并如到片子上面。最好，为了获得N2或者N2O等离子的正作用，同时施加13.56MHZ高频的RF功率和400到500KHZ低频的RF功率。此时，高频的RF功率和低频的RF功率之比为0.2到0.9∶1。
参看图2C，在除掉水分的第1层间绝缘层14上面涂覆SOG层15，以便平面化层间绝缘层，然后进行固化工艺。于是，形成稳定的SOG层15。在SOG层15上面形成第2绝缘层16，于是形成包括第1绝缘层14，SOG层15，第2绝缘层16的第2层间绝缘层20。在第2层间绝缘层20上面形成上部金属层(未表示)。
如上所述，为了除掉吸入和吸附在第1绝缘层14的水分，在第1绝缘层14上面形成SOG层15以前，利用N2或者N2O离子对第1绝缘层14进行等离子处理，这防止了包含在SOG层15的水分穿入金属层13，在固化涂覆在第1绝缘层14上面的SOG层15时，不导致由含在第1绝缘层14中的水分引起SOG层的脱落或破裂。因此，改善了半导体器件的稳定性和提高了生产率。
在不脱离本发明的精神和范围的情况下，可以对所述的工艺和结构进行各种修改和变化。因此，应当理解，上述的对工艺和结构进行的叙述和说明，只是进行举例说明，而不是对本发明的精神和范围进行限制。

Claims (3)

1.一种制造半导体器件的方法，包括下列步骤：
在硅衬底上面形成第1层间绝缘层，
在所述第1层间绝缘层上形成下金属层；
用等离子体化学汽相淀积法在所述含所述下金属层的第一层间绝缘层上形成第一绝缘层；
通过以0.5至5SLM的流速施加N2或N2O气体和同时施加13.56MHz高频射频功率和400至500KHz低频射频功率并在1至3乇的压力和300至450℃的温度下产生的等离子体来去除包含在所述第一绝缘层中的水分；
依次形成SOG层和第二绝缘层；
在所述第二绝缘层上形成上金属层。
2.按照权利要求1的方法，其特征是，所述第1绝缘层是TEOS的氧化层、SiH4的氧化层或额外氧化硅层之一。
3.按照权利要求1的方法，其特征是，所述高频射频功率和低频射频功率之比为0.2到0.9∶1。
CN96123921A 1995-12-23 1996-12-23 一种制造半导体器件的方法 Expired - Fee Related CN1097303C (zh)

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CN1160928A (zh) 1997-10-01
KR970052338A (ko) 1997-07-29
US5902122A (en) 1999-05-11
GB2308735A (en) 1997-07-02
DE19654096B4 (de) 2010-06-02
JPH09186155A (ja) 1997-07-15
GB9626363D0 (en) 1997-02-05
DE19654096A1 (de) 1997-06-26

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