KR900005470A - 반도체장치 - Google Patents
반도체장치 Download PDFInfo
- Publication number
- KR900005470A KR900005470A KR1019890013817A KR890013817A KR900005470A KR 900005470 A KR900005470 A KR 900005470A KR 1019890013817 A KR1019890013817 A KR 1019890013817A KR 890013817 A KR890013817 A KR 890013817A KR 900005470 A KR900005470 A KR 900005470A
- Authority
- KR
- South Korea
- Prior art keywords
- diffusion layer
- layer electrode
- electrode
- gate electrode
- semiconductor device
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims 6
- 238000009792 diffusion process Methods 0.000 claims 17
- 239000012535 impurity Substances 0.000 claims 3
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7885—Hot carrier injection from the channel
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도~제4도는 본 발명의 1실시예에 따른 EPROM의 구조를 나타낸 평면도.
제5도는 제4도를 Y-Y방향으로 자른 단면도.
제6도는 제4도를 X-X방향으로 자른 단면도.
Claims (4)
- 제1의 확산층전극(27)및 제2의 확산층전극(207)과, 이 제1의 확산층전극(27)과 제2의 확산층전극(207)사이의 채널영역위에 형성되어 전기적으로 부유상태로 된 부유게이트전극(32), 이 부유게이트전극(32)위에 형성된 절연막(30), 이 절연막(30)위에 형성된 제어게이트전극(31)을 구비하고, 상기 제1의 확산층전극(27)및 제2의 확산층전극(207)이 상기 부유게이트전극(32)의 긴 변 방향으로 평행하게 형성되고, 부유게이트전극(32)의 짧은 변 방향에 평행하게 제어게이트전극(31)이 형성됨에 따라, 상기 제1의 확산층전극(27)및 제2의 확산층전극(207)과 제어게이트전극(31)의 배선방향이 교차되게 배치되어 있는 불휘발성 반도체장치에 있어서, 상기 제1의 확산층전극(27)및 제2의 확산층전극(207)중 부유게이트전극(32)에 인접하고 있는 부분의 불순물농도가 서로 다른 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서, 부유게이트전극(32)에 인접하고있는 제2의확산층전극(207)부분의 불순물농도가 부유게이트전극(32)에 인접하고 있는 제1의 확산층전극(27)부분을 불순물농도보다도 약 1자리수에서 2자리수까지 낮은 것을 특징으로 하는 반도체장치.
- 제1항에 있어서, 제1의 확산층전극(27)을 드레인으로 하고 제2의 확산층전극(207)을 소오스로 하여 기입동작을 하도록 된 것을 특징으로 하는 반도체장치.
- 제1항에 있어서, 제1의 확산층전극(27)을 소오스로 하고 제2의 확산층전극(207)을 드레인으로 하여 독출동작을 하도록 된 것을 특징으로 하는 반도체 장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP88-240002 | 1988-09-26 | ||
JP63-240002 | 1988-09-26 | ||
JP63240002A JP2755613B2 (ja) | 1988-09-26 | 1988-09-26 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR900005470A true KR900005470A (ko) | 1990-04-14 |
KR930003560B1 KR930003560B1 (ko) | 1993-05-06 |
Family
ID=17053003
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019890013817A KR930003560B1 (ko) | 1988-09-26 | 1989-09-26 | 반도체장치 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5053840A (ko) |
EP (1) | EP0364769B1 (ko) |
JP (1) | JP2755613B2 (ko) |
KR (1) | KR930003560B1 (ko) |
DE (1) | DE68905425T2 (ko) |
Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5304829A (en) * | 1989-01-17 | 1994-04-19 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor device |
US5087584A (en) * | 1990-04-30 | 1992-02-11 | Intel Corporation | Process for fabricating a contactless floating gate memory array utilizing wordline trench vias |
IT1243303B (it) * | 1990-07-24 | 1994-05-26 | Sgs Thomson Microelectronics | Schieramento di celle di memoria con linee metalliche di connessione di source e di drain formate sul substrato ed ortogonalmente sovrastate da linee di connessione di gate e procedimento per la sua fabbricazione |
JP2893894B2 (ja) * | 1990-08-15 | 1999-05-24 | 日本電気株式会社 | 不揮発性メモリ及びその製造方法 |
JP2793722B2 (ja) * | 1991-01-29 | 1998-09-03 | 富士通株式会社 | 不揮発性半導体記憶装置およびその製造方法 |
EP0752721B1 (en) * | 1995-06-29 | 2009-04-29 | Sharp Kabushiki Kaisha | Nonvolatile semiconductor memory and driving method and fabrication method of the same |
US5877054A (en) * | 1995-06-29 | 1999-03-02 | Sharp Kabushiki Kaisha | Method of making nonvolatile semiconductor memory |
JP3366173B2 (ja) * | 1995-07-31 | 2003-01-14 | シャープ株式会社 | 不揮発性半導体メモリの製造方法 |
US5789298A (en) * | 1996-11-04 | 1998-08-04 | Advanced Micro Devices, Inc. | High performance mosfet structure having asymmetrical spacer formation and method of making the same |
US6091100A (en) * | 1998-02-06 | 2000-07-18 | Texas Instruments - Acer Incorporated | High density NAND structure nonvolatile memories |
JP3264241B2 (ja) | 1998-02-10 | 2002-03-11 | 日本電気株式会社 | 半導体装置の製造方法 |
DE19808182C1 (de) * | 1998-02-26 | 1999-08-12 | Siemens Ag | Elektrisch programmierbare Speicherzellenanordnung und ein Verfahren zu deren Herstellung |
US6020606A (en) * | 1998-03-20 | 2000-02-01 | United Silicon Incorporated | Structure of a memory cell |
KR100295136B1 (ko) * | 1998-04-13 | 2001-09-17 | 윤종용 | 불휘발성메모리장치및그제조방법 |
JP3097657B2 (ja) * | 1998-05-13 | 2000-10-10 | 日本電気株式会社 | 半導体記憶装置とその製造方法 |
US6117762A (en) | 1999-04-23 | 2000-09-12 | Hrl Laboratories, Llc | Method and apparatus using silicide layer for protecting integrated circuits from reverse engineering |
US6396368B1 (en) | 1999-11-10 | 2002-05-28 | Hrl Laboratories, Llc | CMOS-compatible MEM switches and method of making |
US6815816B1 (en) | 2000-10-25 | 2004-11-09 | Hrl Laboratories, Llc | Implanted hidden interconnections in a semiconductor device for preventing reverse engineering |
DE10058947A1 (de) * | 2000-11-28 | 2002-07-18 | Infineon Technologies Ag | Nichtflüchtige NOR-Eintransistor-Halbleiterspeicherzelle sowie dazugehörige Halbleiterspeichereinrichtung, Herstellungsverfahren und Verfahren zu deren Programmierung |
DE10062245A1 (de) * | 2000-12-14 | 2002-07-04 | Infineon Technologies Ag | Nichtflüchtige Halbleiterspeicherzelle sowie dazugehörige Halbleiterschaltungsanordnung und Verfahren zu deren Herstellung |
US6791191B2 (en) | 2001-01-24 | 2004-09-14 | Hrl Laboratories, Llc | Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations |
DE10110150A1 (de) * | 2001-03-02 | 2002-09-19 | Infineon Technologies Ag | Verfahren zum Herstellen von metallischen Bitleitungen für Speicherzellenarrays, Verfahren zum Herstellen von Speicherzellenarrays und Speicherzellenarray |
US6740942B2 (en) | 2001-06-15 | 2004-05-25 | Hrl Laboratories, Llc. | Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact |
US6774413B2 (en) | 2001-06-15 | 2004-08-10 | Hrl Laboratories, Llc | Integrated circuit structure with programmable connector/isolator |
KR100485486B1 (ko) * | 2002-09-19 | 2005-04-27 | 동부아남반도체 주식회사 | 플래시 메모리 셀의 구조 및 그 제조 방법 |
US7049667B2 (en) | 2002-09-27 | 2006-05-23 | Hrl Laboratories, Llc | Conductive channel pseudo block process and circuit to inhibit reverse engineering |
US6979606B2 (en) | 2002-11-22 | 2005-12-27 | Hrl Laboratories, Llc | Use of silicon block process step to camouflage a false transistor |
AU2003293540A1 (en) | 2002-12-13 | 2004-07-09 | Raytheon Company | Integrated circuit modification using well implants |
US7242063B1 (en) | 2004-06-29 | 2007-07-10 | Hrl Laboratories, Llc | Symmetric non-intrusive and covert technique to render a transistor permanently non-operable |
US8168487B2 (en) | 2006-09-28 | 2012-05-01 | Hrl Laboratories, Llc | Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer |
US8754483B2 (en) | 2011-06-27 | 2014-06-17 | International Business Machines Corporation | Low-profile local interconnect and method of making the same |
US9064970B2 (en) | 2013-03-15 | 2015-06-23 | Micron Technology, Inc. | Memory including blocking dielectric in etch stop tier |
US9276011B2 (en) | 2013-03-15 | 2016-03-01 | Micron Technology, Inc. | Cell pillar structures and integrated flows |
US9437604B2 (en) | 2013-11-01 | 2016-09-06 | Micron Technology, Inc. | Methods and apparatuses having strings of memory cells including a metal source |
US9608000B2 (en) * | 2015-05-27 | 2017-03-28 | Micron Technology, Inc. | Devices and methods including an etch stop protection material |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4151021A (en) * | 1977-01-26 | 1979-04-24 | Texas Instruments Incorporated | Method of making a high density floating gate electrically programmable ROM |
US4377818A (en) * | 1978-11-02 | 1983-03-22 | Texas Instruments Incorporated | High density electrically programmable ROM |
US4267632A (en) * | 1979-10-19 | 1981-05-19 | Intel Corporation | Process for fabricating a high density electrically programmable memory array |
JPS59126674A (ja) * | 1983-01-10 | 1984-07-21 | Toshiba Corp | 情報記憶用半導体装置 |
JPS60147165A (ja) * | 1984-01-12 | 1985-08-03 | Nec Corp | 不揮発性半導体メモリセル及びその使用方法 |
JPS60182174A (ja) * | 1984-02-28 | 1985-09-17 | Nec Corp | 不揮発性半導体メモリ |
US4763177A (en) * | 1985-02-19 | 1988-08-09 | Texas Instruments Incorporated | Read only memory with improved channel length isolation and method of forming |
US4597060A (en) * | 1985-05-01 | 1986-06-24 | Texas Instruments Incorporated | EPROM array and method for fabricating |
-
1988
- 1988-09-26 JP JP63240002A patent/JP2755613B2/ja not_active Expired - Fee Related
-
1989
- 1989-09-20 US US07/409,687 patent/US5053840A/en not_active Expired - Lifetime
- 1989-09-26 KR KR1019890013817A patent/KR930003560B1/ko not_active IP Right Cessation
- 1989-09-26 EP EP89117743A patent/EP0364769B1/en not_active Expired - Lifetime
- 1989-09-26 DE DE8989117743T patent/DE68905425T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2755613B2 (ja) | 1998-05-20 |
US5053840A (en) | 1991-10-01 |
JPH0287578A (ja) | 1990-03-28 |
EP0364769A3 (en) | 1990-05-02 |
DE68905425T2 (de) | 1993-09-09 |
KR930003560B1 (ko) | 1993-05-06 |
EP0364769A2 (en) | 1990-04-25 |
DE68905425D1 (de) | 1993-04-22 |
EP0364769B1 (en) | 1993-03-17 |
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