KR910003661A - 불휘발성 반도체장치 - Google Patents
불휘발성 반도체장치 Download PDFInfo
- Publication number
- KR910003661A KR910003661A KR1019900011036A KR900011036A KR910003661A KR 910003661 A KR910003661 A KR 910003661A KR 1019900011036 A KR1019900011036 A KR 1019900011036A KR 900011036 A KR900011036 A KR 900011036A KR 910003661 A KR910003661 A KR 910003661A
- Authority
- KR
- South Korea
- Prior art keywords
- insulating film
- semiconductor device
- gate electrode
- gate
- drain
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims 8
- 239000000758 substrate Substances 0.000 claims 2
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7885—Hot carrier injection from the channel
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/05—Etch and refill
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Element Separation (AREA)
Abstract
내용 없음.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 1실시예의 단면도.
Claims (4)
- 제1도전형 반도체기판(101)상에 설치된 제2도전형 소오스 (104) 및 드레인(102)영역과, 상기 소오스(104) 및 드레인(102) 영역간의 채널영역상에 형성된 제1게이트절연막(107)을 매개로 전기적으로 부유상태로 된 제1게이트전극(108), 상기 제1게이트전극(108)상에 형성된 제2게이트졀연막(109)을 매개로 제어게이트로 되는 제2게이트전극(110)을 구비한 반조체소자를 복수개 갖춘 반도체장치에 있어서, 상기 소오스(104) 및 드레인(102)영역은 상기 채널영역을, 인접하는 소자의 채널영역과 분리하기 위한 제1절연막보다 두꺼운 제3절연막(106)의하부에설치하고 있고, 상기 인접하는 소자의 소오스(104) 및 드레인(102) 영역은 상기 제3절연막(106)으로 부터 반도체기판(101)내에 달하도록 설치된 홈(103)에 의해 분리되어 있는 것을 특징으로 하는 불휘발성 반도체장치.
- 제1항에 있어서, 상기 홈(103)은 서로 이접하는 소자의 제1게이트전극(108)단과 자기정합해서 설치된 것을 특징으로 하는 불휘발성 반도체장치.
- 제1항 또는 제2항에 있어서, 상기 제3절연막(106)은 필드절연막인 것을 특징으로 하는 불휘 발성 반도체장치.
- 제1항 또는 제2항에 있어서, 상기 제어게이트(110)는 상기 제1게이트전극(1080상에 형성된 제2절연막(109)과 상기 제3절연막(106)과 상기 홈(103)의 상방을 통해 인접하는 소자군을 결전하는 것을 특징으로 하는 불휘발성 반도체장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1191839A JPH088313B2 (ja) | 1989-07-25 | 1989-07-25 | 不揮発性半導体記憶装置及びその製造方法 |
JP01-191839 | 1989-07-25 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR910003661A true KR910003661A (ko) | 1991-02-28 |
KR930009139B1 KR930009139B1 (ko) | 1993-09-23 |
Family
ID=16281374
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019900011036A KR930009139B1 (ko) | 1989-07-25 | 1990-07-20 | 불휘발성 반도체장치 |
Country Status (5)
Country | Link |
---|---|
US (2) | US5015601A (ko) |
EP (1) | EP0410424B1 (ko) |
JP (1) | JPH088313B2 (ko) |
KR (1) | KR930009139B1 (ko) |
DE (1) | DE69013094T2 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100450828B1 (ko) * | 1994-03-31 | 2004-12-04 | 가부시끼가이샤 히다치 세이사꾸쇼 | 불휘발성반도체기억장치의제조방법 |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5051795A (en) * | 1989-11-21 | 1991-09-24 | Texas Instruments Incorporated | EEPROM with trench-isolated bitlines |
IT1236980B (it) * | 1989-12-22 | 1993-05-12 | Sgs Thomson Microelectronics | Cella di memoria eprom non volatile a gate divisa e processo ad isolamento di campo autoallineato per l'ottenimento della cella suddetta |
KR970000533B1 (ko) * | 1990-12-20 | 1997-01-13 | 후지쓰 가부시끼가이샤 | Eprom 및 그 제조방법 |
JPH05326978A (ja) * | 1992-05-21 | 1993-12-10 | Rohm Co Ltd | 半導体記憶装置およびその製造方法 |
TW299475B (ko) * | 1993-03-30 | 1997-03-01 | Siemens Ag | |
WO1994028551A1 (en) * | 1993-05-28 | 1994-12-08 | Macronix International Co., Ltd. | Flash eprom with block erase flags for over-erase protection |
US6201277B1 (en) * | 1993-08-31 | 2001-03-13 | Texas Instruments Incorporated | Slot trench isolation for flash EPROM |
DE4333979A1 (de) * | 1993-10-05 | 1995-04-13 | Gold Star Electronics | Nichtflüchtiger Halbleiterspeicher und Verfahren zu dessen Herstellung |
KR100456256B1 (ko) * | 1996-04-03 | 2005-06-17 | 소니 가부시끼 가이샤 | 반도체장치및그제조방법 |
JPH09275196A (ja) * | 1996-04-03 | 1997-10-21 | Sony Corp | 半導体装置及びその製造方法 |
US5849621A (en) | 1996-06-19 | 1998-12-15 | Advanced Micro Devices, Inc. | Method and structure for isolating semiconductor devices after transistor formation |
US5808353A (en) * | 1996-06-20 | 1998-09-15 | Harris Corporation | Radiation hardened dielectric for EEPROM |
KR100247862B1 (ko) * | 1997-12-11 | 2000-03-15 | 윤종용 | 반도체 장치 및 그 제조방법 |
US6066530A (en) * | 1998-04-09 | 2000-05-23 | Advanced Micro Devices, Inc. | Oxygen implant self-aligned, floating gate and isolation structure |
US6323516B1 (en) * | 1999-09-03 | 2001-11-27 | Advanced Micro Devices, Inc. | Flash memory device and fabrication method having a high coupling ratio |
US6242305B1 (en) * | 1999-10-25 | 2001-06-05 | Advanced Micro Devices, Inc. | Process for fabricating a bit-line using buried diffusion isolation |
JP2001168306A (ja) * | 1999-12-09 | 2001-06-22 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
JP2001230390A (ja) * | 2000-02-17 | 2001-08-24 | Mitsubishi Electric Corp | 半導体不揮発性記憶装置およびその製造法 |
KR100452037B1 (ko) * | 2002-07-18 | 2004-10-08 | 주식회사 하이닉스반도체 | 반도체 소자의 제조방법 및 그 소자 |
JP4346322B2 (ja) * | 2003-02-07 | 2009-10-21 | 株式会社ルネサステクノロジ | 半導体装置 |
JP2006054283A (ja) * | 2004-08-11 | 2006-02-23 | Nec Electronics Corp | 不揮発性半導体記憶装置,及びその製造方法 |
WO2019190525A1 (en) * | 2018-03-29 | 2019-10-03 | Nitto Belgium Nv | Adhesive tape for automatic reel change |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5141515B2 (ko) * | 1971-11-29 | 1976-11-10 | ||
US4326331A (en) * | 1979-09-17 | 1982-04-27 | Texas Instruments Incorporated | High coupling ratio electrically programmable ROM |
JPS5681974A (en) * | 1979-12-07 | 1981-07-04 | Toshiba Corp | Manufacture of mos type semiconductor device |
JPS61214446A (ja) * | 1985-03-19 | 1986-09-24 | Toshiba Corp | 半導体装置の製造方法 |
JPS6288369A (ja) * | 1985-10-15 | 1987-04-22 | Fujitsu Ltd | 半導体装置の製造方法 |
US4698900A (en) * | 1986-03-27 | 1987-10-13 | Texas Instruments Incorporated | Method of making a non-volatile memory having dielectric filled trenches |
US4855800A (en) * | 1986-03-27 | 1989-08-08 | Texas Instruments Incorporated | EPROM with increased floating gate/control gate coupling |
JPS6386560A (ja) * | 1986-09-30 | 1988-04-16 | Toshiba Corp | 半導体装置の製造方法 |
JPS63168053A (ja) * | 1986-12-27 | 1988-07-12 | Toshiba Corp | 不揮発性半導体記憶装置およびその製造方法 |
JPH0687500B2 (ja) * | 1987-03-26 | 1994-11-02 | 日本電気株式会社 | 半導体記憶装置およびその製造方法 |
US4979004A (en) * | 1988-01-29 | 1990-12-18 | Texas Instruments Incorporated | Floating gate memory cell and device |
US4951103A (en) * | 1988-06-03 | 1990-08-21 | Texas Instruments, Incorporated | Fast, trench isolated, planar flash EEPROMS with silicided bitlines |
-
1989
- 1989-07-25 JP JP1191839A patent/JPH088313B2/ja not_active Expired - Fee Related
-
1990
- 1990-07-18 US US07/553,592 patent/US5015601A/en not_active Expired - Lifetime
- 1990-07-20 KR KR1019900011036A patent/KR930009139B1/ko not_active IP Right Cessation
- 1990-07-25 DE DE69013094T patent/DE69013094T2/de not_active Expired - Fee Related
- 1990-07-25 EP EP90114270A patent/EP0410424B1/en not_active Expired - Lifetime
-
1991
- 1991-02-13 US US07/654,687 patent/US5159431A/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100450828B1 (ko) * | 1994-03-31 | 2004-12-04 | 가부시끼가이샤 히다치 세이사꾸쇼 | 불휘발성반도체기억장치의제조방법 |
Also Published As
Publication number | Publication date |
---|---|
EP0410424A2 (en) | 1991-01-30 |
JPH0355880A (ja) | 1991-03-11 |
US5015601A (en) | 1991-05-14 |
DE69013094T2 (de) | 1995-03-23 |
US5159431A (en) | 1992-10-27 |
EP0410424B1 (en) | 1994-10-05 |
KR930009139B1 (ko) | 1993-09-23 |
EP0410424A3 (en) | 1991-04-10 |
DE69013094D1 (de) | 1994-11-10 |
JPH088313B2 (ja) | 1996-01-29 |
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