WO2020220531A1 - 一种阵列基板行驱动电路及显示面板 - Google Patents

一种阵列基板行驱动电路及显示面板 Download PDF

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Publication number
WO2020220531A1
WO2020220531A1 PCT/CN2019/102478 CN2019102478W WO2020220531A1 WO 2020220531 A1 WO2020220531 A1 WO 2020220531A1 CN 2019102478 W CN2019102478 W CN 2019102478W WO 2020220531 A1 WO2020220531 A1 WO 2020220531A1
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array substrate
substrate row
virtual test
test unit
stage
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PCT/CN2019/102478
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English (en)
French (fr)
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奚苏萍
王添鸿
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020220531A1 publication Critical patent/WO2020220531A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes

Definitions

  • the present invention relates to the field of display technology, in particular to an array substrate row driving circuit and a display panel.
  • GOA Gate Driver On Array
  • Figure 1 is a schematic diagram of a conventional four-clock signal array substrate row drive circuit distribution architecture.
  • the area where the array substrate row drive signal is located can be called the busline area
  • the area where the array substrate row drive circuit is located can be called the array substrate row drive circuit area, the bus area and the array substrate row drive circuit area
  • the combined area can be called the row driving area of the array substrate.
  • the bus area is mainly arranged with multiple signal lines for transmitting various signals required by the operation of the array substrate row driving circuit. For example, as shown in Figure 1, each signal line transmits four clock signals CK1, CK2, CK3, and CK4. , Low-frequency clock signals LC1, LC2, start signal STV2, and power supply low voltage VSS.
  • the array substrate row drive circuit area is mainly arranged with various levels of array substrate row drive circuits step by step.
  • the array substrate row drive circuits of each level output corresponding scanning signals G(1), G(2)...G(n) to Scan lines at all levels of the effective display area of the panel.
  • Fig. 2 is a schematic diagram of an existing single-stage array substrate row driving circuit, showing a single-stage array substrate row driving circuit composed of four thin film transistors T11, T21, T31, and T41 for outputting a scanning signal G(n) The scan line of the corresponding level to the effective display area.
  • a scanning signal G(n) The scan line of the corresponding level to the effective display area.
  • FIG 3 is a layout diagram corresponding to the row drive circuit of the single-stage array substrate shown in Figure 2, in which the circuit functions/structures corresponding to each part of the publication diagram are generally identified in the form of a dashed frame.
  • the layout mainly identifies four Thin film transistors T11, T21, T31 and T41, clock signal CK(n) input terminal, power supply low voltage VSS input terminal, scan signal output terminal G(n), and bootstrap capacitor Cb (not shown in Figure 2).
  • the other thin film transistors connected to the thin film transistor need to be cut off by laser, and then the three terminals of the gate, source and drain of the thin film transistor are found.
  • the measuring machine tests the thin film transistor through the via hole to obtain the electrical information of the thin film transistor.
  • the three terminals of many thin film transistors are not connected with vias.
  • the three terminals of the thin film transistor T11 are not all connected with vias, and only one end is connected to the corresponding via 10, which causes The electrical properties of the thin film transistor T11 cannot be accurately obtained at the current stage.
  • the object of the present invention is to provide an array substrate row driving circuit and a display panel, which are beneficial to measuring the electrical properties of the thin film transistors in the array substrate row driving circuit.
  • the present invention provides an array substrate row drive circuit including: a plurality of single-stage array substrate row drive circuits and at least one virtual test unit that are cascaded together. From the perspective of the layout, the virtual test unit The number, placement, position, and size of thin film transistors in the single-stage array substrate row drive circuit are consistent; the source, drain, and gate of each thin film transistor in the virtual test unit are respectively provided with The corresponding via hole is connected to the corresponding via hole, and there is no connection between each thin film transistor in the virtual test unit.
  • the virtual test unit is located near the single-stage array substrate row driving circuit of the starting stage or the ending stage of the multiple single-stage array substrate row driving circuits cascaded together.
  • the layout size of the virtual test unit is consistent with the layout size of the row driving circuit of the single-stage array substrate.
  • it includes two virtual test units, a first virtual test unit and a second virtual test unit.
  • the first virtual test unit is located near the single-stage array substrate row drive circuit of the initial stage among the plurality of single-stage array substrate row drive circuits cascaded together, and the second virtual test unit is located in the cascade The single-stage array substrate row drive circuit of the final stage among the plurality of single-stage array substrate row drive circuits together.
  • amorphous silicon thin film transistors includes amorphous silicon thin film transistors.
  • indium gallium zinc oxide thin film transistors it includes indium gallium zinc oxide thin film transistors.
  • the present invention also provides a display panel, the array substrate row driving circuit area of the display panel includes the array substrate row driving circuit as described in any one of the foregoing.
  • the array substrate row drive circuit and display panel of the present invention propose a virtual test unit placement solution that is conducive to analysis; on the basis of the original array substrate row drive circuit design, by placing it in the array substrate row drive circuit area
  • the virtual test unit can quickly measure the electrical properties of the corresponding thin film transistor by using the virtual test unit, so that the entire circuit is easy to analyze.
  • Figure 1 is a schematic diagram of a conventional four-clock signal array substrate row drive circuit distribution architecture
  • FIG. 2 is a schematic diagram of a row driving circuit of an existing single-stage array substrate
  • FIG. 3 is the layout of the row driving circuit of the single-stage array substrate shown in FIG. 2;
  • FIG. 4 is a layout diagram of a virtual test unit of a preferred embodiment of the array substrate row driving circuit of the present invention.
  • FIG. 4 is a layout of a virtual test unit (test key) of a preferred embodiment of the array substrate row driving circuit of the present invention.
  • the array substrate row drive circuit of the present invention includes a plurality of single-stage array substrate row drive circuits connected together in cascade (as shown in FIG. 1), and also includes at least one virtual test unit.
  • the present invention drives the array substrate row of the display panel.
  • a virtual test unit is designed in the circuit area.
  • the layout shown in Figure 4 can be placed in the blank space near the start and/or end stages of the array substrate row drive circuit in Figure 1, so that the environment can reflect the array substrate row drive to the maximum. Thin film transistor environment in the circuit area.
  • the virtual test unit in this preferred embodiment is specifically designed based on the single-stage array substrate row drive circuit shown in FIG. 2.
  • the layout of the virtual test unit shown in FIG. 4 can be as large as that of the single-stage array substrate shown in FIG.
  • the size of the layout of the array substrate row driving circuit is generally the same; the layout shown in FIG. 4 generally identifies four thin film transistors T11, T21, T31, and T41 in the form of a dashed frame.
  • each thin film transistor T11, T21, T31, and T41 are respectively provided with corresponding via holes and connected to the corresponding via holes.
  • each thin film transistor T11 There is no connection between T21, T31 and T41.
  • the thin film transistor connected to the thin film transistor in the row driver circuit of the single-stage array substrate needs to be laser cut, and then the three-terminal connection via hole is found.
  • many thin film transistors do not have all three terminals. Connect vias.
  • the source, drain, and gate terminals are provided with corresponding vias 12, 13, and 14 respectively, and are connected to the corresponding vias 12, 13, and 14. Put it into the measuring machine to get the electrical information of the thin film transistor T11.
  • the first virtual test unit can be arranged near the single-stage array substrate row drive circuit of the initial stage among the multiple single-stage array substrate row drive circuits connected together, and the second virtual test unit can be arranged in the cascade.
  • the single-stage array substrate row driving circuit of the final stage among the multiple single-stage array substrate row driving circuits together is near.
  • the present invention is based on the original array substrate row drive design, by placing a virtual test unit near the start level and the end level of the array substrate row drive circuit area, and the virtual test unit can quickly measure the electrical properties of the corresponding thin film transistor , Through comparison and other methods, the analysis progress can be accelerated, so as to find the root cause of the problem, so that the entire circuit is conducive to analysis.
  • the array substrate row drive circuit method of the present invention is applicable to all array substrate row drive circuits of amorphous silicon (a-si) and indium gallium zinc oxide (IGZO).
  • a-si amorphous silicon
  • IGZO indium gallium zinc oxide
  • the present invention also provides a corresponding display panel.
  • the array substrate row drive circuit area of the display panel includes the aforementioned array substrate row drive circuit.
  • the array substrate row drive circuit and display panel of the present invention propose a virtual test unit placement solution that is conducive to analysis; on the basis of the original array substrate row drive circuit design, by placing it in the array substrate row drive circuit area
  • the virtual test unit can quickly measure the electrical properties of the corresponding thin film transistor by using the virtual test unit, so that the entire circuit is easy to analyze.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种阵列基板行驱动电路及显示面板，该阵列基板行驱动电路包括：级联在一起的多个单级阵列基板行驱动电路以及至少一虚拟测试单元，从版图上来看，虚拟测试单元中与单级阵列基板行驱动电路中的薄膜晶体管的数量、摆放方式、位置及大小均一致；虚拟测试单元中每个薄膜晶体管的源极、漏极及栅极三端均分别设有相应的过孔并与相应的过孔连接，虚拟测试单元中每个薄膜晶体管之间没有连接。该阵列基板行驱动电路及显示面板通过在阵列基板行驱动电路区摆放虚拟测试单元，利用虚拟测试单元能快速测量相应薄膜晶体管的电性，从而使整个电路利于解析。

Description

阵列基板行驱动电路及显示面板 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板行驱动电路及显示面板。
 背景技术
阵列基板行驱动（Gate Driver On Array，简称GOA），也就是利用现有薄膜晶体管液晶显示器中的阵列制程将栅极行扫描驱动信号电路制作在阵列基板上，实现对栅极逐行扫描的驱动方式。
当面板出现显示异常时，需要采用多方面手段对面板进行解析，找出异常的原因，但是随着面板尺寸的不断变大，很难很迅速地找出问题的根源。为了快速找出原因，判断是否是阵列基板行驱动电路出现问题，通常需要测阵列基板行驱动电路里面的薄膜晶体管（TFT）电性，但是每一级阵列基板行驱动电路里面有许多薄膜晶体管，如何快速并准确测出相应薄膜晶体管的电性，对传统的测量方法来说，始终是一个挑战。
图1是一个常规四时钟信号阵列基板行驱动电路分布架构示意图。显示面板上，阵列基板行驱动信号所处的区域可以称为总线（Busline）区，阵列基板行驱动电路所处的区域可以称为阵列基板行驱动电路区，总线区和阵列基板行驱动电路区合起来组成的区域可以称为阵列基板行驱动区。总线区内主要布置设有用于传输阵列基板行驱动电路工作时所需各种信号的多条信号线，例如图1所示，各条信号线分别传输四个时钟信号CK1、CK2、CK3及CK4，低频时钟信号LC1、LC2，起始信号STV2，以及电源低电压VSS。阵列基板行驱动电路区主要逐级布置有各级阵列基板行驱动电路，各级阵列基板行驱动电路分别输出对应的各级扫描信号G（1）、G（2）……G（n）至面板的有效显示区的各级扫描线。
图2是一种现有单级阵列基板行驱动电路示意图，绘示了由四个薄膜晶体管T11、T21、T31及T41组成的单级阵列基板行驱动电路，用于输出扫描信号G（n）至有效显示区的对应级的扫描线。对于全高清（FHD）产品，其扫描线共有1080级，也就是说其至少需要1080级如图2所示的阵列基板行驱动电路。
图3 是图2所示单级阵列基板行驱动电路对应的版（layout）图，其中以虚线框形式大体上标识出版图中各部分对应的电路功能/结构，版图中主要标识出了四个薄膜晶体管T11、T21、T31及T41，时钟信号CK（n）输入端，电源低电压VSS输入端，扫描信号输出端G（n），以及自举电容Cb（图2未示）。当采用传统的测量方法测量图3中某个薄膜晶体管时，需先将与该薄膜晶体管相连的其他薄膜晶体管通过激光切断连接，再找出该薄膜晶体管栅极、源极及漏极三端连接的过孔，量测机台经由过孔对该薄膜晶体管进行测试，获得该薄膜晶体管的电性信息。通常许多薄膜晶体管的三端并没有都连接有过孔，如图3所示版图中，薄膜晶体管T11的三端并没有全部连接过孔，仅有一端连接至相应的过孔10，这就造成薄膜晶体管T11电性无法在当级准确获得。
 技术问题
因此，本发明的目的在于提供一种阵列基板行驱动电路及显示面板，利于测量阵列基板行驱动电路中薄膜晶体管的电性。
 技术解决方案
为实现上述目的，本发明提供了一种阵列基板行驱动电路包括：级联在一起的多个单级阵列基板行驱动电路以及至少一虚拟测试单元，从版图上来看，所述虚拟测试单元中与单级阵列基板行驱动电路中的薄膜晶体管的数量、摆放方式、位置及大小均一致；所述虚拟测试单元中每个薄膜晶体管的源极、漏极及栅极三端均分别设有相应的过孔并与相应的过孔连接，所述虚拟测试单元中每个薄膜晶体管之间没有连接。
其中，所述虚拟测试单元位于级联在一起的多个单级阵列基板行驱动电路中的起始级或结束级的单级阵列基板行驱动电路附近。
其中，所述虚拟测试单元的版图大小与单级阵列基板行驱动电路的版图大小一致。
其中，包括第一虚拟测试单元和第二虚拟测试单元两个虚拟测试单元。
其中，所述第一虚拟测试单元位于级联在一起的多个单级阵列基板行驱动电路中的起始级的单级阵列基板行驱动电路附近，所述第二虚拟测试单元位于级联在一起的多个单级阵列基板行驱动电路中的结束级的单级阵列基板行驱动电路附近。
其中，其包括非晶硅薄膜晶体管。
其中，其包括铟镓锌氧化物薄膜晶体管。
本发明还提供了一种显示面板，所述显示面板的阵列基板行驱动电路区包括如前述任一项所述的阵列基板行驱动电路。
 有益效果
综上，本发明的阵列基板行驱动电路及显示面板提出了一种利于解析的虚拟测试单元摆放方案；在原有的阵列基板行驱动电路设计基础上，通过在阵列基板行驱动电路区摆放虚拟测试单元，利用虚拟测试单元能快速测量相应薄膜晶体管的电性，从而使整个电路利于解析。
 附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1是一个常规四时钟信号阵列基板行驱动电路分布架构示意图；
图2是一种现有单级阵列基板行驱动电路示意图；
图3 是图2所示单级阵列基板行驱动电路的版图；
图4为本发明阵列基板行驱动电路一较佳实施例的虚拟测试单元的版图。
 本发明的实施方式
参见图4，其为本发明阵列基板行驱动电路一较佳实施例的虚拟测试单元（test key）的版图。本发明阵列基板行驱动电路除包括级联在一起的多个单级阵列基板行驱动电路（如图1所示）外，还包括至少一虚拟测试单元，本发明在显示面板的阵列基板行驱动电路区设计了虚拟测试单元，图4所示的版图可以放到图1中的阵列基板行驱动电路起始级和/或结束级附近的空白处，这样的环境可以最大限度反映阵列基板行驱动电路区里的薄膜晶体管环境。
该较佳实施例中的虚拟测试单元具体为根据图2所示的单级阵列基板行驱动电路设计得出，图4所示的虚拟测试单元的版图的大小可以与图3所示的单级阵列基板行驱动电路的版图的大小大体上一致；图4所示的版图中以虚线框形式大体上标识出了四个薄膜晶体管T11、T21、T31及T41。
从图4和图3所示的版图上来看，所述虚拟测试单元中与单级阵列基板行驱动电路中的薄膜晶体管的数量、摆放方式、位置及大小均一致；所述虚拟测试单元中每个薄膜晶体管T11、T21、T31及T41的源极、漏极及栅极三端均分别设有相应的过孔并与相应的过孔连接，所述虚拟测试单元中每个薄膜晶体管T11、T21、T31及T41之间没有连接。
当解析显示面板，判断是否是阵列基板行驱动电路出现问题，需要研究单级阵列基板行驱动电路中某个薄膜晶体管的电性时，只需要在虚拟测试单元中找出其对应的薄膜晶体管即可进行量测。而不用像现有设计，需先将单级阵列基板行驱动电路中该薄膜晶体管与其相连的薄膜晶体管激光切断，再找出其三端连接的过孔，且通常许多薄膜晶体管三端并没有都连接过孔。以图4中的薄膜晶体管T11为例，其源极、漏极及栅极三端均分别设有相应的过孔12、13及14并与相应的过孔12、13及14连接，只需要放入量测机台，即可获得薄膜晶体管T11电性信息。
本发明可以将第一虚拟测试单元设置于级联在一起的多个单级阵列基板行驱动电路中的起始级的单级阵列基板行驱动电路附近，将第二虚拟测试单元设置于级联在一起的多个单级阵列基板行驱动电路中的结束级的单级阵列基板行驱动电路附近。本发明在原有的阵列基板行驱动设计基础上，通过在阵列基板行驱动电路区的起始级及结束级附近各摆放一虚拟测试单元，利用虚拟测试单元能快速测量相应薄膜晶体管的电性，通过对比等方式，能加快解析进度，从而找出问题的根源，从而使整个电路利于解析。
本发明的阵列基板行驱动电路方法适用于所有非晶硅（a-si）及铟镓锌氧化物（IGZO）的阵列基板行驱动电路。
基于本发明的阵列基板行驱动电路，本发明还提供了相应的显示面板，所述显示面板的阵列基板行驱动电路区包括前述的阵列基板行驱动电路。
综上，本发明的阵列基板行驱动电路及显示面板提出了一种利于解析的虚拟测试单元摆放方案；在原有的阵列基板行驱动电路设计基础上，通过在阵列基板行驱动电路区摆放虚拟测试单元，利用虚拟测试单元能快速测量相应薄膜晶体管的电性，从而使整个电路利于解析。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (14)

  1. 一种阵列基板行驱动电路，包括：级联在一起的多个单级阵列基板行驱动电路以及至少一虚拟测试单元，从版图上来看，所述虚拟测试单元中与单级阵列基板行驱动电路中的薄膜晶体管的数量、摆放方式、位置及大小均一致；所述虚拟测试单元中每个薄膜晶体管的源极、漏极及栅极三端均分别设有相应的过孔并与相应的过孔连接，所述虚拟测试单元中每个薄膜晶体管之间没有连接。
  2. 如权利要求1所述的阵列基板行驱动电路，其中，所述虚拟测试单元位于级联在一起的多个单级阵列基板行驱动电路中的起始级或结束级的单级阵列基板行驱动电路附近。
  3. 如权利要求1所述的阵列基板行驱动电路，其中，所述虚拟测试单元的版图大小与单级阵列基板行驱动电路的版图大小一致。
  4. 如权利要求1所述的阵列基板行驱动电路，包括第一虚拟测试单元和第二虚拟测试单元两个虚拟测试单元。
  5. 如权利要求4所述的阵列基板行驱动电路，其中，所述第一虚拟测试单元位于级联在一起的多个单级阵列基板行驱动电路中的起始级的单级阵列基板行驱动电路附近，所述第二虚拟测试单元位于级联在一起的多个单级阵列基板行驱动电路中的结束级的单级阵列基板行驱动电路附近。
  6. 如权利要求1所述的阵列基板行驱动电路，包括非晶硅薄膜晶体管。
  7. 如权利要求1所述的阵列基板行驱动电路，包括铟镓锌氧化物薄膜晶体管。
  8. 一种显示面板，其中，所述显示面板的阵列基板行驱动电路区包括阵列基板行驱动电路；
    所述阵列基板行驱动电路包括：级联在一起的多个单级阵列基板行驱动电路以及至少一虚拟测试单元，从版图上来看，所述虚拟测试单元中与单级阵列基板行驱动电路中的薄膜晶体管的数量、摆放方式、位置及大小均一致；所述虚拟测试单元中每个薄膜晶体管的源极、漏极及栅极三端均分别设有相应的过孔并与相应的过孔连接，所述虚拟测试单元中每个薄膜晶体管之间没有连接。
  9. 如权利要求8所述的显示面板，其中，所述虚拟测试单元位于级联在一起的多个单级阵列基板行驱动电路中的起始级或结束级的单级阵列基板行驱动电路附近。
  10. 如权利要求8所述的显示面板，其中，所述虚拟测试单元的版图大小与单级阵列基板行驱动电路的版图大小一致。
  11. 如权利要求8所述的显示面板，其中，所述阵列基板行驱动电路包括第一虚拟测试单元和第二虚拟测试单元两个虚拟测试单元。
  12. 如权利要求11所述的显示面板，其中，所述第一虚拟测试单元位于级联在一起的多个单级阵列基板行驱动电路中的起始级的单级阵列基板行驱动电路附近，所述第二虚拟测试单元位于级联在一起的多个单级阵列基板行驱动电路中的结束级的单级阵列基板行驱动电路附近。
  13. 如权利要求8所述的显示面板，其中，所述阵列基板行驱动电路包括非晶硅薄膜晶体管。
  14. 如权利要求8所述的显示面板，其中，所述阵列基板行驱动电路包括铟镓锌氧化物薄膜晶体管。
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