WO2020238013A1 - Goa 电路及阵列基板 - Google Patents

Goa 电路及阵列基板 Download PDF

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Publication number
WO2020238013A1
WO2020238013A1 PCT/CN2019/115296 CN2019115296W WO2020238013A1 WO 2020238013 A1 WO2020238013 A1 WO 2020238013A1 CN 2019115296 W CN2019115296 W CN 2019115296W WO 2020238013 A1 WO2020238013 A1 WO 2020238013A1
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Prior art keywords
pull
control
switch
circuit
signal
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PCT/CN2019/115296
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English (en)
French (fr)
Inventor
薛炎
韩佰祥
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/616,504 priority Critical patent/US11176891B1/en
Publication of WO2020238013A1 publication Critical patent/WO2020238013A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof

Definitions

  • the present invention relates to the field of display driving technology, in particular to a GOA circuit and an array substrate with the GOA circuit.
  • the horizontal scan lines of the AMOLED display panel are driven by an external integrated circuit.
  • the external integrated circuit can control the step-by-step turn-on of the row scan lines at all levels.
  • GOA Gate The Driver on Array method can integrate the line scan driving circuit on the display panel substrate, which can reduce the number of external ICs, thereby reducing the production cost of the display panel, and can realize the narrow frame of the display device.
  • IGZO indium gallium zinc oxide
  • IGZO-TFT In the IGZO-TFT manufacturing process, process fluctuations will affect the uniformity of the overall panel Vth (threshold voltage). In addition, IGZO-TFT is subject to interference from external conditions such as voltage, light, and temperature variations, and the device Vth is more likely to shift. Based on the above factors, in order to ensure that GOA can work normally under the premise of uneven or variable Vth, a lot of sub-circuits need to be set in the IGZO-GOA circuit. Therefore, the design of each level of IGZO-GOA is more complicated, and the number of TFTs is large (usually 20 Above), this is not conducive to the narrow bezel of the display panel, which is inconsistent with the original intention of the GOA circuit.
  • IGZO-TFT indium gallium In the zinc oxide process, process fluctuations will affect the uniformity of the overall panel Vth (threshold voltage). In addition, IGZO-TFT is affected by external conditions such as voltage, light, and temperature variations, and the device Vth is prone to deviation .
  • the present invention provides a GOA circuit.
  • the GOA circuit includes a plurality of cascaded GOA units, wherein each GOA unit includes:
  • the pull-up control circuit receives the scan driving signal of the upper-level GOA unit and outputs the turn-on control signal
  • a pull-up circuit that receives the turn-on control signal, and outputs a scan driving signal of the current level according to the turn-on control signal
  • a pull-down circuit which receives a pull-down control signal, and pulls the scan driving signal of the current level to a low level;
  • the output potential signal is opposite to the input potential signal
  • a bootstrap capacitor to maintain and increase the potential of the turn-on control signal
  • part or all of the TFT devices in the pull-up control circuit, the pull-up circuit, the pull-down circuit, and the inverter are double-gate TFT devices, and the bottom gate of the double-gate TFT device An external voltage is connected to control the threshold voltage of the dual-gate TFT device.
  • the inverter includes a first TFT device and a second TFT device, and the input terminal of the first TFT device is connected to a low voltage potential, and the control terminal thereof is connected to the turn-on control signal ;
  • the input terminal and the control terminal of the second TFT device are both connected to a high voltage potential.
  • control terminal of the first TFT device is the input terminal of the inverter, and the first TFT device is connected to the output terminal of the second TFT device and serves as the The output terminal of the inverter, and the output signal is the pull-down control signal.
  • the pull-up control circuit includes a pull-up control switch, and the input end of the pull-up control switch receives the scan driving signal of the upper-level GOA unit, and its control end receives the first A clock signal whose output terminal outputs the turn-on control signal.
  • the pull-up circuit includes a pull-up switch, and the pull-up switch is electrically connected to the pull-up control circuit, then the control terminal of the pull-up switch receives the turn-on control Signal, the input terminal of which receives a second clock signal whose waveform is opposite to the first clock signal, and the output terminal of which outputs the scan driving signal of the current level.
  • the output terminal and the control terminal of the pull-up switch are respectively connected to two ends of the bootstrap capacitor.
  • the pull-down circuit includes a first pull-down switch and a second pull-down switch, and the input terminals of the first pull-down switch and the second pull-down switch are both connected to a low voltage potential;
  • the output terminal of the first pull-down switch is connected to the scan driving signal of the current level, and the output terminal of the second pull-down switch is connected to the turn-on control signal.
  • control terminals of the first pull-down switch and the second pull-down switch are both electrically connected to the inverter, and receive the pull-down control output by the inverter signal.
  • the first TFT device is the dual-gate TFT device
  • the bottom gate of the dual-gate TFT device is connected to an external voltage to control the dual-gate TFT device Threshold voltage.
  • the pull-up control switch and the pull-up switch are both the dual-gate TFT device, and the bottom gate of the dual-gate TFT device is connected to an external voltage to control all The threshold voltage of the double-gate TFT device is described.
  • the first pull-down switch and the second pull-down switch are both the dual-gate TFT device, and the bottom gate of the dual-gate TFT device is connected to an external voltage to Controlling the threshold voltage of the dual-gate TFT device.
  • an array substrate the array substrate includes a GOA circuit
  • the GOA circuit includes a plurality of cascaded GOA units, wherein each GOA unit includes:
  • the pull-up control circuit receives the scan driving signal of the upper-level GOA unit and outputs the turn-on control signal
  • a pull-up circuit that receives the turn-on control signal, and outputs a scan driving signal of the current level according to the turn-on control signal
  • a pull-down circuit which receives a pull-down control signal, and pulls the scan driving signal of the current level to a low level;
  • the output potential signal is opposite to the input potential signal
  • a bootstrap capacitor to maintain and increase the potential of the turn-on control signal
  • part or all of the TFT devices in the pull-up control circuit, the pull-up circuit, the pull-down circuit, and the inverter are double-gate TFT devices, and the bottom gate of the double-gate TFT device An external voltage is connected to control the threshold voltage of the dual-gate TFT device.
  • the inverter includes a first TFT device and a second TFT device, and the input terminal of the first TFT device is connected to a low voltage potential, and the control terminal thereof is connected to the turn-on control signal ;
  • the input terminal and the control terminal of the second TFT device are both connected to a high voltage potential.
  • control terminal of the first TFT device is the input terminal of the inverter, and the first TFT device is connected to the output terminal of the second TFT device and serves as the The output terminal of the inverter, and the output signal is the pull-down control signal.
  • the pull-up control circuit includes a pull-up control switch, and the input end of the pull-up control switch receives the scan driving signal of the upper-level GOA unit, and its control end receives the first A clock signal whose output terminal outputs the turn-on control signal.
  • the pull-up circuit includes a pull-up switch, and the pull-up switch is electrically connected to the pull-up control circuit, then the control terminal of the pull-up switch receives the turn-on control Signal, the input terminal of which receives a second clock signal whose waveform is opposite to the first clock signal, and the output terminal of which outputs the scan driving signal of the current level.
  • the output terminal and the control terminal of the pull-up switch are respectively connected to two ends of the bootstrap capacitor.
  • the pull-down circuit includes a first pull-down switch and a second pull-down switch, and the input terminals of the first pull-down switch and the second pull-down switch are both connected to a low voltage potential;
  • the output terminal of the first pull-down switch is connected to the scan driving signal of the current level, and the output terminal of the second pull-down switch is connected to the turn-on control signal.
  • control terminals of the first pull-down switch and the second pull-down switch are both electrically connected to the inverter, and receive the pull-down control output by the inverter signal.
  • the GOA circuit provided by the present invention adjusts the threshold voltage of the device by setting the dual-gate TFT, realizes the controllability of the threshold voltage, ensures the stability of the GOA circuit, and improves the service life of the array substrate.
  • the The GOA circuit only uses 6 TFTs, which makes the circuit structure simple and satisfies the narrow frame of the panel.
  • FIG. 1 is a schematic diagram of the GOA circuit structure according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a cross-sectional structure of a TFT in a GOA circuit according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a TFT circuit structure in a GOA circuit according to an embodiment of the present invention.
  • Figure 4a is a panel distribution diagram of an embodiment of the present invention.
  • Figure 4b is a schematic diagram of a GOA circuit feedback system according to an embodiment of the present invention.
  • 4c is a graph of the relationship between the bottom gate external voltage of the TFT and the threshold voltage in the GOA circuit of the embodiment of the present invention.
  • Fig. 5 is a signal waveform diagram of a GOA unit according to an embodiment of the present invention.
  • the present invention is directed to the technical problems of the existing GOA circuit that the threshold voltage of the device is easily shifted and the large number of TFTs are not conducive to narrowing the frame of the panel.
  • the present embodiment can solve the defects.
  • the embodiment of the present invention provides a GOA circuit.
  • the GOA circuit includes a plurality of cascaded GOA units.
  • the Nth-stage GOA unit is now taken as an example for detailed description.
  • the GOA unit includes a pull-up control circuit 10, a pull-up circuit 20, a pull-down circuit 30, an inverter 40, and a bootstrap capacitor Cbt, where:
  • the pull-up control circuit 10 receives the scan driving signal G(n-1) of the upper-level GOA unit, and outputs the turn-on control signal Q.
  • the pull-up circuit 20 receives the turn-on control signal Q, and outputs a scan driving signal G(n) of the current level according to the turn-on control signal Q.
  • the pull-down circuit 30 receives the pull-down control signal QB, and pulls the scan driving signal Q of the current level to a low level.
  • the output potential signal of the inverter 40 is opposite to the input potential signal.
  • the bootstrap capacitor Cbt maintains and increases the potential of the turn-on control signal Q.
  • the TFT devices in the pull-up control circuit 10 are double-gate TFT devices, and the bottom gate is connected to an external voltage, To control the threshold voltage of the double-gate TFT device.
  • the pull-up control circuit 10 includes a pull-up control switch T1
  • the pull-up circuit 20 includes a pull-up switch T2
  • the pull-down circuit 30 includes a first pull-down switch T31 and a second pull-down switch.
  • the inverter includes a first TFT device T41 and a second TFT device T42.
  • the pull-up control switch T1, the pull-up switch T2, the first pull-down switch T31, the second pull-down switch T32, and the first TFT device T41 are all the double-gate TFT devices
  • the second TFT device T42 is basically not affected by voltage, so it can be considered that the threshold voltage of the second TFT device T42 does not shift, and there is no need to set the double-gate TFT.
  • the remaining 5 TFTs are all added with bottom
  • the gate realizes a controllable threshold voltage, because different TFTs receive different voltages (that is, the pull-up control switch T1 is affected by the 50% duty cycle gate voltage, and the pull-up switch T2 is affected by the source-drain voltage.
  • the first pull-down switch T31 and the second pull-down switch T32 are similarly affected by the gate voltage, and it can be considered that the offset is the same.
  • the first TFT device T41 is affected by the gate voltage). TFTs add different bottom gate voltages to achieve independent control of the Vth of each TFT.
  • the cross-sectional structure diagram of the dual-gate TFT is shown in FIG. 2 and includes a substrate 201 and various TFT devices, wherein a bottom gate 202 is disposed on the substrate 201, and a bottom gate insulating layer 203 is disposed on the bottom gate 202 And cover the bottom gate 202, the active layer 204 is disposed on the bottom gate insulating layer 203, and then a top gate insulating layer 209 and a top gate 210 are disposed on the active layer 204, and the top gate is insulated
  • the layer 209 is located between the active layer 204 and the top gate 210.
  • a source electrode 206 and a drain electrode 207 are respectively arranged on both sides of the active layer 204, and then the interlayer insulating layer 208 covers the The active layer 204, the top gate insulating layer 209, a part of the source electrode 206 and a part of the drain electrode 207, and a part of the source electrode 206 and the drain electrode 207 are disposed through the interlayer insulating layer 208
  • a flat layer 211 is disposed on the interlayer insulating layer 208, and the flat layer 211 covers the source electrode 206 and the drain electrode 207 to expose the interlayer insulating layer. Part of layer 208.
  • the circuit structure diagram of the double-gate TFT is shown in FIG. 3.
  • the double-gate TFT includes a receiving terminal 301, a control terminal 302, an output terminal 303, and an external voltage terminal 304, wherein the control terminal 302 is the The top gate of the double-gate TFT, and the external voltage terminal is the bottom gate of the double-gate TFT.
  • control terminal in the TFT device is used to control whether the TFT device is turned on, that is, when the control terminal of the TFT device receives a high voltage signal, the TFT device will turn on and turn it on.
  • the signal received at the input end is transmitted from the output end.
  • FIG. 4c it is a graph of the influence of the bottom gate external voltage on the performance of the TFT in the dual-gate TFT provided by the embodiment of the present invention, wherein the x-axis represents the external voltage and the y-axis represents the threshold voltage.
  • the x-axis represents the external voltage
  • the y-axis represents the threshold voltage.
  • the embodiment of the present invention adjusts the bottom gate voltage by setting a feedback system.
  • FIG. 4a it is a distribution diagram of the panel 40 of the present invention.
  • the GOA circuits 402 are distributed on both sides of the panel 40, and the The feedback system 401 is arranged on the outside of the GOA circuits 402 on both sides, the middle area is the wiring area 403, and the COF404 is arranged under the panel 40.
  • FIG. 4b it is a schematic structural diagram of a feedback system provided by an embodiment of the present invention, wherein the feedback system selects some of the GOA units as feedback units, and the layout structure of the selected GOA units is the same as that used for cascade transmission.
  • the layout structure of the GOA unit remains the same, and the signal source of the three-segment connection of the TFT is also the same.
  • the voltage received by the feedback TFT in these feedback GOA units is the same as that of the GOA unit used in the stage transmission.
  • the voltages received by the TFTs also remain the same. Therefore, the electrical properties of the feedback TFTs are consistent with the electrical properties of the TFTs in the GOA in the grade transfer.
  • the electrical properties of the feedback TFT are measured through the feedback system, the initial threshold voltage of the TFT is obtained according to the measurement result, and then the bottom gate voltage of the TFT is adjusted so that the GOA circuit can output a narrow pulse signal And wide pulse signal, interval measurement data, establishment of database, setting program, so that the bottom gate voltage of the TFT can be automatically adjusted with the change of time.
  • the electrical properties of the TFT are detected by the feedback system, and then the feedback system is cut off, which can further narrow the frame.
  • FIG. 1 As an example, the structure and working conditions of the GOA circuit provided by the embodiment of the present invention are described in detail.
  • the pull-up control circuit 10 includes a pull-up control switch T1, and the pull-up control switch T1 is the double-gate TFT device, then the input terminal of the pull-up control switch receives For the scan driving signal of the upper-level GOA unit, the control terminal (that is, the top gate) receives the first clock signal CK1, and its bottom gate is connected to an external voltage V1 to adjust the threshold voltage of the TFT device.
  • the pull-up The output terminal of the control switch T1 outputs a turn-on control signal Q.
  • the pull-up circuit includes a pull-up switch T2, and the pull-up switch T2 is the double-gate TFT device.
  • the input terminal of the pull-up switch T2 receives a second clock signal CK1 that has a waveform opposite to that of the first clock signal CK1.
  • the control terminal (that is, the top gate) is electrically connected to the pull-up control circuit 10, and the control terminal of the pull-up switch T2 receives the turn-on control signal Q output by the pull-up control switch T1, so
  • the output terminal of the pull-up switch T2 outputs the scan driving signal G(n) of the GOA unit of this stage, and at the same time, the bottom gate of the pull-up switch is connected to an external voltage V2 to adjust the TFT device Threshold voltage.
  • Both ends of the bootstrap capacitor Cbt are electrically connected to the control end and the output end of the pull-up switch T2, and the bootstrap capacitor Cbt is used to maintain and increase the potential of the turn-on control signal.
  • the pull-down circuit 30 includes a first pull-down switch T31 and a second pull-down switch T32. Both the first pull-down switch T31 and the second pull-down switch T32 are the double-gate TFT devices. The bottom gates are connected to an external voltage V3 for adjusting the threshold voltage of the TFT device.
  • the input terminal of the first pull-down switch T31 is connected to a low voltage potential VGL, its output terminal is connected to the scan driving signal G(n) of the current level, and its control terminal receives the pull-down output from the inverter 40 Control signal QB.
  • the input terminal of the second pull-down switch T32 is the same as the low voltage potential VGL, its output terminal is connected to the turn-on control signal Q, and its control terminal receives the pull-down control signal output from the inverter 40 QB.
  • the inverter 40 includes a first TFT device T41 and a second TFT device T42.
  • first TFT device T41 is the double-gate TFT device, and its bottom gate is connected to an external voltage V4 for adjusting
  • the threshold voltage of the TFT device, the second TFT device T42 is basically not affected by the voltage, it can be approximated that the threshold voltage of the second TFT device T42 will not shift, therefore, the second TFT device T42 does not need Increase the bottom grid.
  • the input terminal of the first TFT device T41 is connected to the low voltage potential VGL, the control terminal thereof is connected to the turn-on control signal Q, and the control terminal of the first TFT device T41 serves as the input terminal of the inverter 40 101, the input terminal 101 receives the signal as the turn-on control signal Q, the input terminal and the control terminal of the second TFT device T42 are both connected to a high voltage potential VGH, and at the same time, the first TFT device T41 and the control terminal
  • the output terminal of the second TFT device T42 is connected and serves as the output terminal 102 of the inverter 40, and its output signal is the pull-down control signal QB.
  • the turn-on control signal Q received by the input terminal 101 is at a high level, and the pull-down control signal QB output by the output terminal 102 is at a low level; the turn-on control signal Q received by the input terminal 101 If it is a low potential, the pull-down control signal QB output by the output terminal 102 is a high potential.
  • the working principle of the inverter 40 is as follows: the first TFT device T41 and the second TFT device T42 output potential signals for the inverter 40 at the same time.
  • the size of T41 is much larger than the size of the second TFT device T41, so when the first TFT device T41 is turned on, the potential of the pull-down control signal QB is mainly limited by the first TFT device T41.
  • the potential of the pull-down control signal QB is mainly limited by the second TFT device T42.
  • FIG. 5 it is a signal waveform diagram of the GOA unit of the present invention. The following will be analyzed in conjunction with the GOA circuit diagram of FIG. 1.
  • Section S1 At this time, the first clock signal CK1 received by the control terminal of the pull-up control switch T1 is at a high level, so the pull-up control switch T1 is turned on, and its input terminal receives the signal from the upper-level GOA unit
  • the scan driving signal G(n-1), and the scan driving signal G(n-1) is high, so the turn-on control signal Q output from the output terminal of the pull-up control switch T1 is also high
  • the bootstrap capacitor Cbt starts to charge.
  • the control terminal of the pull-up switch T2 receives the turn-on control signal Q, and the turn-on control signal Q is at a high level, the pull-up switch T2 will be turned on. At this time, the input of the pull-up switch T2 If the second clock signal CK2 received by the terminal is at a low level, the scan driving signal G(n) of the current level GOA unit output by the output terminal of the pull-up switch is at a low level.
  • the control terminal of the first TFT device T41 receives the turn-on control signal Q and is at a high level, that is, when the input terminal 101 of the inverter 40 receives a potential signal at a high level, the output terminal of the inverter 40
  • the pull-down control signal QB output by 102 is at a low level.
  • the control ends of the first pull-down switch T31 and the second pull-down switch T32 receive the pull-down control signal QB, so the first pull-down switch T31 and the second pull-down switch T32 are not turned on.
  • the turn-on control signal Q rises to a higher potential under the coupling action of the bootstrap capacitor Cbt.
  • the turn-on control signal Q received by the control terminal of the pull-up switch T2 is at a high level, and the pull-up switch T2 is turned on.
  • the second clock signal CK2 received at its input terminal is at a high level.
  • the scan driving signal G(n) output by the output terminal of the pull-up switch T2 is high.
  • the turn-on control signal Q received by the control terminal of the first TFT device T41 is high, that is, the potential signal received by the input terminal 101 of the inverter 40 is high, then the inverting If the pull-down control signal QB output by the output terminal of the device 40 is at a low level, the first pull-down switch T31 and the second pull-down switch T32 are not turned on.
  • the control terminal of the pull-up switch T2 receives the turn-on control signal Q to be a low level, so the pull-up switch T2 is not turned on.
  • the control terminal of the first TFT device T41 receives the turn-on control signal Q to be a low level, that is, the potential signal received by the input terminal 101 of the inverter 40 is a low level, then the output terminal 102 of the inverter The output pull-down control signal QB is high.
  • the first pull-down switch T31 and the second pull-down switch T32 both receive the pull-down control signal QB as a high level, the first pull-down switch T31 and the second pull-down switch T32 are both turned on And the input terminals of T31 and T32 both receive the low voltage potential VGL, so the output terminal of the first pull-down switch T31 is connected to the scan driving signal G(n) to have a low potential, and the second pull-down switch The output terminal of T32 is connected to the turn-on control signal Q to have a low potential.
  • the GOA circuit provided by the embodiment of the present invention uses double-gate TFTs as circuit switches, which ensures the stability of the GOA circuit and improves the yield of the array substrate.
  • the feedback provided on both sides of the panel The system can be removed after the test is completed, which can further narrow the frame.
  • the GOA circuit provided by the embodiment of the present invention adjusts the threshold voltage of the device by setting the double-gate TFT, realizes the controllability of the threshold voltage, ensures the stability of the GOA circuit, and improves the service life of the array substrate.
  • the invented GOA circuit only uses 6 TFTs, which makes the circuit structure simple and satisfies the narrow frame of the panel.
  • an embodiment of the present invention also provides an array substrate, and the array substrate includes the GOA circuit described in the foregoing embodiment, and its structure and principle are the same as the foregoing GOA circuit, and will not be repeated here.
  • the array substrate can be used in various display panels and display devices, including liquid crystal displays and organic light emitting semiconductor displays.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

本发明公开了一种GOA电路及阵列基板，所述GOA电路采用双栅型TFT作为电路开关，底栅连接外接电压，由所述外接电压来调整所述TFT的阈值电压，以保证所述GOA电路的稳定性，同时所述GOA电路只设置6颗TFT，使得结构简单，实现了面板的窄边框化。

Description

GOA电路及阵列基板 技术领域
本发明涉及显示驱动技术领域，尤其涉及一种GOA电路及具有该GOA电路的阵列基板。
 背景技术
目前AMOLED显示面板水平扫描线的驱动是由外接集成电路来实现的，外接集成电路可以控制各级行扫描线的逐级开启，而采用GOA(Gate Driver on Array)方法，可以将行扫描驱动电路集成在显示面板基板上，能够减少外接IC的数量，从而降低了显示面板的生产成本，并且能够实现显示装置的窄边框化。IGZO（indium gallium zinc oxide，铟镓锌氧化物）具有高的迁移率，和良好的器件稳定性，目前广泛的应用于IGZO-GOA电路中。
在IGZO-TFT制程中，工艺波动会影响整体面板Vth（阈值电压）的均匀性，此外，IGZO-TFT受到电压、光照及温度变异等外界条件干扰，器件Vth较易发生偏移。综合以上因素，为保证GOA在Vth不均匀或变异前提下能够正常工作，IGZO-GOA电路中需要设置很多的子电路，因而每级IGZO-GOA的设计较为复杂，TFT的数量众多（通常20个以上），这不利于显示面板的窄边框化，与GOA电路的设计初衷不符。
 技术问题
在IGZO-TFT（indium gallium zinc oxide，铟镓锌氧化物）制程中，工艺波动会影响整体面板Vth（阈值电压）的均匀性，此外，IGZO-TFT受到电压、光照及温度变异等外界条件干扰，器件Vth容易发生偏移。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种GOA电路，所述GOA电路包括多个级联的GOA单元，其中，每个GOA单元包括：
上拉控制电路，接收上一级GOA单元的扫描驱动信号，并输出开启控制信号；
上拉电路，接收所述开启控制信号，并根据所述开启控制信号输出当前级别的扫描驱动信号；
下拉电路，接收下拉控制信号，并将所述当前级别的扫描驱动信号下拉为低电位；
反相器，其输出电位信号与输入电位信号相反；
自举电容，维持并提高所述开启控制信号的电位；
其中，所述上拉控制电路、所述上拉电路、所述下拉电路以及所述反相器中的部分或全部TFT器件为双栅型TFT器件，且所述双栅型TFT器件的底栅连接外接电压，以控制所述双栅型TFT器件的阈值电压。
在本发明的一种实施例中，所述反相器包括第一TFT器件与第二TFT器件，且所述第一TFT器件的输入端连接低电压电位，其控制端连接所述开启控制信号；
所述第二TFT器件的输入端和控制端均连接高电压电位。
在本发明的一种实施例中，所述第一TFT器件的控制端为所述反相器的输入端，所述第一TFT器件与所述第二TFT器件的输出端相连并作为所述反相器的输出端，且输出信号为所述下拉控制信号。
在本发明的一种实施例中，所述上拉控制电路包括上拉控制开关，且所述上拉控制开关的输入端接收所述上一级GOA单元的扫描驱动信号，其控制端接收第一时钟信号，其输出端输出所述开启控制信号。
在本发明的一种实施例中，所述上拉电路包括上拉开关，且所述上拉开关与所述上拉控制电路电连接，则所述上拉开关的控制端接收所述开启控制信号，其输入端接收与所述第一时钟信号波形相反的第二时钟信号，其输出端输出所述当前级别的扫描驱动信号。
在本发明的一种实施例中，所述上拉开关的输出端以及控制端分别连接所述自举电容的两端。
在本发明的一种实施例中，所述下拉电路包括第一下拉开关与第二下拉开关，且所述第一下拉开关和所述第二下拉开关的输入端均连接低电压电位；
所述第一下拉开关的输出端连接所述当前级别的扫描驱动信号，所述第二下拉开关的输出端连接所述开启控制信号。
在本发明的一种实施例中，所述第一下拉开关和所述第二下拉开关的控制端均与所述反相器电连接，并接收所述反相器输出的所述下拉控制信号。
在本发明的一种实施例中，所述第一TFT器件为所述双栅型TFT器件，且所述双栅型TFT器件的底栅连接外接电压，以控制所述双栅型TFT器件的阈值电压。
在本发明的一种实施例中，所述上拉控制开关以及所述上拉开关均为所述双栅型TFT器件，且所述双栅型TFT器件的底栅连接外接电压，以控制所述双栅型TFT器件的阈值电压。
在本发明的一种实施例中，所述第一下拉开关以及所述第二下拉开关均为所述双栅型TFT器件，且所述双栅型TFT器件的底栅连接外接电压，以控制所述双栅型TFT器件的阈值电压。
根据本发明的上述目的，提供一种阵列基板，所述阵列基板包括GOA电路，且所述GOA电路包括多个级联的GOA单元，其中，每个GOA单元包括：
上拉控制电路，接收上一级GOA单元的扫描驱动信号，并输出开启控制信号；
上拉电路，接收所述开启控制信号，并根据所述开启控制信号输出当前级别的扫描驱动信号；
下拉电路，接收下拉控制信号，并将所述当前级别的扫描驱动信号下拉为低电位；
反相器，其输出电位信号与输入电位信号相反；
自举电容，维持并提高所述开启控制信号的电位；
其中，所述上拉控制电路、所述上拉电路、所述下拉电路以及所述反相器中的部分或全部TFT器件为双栅型TFT器件，且所述双栅型TFT器件的底栅连接外接电压，以控制所述双栅型TFT器件的阈值电压。
在本发明的一种实施例中，所述反相器包括第一TFT器件与第二TFT器件，且所述第一TFT器件的输入端连接低电压电位，其控制端连接所述开启控制信号；
所述第二TFT器件的输入端和控制端均连接高电压电位。
在本发明的一种实施例中，所述第一TFT器件的控制端为所述反相器的输入端，所述第一TFT器件与所述第二TFT器件的输出端相连并作为所述反相器的输出端，且输出信号为所述下拉控制信号。
在本发明的一种实施例中，所述上拉控制电路包括上拉控制开关，且所述上拉控制开关的输入端接收所述上一级GOA单元的扫描驱动信号，其控制端接收第一时钟信号，其输出端输出所述开启控制信号。
在本发明的一种实施例中，所述上拉电路包括上拉开关，且所述上拉开关与所述上拉控制电路电连接，则所述上拉开关的控制端接收所述开启控制信号，其输入端接收与所述第一时钟信号波形相反的第二时钟信号，其输出端输出所述当前级别的扫描驱动信号。
在本发明的一种实施例中，所述上拉开关的输出端以及控制端分别连接所述自举电容的两端。
在本发明的一种实施例中，所述下拉电路包括第一下拉开关与第二下拉开关，且所述第一下拉开关和所述第二下拉开关的输入端均连接低电压电位；
所述第一下拉开关的输出端连接所述当前级别的扫描驱动信号，所述第二下拉开关的输出端连接所述开启控制信号。
在本发明的一种实施例中，所述第一下拉开关和所述第二下拉开关的控制端均与所述反相器电连接，并接收所述反相器输出的所述下拉控制信号。
 有益效果
本发明所提供的GOA电路通过设置双栅型TFT来调整器件的阈值电压，实现了阈值电压的可控性，保证了GOA电路的稳定性，提高了阵列基板的使用寿命，同时，本发明的GOA电路只采用6颗TFT，使得电路结构简单，满足了面板的窄边框化。
 附图说明
图1为本发明实施例的GOA电路结构示意图。
图2为本发明实施例的GOA电路中TFT剖面结构示意图。
图3为本发明实施例的GOA电路中TFT电路结构示意图。
图4a为本发明实施例的面板分布图；
图4b为本发明实施例的GOA电路反馈***示意图；
图4c为本发明实施例的GOA电路中TFT的底栅外接电压与阈值电压关系曲线图。
图5为本发明实施例的GOA单元的信号波形图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对现有的GOA电路，由于器件阈值电压易偏移并TFT数量众多不利于面板窄边框化的技术问题，本实施例能够解决该缺陷。
本发明实施例提供一种GOA电路，所述GOA电路包括多个级联的GOA单元，现以第N级GOA单元为例，进行详述。
如图1所示，所述GOA单元包括上拉控制电路10、上拉电路20、下拉电路30、反相器40以及自举电容Cbt，其中：
所述上拉控制电路10，接收上一级GOA单元的扫描驱动信号G(n-1)，并输出开启控制信号Q。
所述上拉电路20，接收所述开启控制信号Q，并根据所述开启控制信号Q输出当前级别的扫描驱动信号G(n)。
所述下拉电路30，接收下拉控制信号QB，并将所述当前级别的扫描驱动信号Q下拉为低电位。
所述反相器40，其输出电位信号与输入电位信号相反。
所述自举电容Cbt，维持并提高所述开启控制信号Q的电位。
其中，所述上拉控制电路10、所述上拉电路20、所述下拉电路30以及所述反相器40中的部分或全部TFT器件为双栅型TFT器件，且底栅连接外接电压，以控制所述双栅型TFT器件的阈值电压。
在本发明实施例中，所述上拉控制电路10包括上拉控制开关T1，所述上拉电路20包括上拉开关T2，所述下拉电路30包括第一下拉开关T31与第二下拉开关T32，所述反相器包括第一TFT器件T41与第二TFT器件T42。
其中，所述上拉控制开关T1、所述上拉开关T2、所述第一下拉开关T31、所述第二下拉开关T32以及所述第一TFT器件T41均为所述双栅型TFT器件，且所述第二TFT器件T42基本不受电压影响，所以可认为所述第二TFT器件T42的阈值电压不发生偏移，无需设置为所述双栅型TFT，其余5颗TFT均添加底栅实现阈值电压可控，由于不同TFT受到的电压不同（即所述上拉控制开关T1受50%占空比的栅极电压的作用，所述上拉开关T2受源漏极电压的作用，所述第一下拉开关T31以及所述第二下拉开关T32受栅极电压的作用相似，可认为偏移量相同，所述第一TFT器件T41受到栅极电压的作用），该设计针对不同TFT添加不同的底栅电压，实现每颗TFT的Vth的独立控制。
所述双栅型TFT剖面结构图如图2所示，包括基板201以及各种TFT器件，其中，底栅202设置于所述基板201上，底栅绝缘层203设置于所述底栅202上并包覆所述底栅202，有源层204设置于所述底栅绝缘层203上，然后在所述有源层204上设置顶栅绝缘层209以及顶栅210，且所述顶栅绝缘层209位于所述有源层204与所述顶栅210之间，同时，在所述有源层204两侧分别设置源极206以及漏极207，再以层间绝缘层208包覆所述有源层204、所述顶栅绝缘层209、部分所述源极206以及部分所述漏极207，所述源极206和所述漏极207的一部分穿过所述层间绝缘层208设置于所述层间绝缘层208之上，且在所述层间绝缘层208上设置平坦层211，所述平坦层211包覆所述源极206和所述漏极207露出所述层间绝缘层208的部分。
所述双栅型TFT的电路结构示意图如图3所示，所述双栅型TFT包括接收端301，控制端302，输出端303以及外接电压端304，其中，所述控制端302为所述双栅型TFT的顶栅，所述外接电压端为所述双栅型TFT的底栅。
需要注意的是，所述TFT器件中的控制端用以控制所述TFT器件是否导通，即当所述TFT器件的控制端接收到高电压信号时，所述TFT器件将导通，将其输入端所接收到的信号从输出端传出。
另外，如图4c所示，为本发明实施例提供的所述双栅型TFT中底栅外接电压对所述TFT的性能影响曲线图，其中，x轴表示外接电压，y轴表示阈值电压，如图所示，当所述底栅电压接正压时，则所述TFT的阈值电压负偏，当所述底栅电压接负时，所述TFT的阈值电压正偏，依此规律通过控制所述底栅电压来调节所述TFT的阈值电压保持稳定。
因此，本发明实施例通过设置反馈***来调节所述底栅电压，如图4a所示，为本发明面板40的分布图，其中，GOA电路402分布于所述面板40两侧，且所述反馈***401设置于两侧所述GOA电路402的外侧，中间区域为走线区403，所述面板40下方设置有COF404。
如图4b所示，为本发明实施例提供的反馈***的结构示意图，其中，所述反馈***选取部分所述GOA单元作为反馈单元，所述选中的GOA单元的布局结构与用于级传的所述GOA单元的布局结构保持一致，且所述TFT的三段连接的信号源也保持一致，如此，这些所述反馈GOA单元中反馈TFT受到的电压与级传用的所述GOA单元中所述TFT所受电压也保持一致，所以，这些所述反馈TFT的电性与级传中所述GOA中所述TFT电性一致。
因此，通过所述反馈***来测量所述反馈TFT的电性，根据量测结果得到所述TFT的初始阈值电压，然后调节所述TFT的底栅电压，使得所述GOA电路能够输出窄脉冲信号及宽脉冲信号，隔期测量数据，建立数据库，设定程序，使所述TFT的底栅电压能够随着时间的改变自动调整。
利用所述反馈***探测得到所述TFT的电性，随后将该反馈***切除，能够进一步收窄边框。
接下来，以图1为例，详述本发明实施例提供的所述GOA电路的结构以及工作情况。
如图1所示，所述上拉控制电路10中，包括上拉控制开关T1，且所述上拉控制开关T1为所述双栅型TFT器件，则所述上拉控制开关的输入端接收上一级GOA单元的扫描驱动信号，控制端（即顶栅）接收第一时钟信号CK1，其底栅连接一外接电压V1，用以调节所述TFT器件的阈值电压，另外，所述上拉控制开关T1的输出端输出开启控制信号Q。
所述上拉电路包括上拉开关T2，且所述上拉开关T2为所述双栅型TFT器件，所述上拉开关T2的输入端接收与所述第一时钟信号CK1波形相反的第二时钟信号CK2，控制端（即顶栅）与所述上拉控制电路10电连接，则所述上拉开关T2的控制端接收所述上拉控制开关T1输出的所述开启控制信号Q，所述上拉开关T2的输出端输出本级所述GOA单元的所述扫描驱动信号G（n），同时，所述上拉开关的底栅连接一外接电压V2，用以调节所述TFT器件的阈值电压。
所述自举电容Cbt的两端分别与所述上拉开关T2的控制端以及输出端电连接，所述自举电容Cbt用以维持并提高所述开启控制信号的电位。
所述下拉电路30包括第一下拉开关T31以及第二下拉开关T32，所述第一下拉开关T31以及所述第二下拉开关T32均为所述双栅型TFT器件，则T31和T32的底栅均连接一外接电压V3，用以调节所述TFT器件的阈值电压。
其中，所述第一下拉开关T31的输入端连接一低压电位VGL，其输出端连接所述当前级别的扫描驱动信号G（n），其控制端接收来自所述反相器40输出的下拉控制信号QB，另外，所述第二下拉开关T32的输入端同样所述低压电位VGL，其输出端连接所述开启控制信号Q，其控制端接收来自所述反相器40输出的下拉控制信号QB。
所述反相器40包括第一TFT器件T41以及第二TFT器件T42，其中，仅所述第一TFT器件T41为所述双栅型TFT器件，其底栅连接一外接电压V4，用以调节所述TFT器件的阈值电压，所述第二TFT器件T42基本不受电压影响，可近似认为所述第二TFT器件T42的阈值电压不会发生偏移，因此，所述第二TFT器件T42无需增加底栅。
所述第一TFT器件T41的输入端连接所述低电压电位VGL，其控制端连接所述开启控制信号Q，且所述第一TFT器件T41的控制端作为所述反相器40的输入端101，则所述输入端101接收信号为所述开启控制信号Q，所述第二TFT器件T42输入端和控制端均是连接一高电压电位VGH，同时，所述第一TFT器件T41以及所述第二TFT器件T42的输出端相连接，并作为所述反相器40的输出端102，其输出信号为所述下拉控制信号QB。
即，所述输入端101接收的所述开启控制信号Q为高电位，则所述输出端102输出的所述下拉控制信号QB为低电位；所述输入端101接收的所述开启控制信号Q为低电位，则所述输出端102输出的所述下拉控制信号QB为高电位。
具体的，所述反相器40的工作原理如下：所述第一TFT器件T41和所述第二TFT器件T42同时为所述反相器40输出电位信号，其中，由于所述第一TFT器件T41的尺寸远大于所述第二TFT器件T41的尺寸，所以当所述第一TFT器件T41导通时，所述下拉控制信号QB的电位主要受所述第一TFT器件T41限制，当所述第一TFT器件T41未导通时，所述下拉控制信号QB的电位主要受所述第二TFT器件T42限制。
如图5所示，为本发明中GOA单元的信号波形图，下面将配合图1的GOA电路图进行分析。
S1段：此时所述上拉控制开关T1的控制端接收的所述第一时钟信号CK1为高电位，所以所述上拉控制开关T1导通，其输入端接收来自上一级GOA单元的所述扫描驱动信号G（n-1），且所述扫描驱动信号G（n-1）为高电位，所以所述上拉控制开关T1的输出端输出的所述开启控制信号Q也为高电位，此时，所述自举电容Cbt开始进行充电。
所述上拉开关T2的控制端接收所述开启控制信号Q，且所述开启控制信号Q为高电位，则所述上拉开关T2将导通，此时，所述上拉开关T2的输入端接收的所述第二时钟信号CK2为低电位，则所述上拉开关输出端输出的当前级别GOA单元的所述扫描驱动信号G（n）为低电位。
所述第一TFT器件T41的控制端接收所述开启控制信号Q，为高电位，即所述反相器40的输入端101接收电位信号为高电位，则所述反相器40的输出端102输出的所述下拉控制信号QB为低电位。
所述第一下拉开关T31以及所述第二下拉开关T32的控制端接收所述下拉控制信号QB，因此所述第一下拉开关T31与所述第二下拉开关T32均未导通。
S2：此时所述上拉控制开关T1的控制端接收到的所述第一时钟信号CK1为低电位，所以所述上拉控制开关T1未导通。
所述自举电容Cbt已完成充电，则所述开启控制信号Q在所述自举电容Cbt的耦合作用下升至更高电位。
则所述上拉开关T2的控制端接收的所述开启控制信号Q为高电位，所述上拉开关T2导通，此时其输入端接收的所述第二时钟信号CK2为高电位，因此，所述上拉开关T2的输出端输出的所述扫描驱动信号G（n）为高电位。
且此时所述第一TFT器件T41的控制端所接收的所述开启控制信号Q为高电位，即所述反相器40的输入端101接收的电位信号为高电位，则所述反相器40的输出端输出的所述下拉控制信号QB为低电位，则所述第一下拉开关T31以及所述第二下拉开关T32均未导通。
S3：此时，所述上拉控制开关T1的控制端接收到的所述第一时钟信号CK1为高电位，则所述上拉控制开关T1导通，且所述上一级的GOA单元的所述扫描驱动信号G（n-1）为低电位，因此，所述上拉控制开关T1所输出的所述开启控制信号Q为低电位。
所述上拉开关T2的控制端接收所述开启控制信号Q为低电位，所以所述上拉开关T2未导通。
所述第一TFT器件T41的控制端接收所述开启控制信号Q为低电位，即所述反相器40的输入端101接收的电位信号为低电位，则所述反相器的输出端102输出的所述下拉控制信号QB为高电位。
所述第一下拉开关T31以及所述第二下拉开关T32的控制端均接收所述下拉控制信号QB为高电位，则所述第一下拉开关T31以及所述第二下拉开关T32均导通，且T31和T32的输入端均接收所述低电压电位VGL，所以所述第一下拉开关T31的输出端连接所述扫描驱动信号G（n）为低电位，所述第二下拉开关T32的输出端连接所述开启控制信号Q为低电位。
综上所述，本发明实施例所提供的GOA电路采用双栅型TFT作为电路开关，保证了GOA电路的稳定性，提高了阵列基板的良率，同时，设置于所述面板两侧的反馈***在测试完毕之后可拆除，能够进一步的收窄边框。
本发明实施例所提供的GOA电路通过设置双栅型TFT来调整器件的阈值电压，实现了阈值电压的可控性，保证了GOA电路的稳定性，提高了阵列基板的使用寿命，同时，本发明的GOA电路只采用6颗TFT，使得电路结构简单，满足了面板的窄边框化。
另外，本发明实施例还提供一种阵列基板，且所述阵列基板包括上述实施例所述的GOA电路，其结构以及原理均与上述GOA电路相同，在此不再赘述。
所述阵列基板可用于各种显示面板及显示装置中，其中包括液晶显示器以及有机发光半导体显示器。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (19)

  1. 一种GOA电路，所述GOA电路包括多个级联的GOA单元，其中，每个GOA单元包括：
    上拉控制电路，接收上一级GOA单元的扫描驱动信号，并输出开启控制信号；
    上拉电路，接收所述开启控制信号，并根据所述开启控制信号输出当前级别的扫描驱动信号；
    下拉电路，接收下拉控制信号，并将所述当前级别的扫描驱动信号下拉为低电位；
    反相器，其输出电位信号与输入电位信号相反；
    自举电容，维持并提高所述开启控制信号的电位；
    其中，所述上拉控制电路、所述上拉电路、所述下拉电路以及所述反相器中的部分或全部TFT器件为双栅型TFT器件，且所述双栅型TFT器件的底栅连接外接电压，以控制所述双栅型TFT器件的阈值电压。
  2. 根据权利要求1所述的GOA电路，其中，所述反相器包括第一TFT器件与第二TFT器件，且所述第一TFT器件的输入端连接低电压电位，其控制端连接所述开启控制信号；
    所述第二TFT器件的输入端和控制端均连接高电压电位。
  3. 根据权利要求2所述的GOA电路，其中，所述第一TFT器件的控制端为所述反相器的输入端，所述第一TFT器件与所述第二TFT器件的输出端相连并作为所述反相器的输出端，且输出信号为所述下拉控制信号。
  4. 根据权利要求1所述的GOA电路，其中，所述上拉控制电路包括上拉控制开关，且所述上拉控制开关的输入端接收所述上一级GOA单元的扫描驱动信号，其控制端接收第一时钟信号，其输出端输出所述开启控制信号。
  5. 根据权利要求4所述的GOA电路，其中，所述上拉电路包括上拉开关，且所述上拉开关与所述上拉控制电路电连接，则所述上拉开关的控制端接收所述开启控制信号，其输入端接收与所述第一时钟信号波形相反的第二时钟信号，其输出端输出所述当前级别的扫描驱动信号。
  6. 根据权利要求5所述的GOA电路，其中，所述上拉开关的输出端以及控制端分别连接所述自举电容的两端。
  7. 根据权利要求1所述的GOA电路，其中，所述下拉电路包括第一下拉开关与第二下拉开关，且所述第一下拉开关和所述第二下拉开关的输入端均连接低电压电位；
    所述第一下拉开关的输出端连接所述当前级别的扫描驱动信号，所述第二下拉开关的输出端连接所述开启控制信号。
  8. 根据权利要求7所述的GOA电路，其中，所述第一下拉开关和所述第二下拉开关的控制端均与所述反相器电连接，并接收所述反相器输出的所述下拉控制信号。
  9. 根据权利要求2所述的GOA电路，其中，所述第一TFT器件为所述双栅型TFT器件，且所述双栅型TFT器件的底栅连接外接电压，以控制所述双栅型TFT器件的阈值电压。
  10. 根据权利要求5所述的GOA电路，其中，所述上拉控制开关以及所述上拉开关均为所述双栅型TFT器件，且所述双栅型TFT器件的底栅连接外接电压，以控制所述双栅型TFT器件的阈值电压。
  11. 根据权利要求7所述的GOA电路，其中，所述第一下拉开关以及所述第二下拉开关均为所述双栅型TFT器件，且所述双栅型TFT器件的底栅连接外接电压，以控制所述双栅型TFT器件的阈值电压。
  12. 一种阵列基板，所述阵列基板包括GOA电路，且所述GOA电路包括多个级联的GOA单元，其中，每个GOA单元包括：
    上拉控制电路，接收上一级GOA单元的扫描驱动信号，并输出开启控制信号；
    上拉电路，接收所述开启控制信号，并根据所述开启控制信号输出当前级别的扫描驱动信号；
    下拉电路，接收下拉控制信号，并将所述当前级别的扫描驱动信号下拉为低电位；
    反相器，其输出电位信号与输入电位信号相反；
    自举电容，维持并提高所述开启控制信号的电位；
    其中，所述上拉控制电路、所述上拉电路、所述下拉电路以及所述反相器中的部分或全部TFT器件为双栅型TFT器件，且所述双栅型TFT器件的底栅连接外接电压，以控制所述双栅型TFT器件的阈值电压。
  13. 根据权利要求12所述的阵列基板，其中，所述反相器包括第一TFT器件与第二TFT器件，且所述第一TFT器件的输入端连接低电压电位，其控制端连接所述开启控制信号；
    所述第二TFT器件的输入端和控制端均连接高电压电位。
  14. 根据权利要求13所述的阵列基板，其中，所述第一TFT器件的控制端为所述反相器的输入端，所述第一TFT器件与所述第二TFT器件的输出端相连并作为所述反相器的输出端，且输出信号为所述下拉控制信号。
  15. 根据权利要求12所述的阵列基板，其中，所述上拉控制电路包括上拉控制开关，且所述上拉控制开关的输入端接收所述上一级GOA单元的扫描驱动信号，其控制端接收第一时钟信号，其输出端输出所述开启控制信号。
  16. 根据权利要求15所述的阵列基板，其中，所述上拉电路包括上拉开关，且所述上拉开关与所述上拉控制电路电连接，则所述上拉开关的控制端接收所述开启控制信号，其输入端接收与所述第一时钟信号波形相反的第二时钟信号，其输出端输出所述当前级别的扫描驱动信号。
  17. 根据权利要求16所述的阵列基板，其中，所述上拉开关的输出端以及控制端分别连接所述自举电容的两端。
  18. 根据权利要求12所述的阵列基板，其中，所述下拉电路包括第一下拉开关与第二下拉开关，且所述第一下拉开关和所述第二下拉开关的输入端均连接低电压电位；
    所述第一下拉开关的输出端连接所述当前级别的扫描驱动信号，所述第二下拉开关的输出端连接所述开启控制信号。
  19. 根据权利要求18所述的阵列基板，其中，所述第一下拉开关和所述第二下拉开关的控制端均与所述反相器电连接，并接收所述反相器输出的所述下拉控制信号。
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