WO2020220531A1 - Circuit d'attaque de rangée de substrat à matrice et panneau d'affichage - Google Patents

Circuit d'attaque de rangée de substrat à matrice et panneau d'affichage Download PDF

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Publication number
WO2020220531A1
WO2020220531A1 PCT/CN2019/102478 CN2019102478W WO2020220531A1 WO 2020220531 A1 WO2020220531 A1 WO 2020220531A1 CN 2019102478 W CN2019102478 W CN 2019102478W WO 2020220531 A1 WO2020220531 A1 WO 2020220531A1
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WO
WIPO (PCT)
Prior art keywords
array substrate
substrate row
virtual test
test unit
stage
Prior art date
Application number
PCT/CN2019/102478
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English (en)
Chinese (zh)
Inventor
奚苏萍
王添鸿
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Publication of WO2020220531A1 publication Critical patent/WO2020220531A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes

Definitions

  • the present invention relates to the field of display technology, in particular to an array substrate row driving circuit and a display panel.
  • GOA Gate Driver On Array
  • Figure 1 is a schematic diagram of a conventional four-clock signal array substrate row drive circuit distribution architecture.
  • the area where the array substrate row drive signal is located can be called the busline area
  • the area where the array substrate row drive circuit is located can be called the array substrate row drive circuit area, the bus area and the array substrate row drive circuit area
  • the combined area can be called the row driving area of the array substrate.
  • the bus area is mainly arranged with multiple signal lines for transmitting various signals required by the operation of the array substrate row driving circuit. For example, as shown in Figure 1, each signal line transmits four clock signals CK1, CK2, CK3, and CK4. , Low-frequency clock signals LC1, LC2, start signal STV2, and power supply low voltage VSS.
  • the array substrate row drive circuit area is mainly arranged with various levels of array substrate row drive circuits step by step.
  • the array substrate row drive circuits of each level output corresponding scanning signals G(1), G(2)...G(n) to Scan lines at all levels of the effective display area of the panel.
  • Fig. 2 is a schematic diagram of an existing single-stage array substrate row driving circuit, showing a single-stage array substrate row driving circuit composed of four thin film transistors T11, T21, T31, and T41 for outputting a scanning signal G(n) The scan line of the corresponding level to the effective display area.
  • a scanning signal G(n) The scan line of the corresponding level to the effective display area.
  • FIG 3 is a layout diagram corresponding to the row drive circuit of the single-stage array substrate shown in Figure 2, in which the circuit functions/structures corresponding to each part of the publication diagram are generally identified in the form of a dashed frame.
  • the layout mainly identifies four Thin film transistors T11, T21, T31 and T41, clock signal CK(n) input terminal, power supply low voltage VSS input terminal, scan signal output terminal G(n), and bootstrap capacitor Cb (not shown in Figure 2).
  • the other thin film transistors connected to the thin film transistor need to be cut off by laser, and then the three terminals of the gate, source and drain of the thin film transistor are found.
  • the measuring machine tests the thin film transistor through the via hole to obtain the electrical information of the thin film transistor.
  • the three terminals of many thin film transistors are not connected with vias.
  • the three terminals of the thin film transistor T11 are not all connected with vias, and only one end is connected to the corresponding via 10, which causes The electrical properties of the thin film transistor T11 cannot be accurately obtained at the current stage.
  • the object of the present invention is to provide an array substrate row driving circuit and a display panel, which are beneficial to measuring the electrical properties of the thin film transistors in the array substrate row driving circuit.
  • the present invention provides an array substrate row drive circuit including: a plurality of single-stage array substrate row drive circuits and at least one virtual test unit that are cascaded together. From the perspective of the layout, the virtual test unit The number, placement, position, and size of thin film transistors in the single-stage array substrate row drive circuit are consistent; the source, drain, and gate of each thin film transistor in the virtual test unit are respectively provided with The corresponding via hole is connected to the corresponding via hole, and there is no connection between each thin film transistor in the virtual test unit.
  • the virtual test unit is located near the single-stage array substrate row driving circuit of the starting stage or the ending stage of the multiple single-stage array substrate row driving circuits cascaded together.
  • the layout size of the virtual test unit is consistent with the layout size of the row driving circuit of the single-stage array substrate.
  • it includes two virtual test units, a first virtual test unit and a second virtual test unit.
  • the first virtual test unit is located near the single-stage array substrate row drive circuit of the initial stage among the plurality of single-stage array substrate row drive circuits cascaded together, and the second virtual test unit is located in the cascade The single-stage array substrate row drive circuit of the final stage among the plurality of single-stage array substrate row drive circuits together.
  • amorphous silicon thin film transistors includes amorphous silicon thin film transistors.
  • indium gallium zinc oxide thin film transistors it includes indium gallium zinc oxide thin film transistors.
  • the present invention also provides a display panel, the array substrate row driving circuit area of the display panel includes the array substrate row driving circuit as described in any one of the foregoing.
  • the array substrate row drive circuit and display panel of the present invention propose a virtual test unit placement solution that is conducive to analysis; on the basis of the original array substrate row drive circuit design, by placing it in the array substrate row drive circuit area
  • the virtual test unit can quickly measure the electrical properties of the corresponding thin film transistor by using the virtual test unit, so that the entire circuit is easy to analyze.
  • Figure 1 is a schematic diagram of a conventional four-clock signal array substrate row drive circuit distribution architecture
  • FIG. 2 is a schematic diagram of a row driving circuit of an existing single-stage array substrate
  • FIG. 3 is the layout of the row driving circuit of the single-stage array substrate shown in FIG. 2;
  • FIG. 4 is a layout diagram of a virtual test unit of a preferred embodiment of the array substrate row driving circuit of the present invention.
  • FIG. 4 is a layout of a virtual test unit (test key) of a preferred embodiment of the array substrate row driving circuit of the present invention.
  • the array substrate row drive circuit of the present invention includes a plurality of single-stage array substrate row drive circuits connected together in cascade (as shown in FIG. 1), and also includes at least one virtual test unit.
  • the present invention drives the array substrate row of the display panel.
  • a virtual test unit is designed in the circuit area.
  • the layout shown in Figure 4 can be placed in the blank space near the start and/or end stages of the array substrate row drive circuit in Figure 1, so that the environment can reflect the array substrate row drive to the maximum. Thin film transistor environment in the circuit area.
  • the virtual test unit in this preferred embodiment is specifically designed based on the single-stage array substrate row drive circuit shown in FIG. 2.
  • the layout of the virtual test unit shown in FIG. 4 can be as large as that of the single-stage array substrate shown in FIG.
  • the size of the layout of the array substrate row driving circuit is generally the same; the layout shown in FIG. 4 generally identifies four thin film transistors T11, T21, T31, and T41 in the form of a dashed frame.
  • each thin film transistor T11, T21, T31, and T41 are respectively provided with corresponding via holes and connected to the corresponding via holes.
  • each thin film transistor T11 There is no connection between T21, T31 and T41.
  • the thin film transistor connected to the thin film transistor in the row driver circuit of the single-stage array substrate needs to be laser cut, and then the three-terminal connection via hole is found.
  • many thin film transistors do not have all three terminals. Connect vias.
  • the source, drain, and gate terminals are provided with corresponding vias 12, 13, and 14 respectively, and are connected to the corresponding vias 12, 13, and 14. Put it into the measuring machine to get the electrical information of the thin film transistor T11.
  • the first virtual test unit can be arranged near the single-stage array substrate row drive circuit of the initial stage among the multiple single-stage array substrate row drive circuits connected together, and the second virtual test unit can be arranged in the cascade.
  • the single-stage array substrate row driving circuit of the final stage among the multiple single-stage array substrate row driving circuits together is near.
  • the present invention is based on the original array substrate row drive design, by placing a virtual test unit near the start level and the end level of the array substrate row drive circuit area, and the virtual test unit can quickly measure the electrical properties of the corresponding thin film transistor , Through comparison and other methods, the analysis progress can be accelerated, so as to find the root cause of the problem, so that the entire circuit is conducive to analysis.
  • the array substrate row drive circuit method of the present invention is applicable to all array substrate row drive circuits of amorphous silicon (a-si) and indium gallium zinc oxide (IGZO).
  • a-si amorphous silicon
  • IGZO indium gallium zinc oxide
  • the present invention also provides a corresponding display panel.
  • the array substrate row drive circuit area of the display panel includes the aforementioned array substrate row drive circuit.
  • the array substrate row drive circuit and display panel of the present invention propose a virtual test unit placement solution that is conducive to analysis; on the basis of the original array substrate row drive circuit design, by placing it in the array substrate row drive circuit area
  • the virtual test unit can quickly measure the electrical properties of the corresponding thin film transistor by using the virtual test unit, so that the entire circuit is easy to analyze.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un circuit d'attaque de rangée de substrat à matrice et un panneau d'affichage, le circuit d'attaque de rangée de substrat à matrice comportant: une pluralité de circuits d'attaque de rangée de substrat à matrice mono-étage qui sont placés en cascade ensemble et au moins une unité de test virtuel. Dans une vue d'implantation, le nombre, la méthode de placement, la position et la taille de transistors à couches minces dans les unités de test virtuel sont cohérents avec ceux de transistors à couches minces dans les circuits d'attaque de rangée de substrat à matrice mono-étage. La source, le drain et la grille de chaque transistor à couches minces dans les unités de test virtuel sont respectivement munis d'un trou d'interconnexion correspondant et sont reliés au trou d'interconnexion correspondant, et aucun des transistors à couches minces dans les unités de test virtuel n'est relié aux autres. Dans le circuit d'attaque de rangée de substrat à matrice et le panneau d'affichage, les unités de test virtuel sont placées dans une zone de circuits d'attaque de rangée de substrat à matrice, ce qui permet de mesurer rapidement les propriétés électriques des transistors à couches minces correspondants en utilisant les unités de test virtuel, facilitant ainsi l'analyse du circuit dans son ensemble.
PCT/CN2019/102478 2019-04-30 2019-08-26 Circuit d'attaque de rangée de substrat à matrice et panneau d'affichage WO2020220531A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910364398.X 2019-04-30
CN201910364398.XA CN109903712A (zh) 2019-04-30 2019-04-30 阵列基板行驱动电路及显示面板

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WO2020220531A1 true WO2020220531A1 (fr) 2020-11-05

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CN109903712A (zh) * 2019-04-30 2019-06-18 深圳市华星光电半导体显示技术有限公司 阵列基板行驱动电路及显示面板
CN111025632B (zh) * 2019-12-27 2022-05-10 宜昌南玻显示器件有限公司 组合显示***的简易设计方法
CN111369929B (zh) * 2020-04-10 2021-07-23 深圳市华星光电半导体显示技术有限公司 Goa电路及显示面板
CN115763469A (zh) * 2021-09-01 2023-03-07 长鑫存储技术有限公司 一种驱动电路的版图、半导体结构及半导体存储器

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US20100315401A1 (en) * 2009-06-15 2010-12-16 Au Optronics Corp. Driver Circuit Structure and Method for Repairing the Same
CN103730384A (zh) * 2013-12-13 2014-04-16 深圳市华星光电技术有限公司 一种tft电性量测方法及装置
CN105632959A (zh) * 2016-01-05 2016-06-01 京东方科技集团股份有限公司 一种阵列基板及其制备方法和显示装置
CN108922491A (zh) * 2018-09-07 2018-11-30 惠科股份有限公司 显示面板、显示装置及驱动方法
CN109166507A (zh) * 2018-11-01 2019-01-08 京东方科技集团股份有限公司 测试元件组、电学性能测试方法、阵列基板、显示装置
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