WO2016192139A1 - 基于氧化物半导体薄膜晶体管的goa电路 - Google Patents

基于氧化物半导体薄膜晶体管的goa电路 Download PDF

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Publication number
WO2016192139A1
WO2016192139A1 PCT/CN2015/082007 CN2015082007W WO2016192139A1 WO 2016192139 A1 WO2016192139 A1 WO 2016192139A1 CN 2015082007 W CN2015082007 W CN 2015082007W WO 2016192139 A1 WO2016192139 A1 WO 2016192139A1
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Prior art keywords
thin film
film transistor
electrically connected
node
gate
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PCT/CN2015/082007
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English (en)
French (fr)
Inventor
戴超
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深圳市华星光电技术有限公司
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Priority to JP2017544641A priority Critical patent/JP6518335B2/ja
Priority to US14/771,501 priority patent/US9858880B2/en
Priority to KR1020177013214A priority patent/KR101933332B1/ko
Priority to GB1706062.5A priority patent/GB2546044B/en
Publication of WO2016192139A1 publication Critical patent/WO2016192139A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0417—Special arrangements specific to the use of low carrier mobility technology
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers

Definitions

  • the present invention relates to the field of liquid crystal display driving, and more particularly to a GOA circuit based on an oxide semiconductor thin film transistor.
  • LCD Liquid crystal display
  • PDAs personal digital assistants
  • digital cameras computer screens or laptop screens, etc.
  • liquid crystal displays which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to fill liquid crystal molecules between a Thin Film Transistor Array Substrate (TFT Array Substrate) and a Color Filter (CF), and apply driving on the two substrates.
  • TFT Array Substrate Thin Film Transistor Array Substrate
  • CF Color Filter
  • each pixel is electrically connected to a thin film transistor (TFT), a gate of a thin film transistor is connected to a horizontal scanning line, and a drain is connected to a vertical data line, and a source (Source) ) is connected to the pixel electrode.
  • TFT thin film transistor
  • Source Source
  • the Gate Driver on Array is a driving method in which a gate row scanning driving circuit is fabricated on a TFT array substrate by using an array process of an existing thin film transistor liquid crystal display (Array) process to realize gate-by-row scanning.
  • GOA technology can reduce the bonding process of external ICs, have the opportunity to increase production capacity and reduce product cost, and can make LCD panels more suitable for making narrow-frame or borderless display products.
  • oxide semiconductor thin film transistors such as Indium Gallium Zinc Oxide (IGZO) thin film transistors
  • IGZO Indium Gallium Zinc Oxide
  • the oxide semiconductor has a high carrier mobility, its threshold voltage is around 0V, and the swing of the subthreshold region is small, while the gate and source of many TFT elements are in the GOA circuit in the off state.
  • the voltage Vgs is usually 0V, which increases the design difficulty of the GOA circuit based on the oxide semiconductor thin film transistor.
  • the oxide semiconductor thin film transistor sometimes has a tendency to decrease the threshold voltage to a negative value, which will directly lead to the failure of the GOA circuit based on the oxide semiconductor thin film transistor.
  • the threshold voltage of the oxide semiconductor thin film transistor will move to a negative value, which will cause the GOA circuit to fail; likewise, under the electrical stress of some light, the threshold voltage of the oxide semiconductor thin film transistor will go to Negative values move. Therefore, designing a GOA circuit based on an oxide semiconductor thin film transistor must consider the influence of the threshold voltage drift of the TFT.
  • FIG. 1 shows a conventional GOA circuit based on an oxide semiconductor thin film transistor for the above problems, comprising a pull-up control module 100, a pull-up module 200, a downlink module 300, a first pull-down module 400, and The capacitor module 500 and the pull-down maintenance module 600 are lifted.
  • the existing GOA circuit based on the oxide semiconductor thin film transistor still has certain problems, for example, let N be a positive integer, and in the Nth stage GOA unit circuit, since the first constant voltage negative potential VSS and the second are set The constant voltage negative potential DCL, the Nth stage GOA unit circuit has a crosstalk current problem during the inactive period; since the drain of a thin film transistor T75 in the pull-down maintaining module 600 is electrically connected to the constant voltage high potential DCH, the constant voltage is high.
  • the potential DCH affects the pull-down maintenance of the first node Q(N) during the inactive period; in addition, when each frame picture is displayed, there is residual charge at the first node Q(N), which may affect the normal output of the GOA circuit, resulting in a screen display. abnormal.
  • An object of the present invention is to provide a GOA circuit based on an oxide semiconductor thin film transistor, which can not only prevent leakage, improve the reliability of the GOA circuit, but also avoid the generation of crosstalk current, and avoid the constant voltage high potential to be pulled down by the first node.
  • the effect is to remove the interference of the residual charge on the GOA circuit and ensure the normal output of the GOA circuit and the normal display of the picture.
  • the present invention provides a GOA circuit based on an oxide semiconductor thin film transistor, comprising a plurality of cascaded GOA unit circuits, each stage of the GOA unit circuit comprising: a pull-up control module, a pull-up module, and a downlink Module, first pull-down module, bootstrap capacitor module, and pull-down maintenance module;
  • N be a positive integer, in addition to the first stage GOA unit circuit, in the Nth stage GOA unit circuit:
  • the pull-up control module includes an eleventh thin film transistor, and a gate of the eleventh thin film transistor receives a level-transmitting signal of a first-stage N-1th GOA unit circuit, and the source is electrically connected to a constant voltage high potential The drain is electrically connected to the first node;
  • the pull-up module includes: a 21st thin film transistor, a gate of the 21st thin film transistor is electrically connected to the first node, and a source is electrically connected to the mth corresponding to the circuit of the Nth stage GOA unit Group clock signal, drain output scan drive signal;
  • the down-transmission module includes: a 22nd thin film transistor, a gate of the 22nd thin film transistor is electrically connected to the first node, and a source is electrically connected to the mth corresponding to the circuit of the Nth stage GOA unit Group clock signal, drain output stage signal;
  • the first pull-down module includes a forty-th thin film transistor and a forty-first thin film transistor; the gate and the source of the forty-th thin film transistor are electrically connected to the first node, and the drain is electrically connected to the drain a drain of the forty-th thin film transistor; a gate input of the forty-th thin film transistor corresponding to the m+2th group clock signal of the lower two-pole N+2th GOA unit circuit, and a source input scan driving signal;
  • the bootstrap capacitor module includes a capacitor, one end of the capacitor is electrically connected to the first node, and the other end is electrically connected to the scan driving signal;
  • the pull-down maintaining module includes: a dual inverter composed of a plurality of thin film transistors, a forty-second thin film transistor, a thirty-second thin film transistor, a seventy-fifth thin film transistor, and a seventy-sixth thin film transistor;
  • the input end of the dual inverter is electrically connected to the first node, and the output end is electrically connected to the second node;
  • the gate of the forty-second thin film transistor is electrically connected to the second node, and the drain is electrically connected In the first node, the source is electrically connected to the third node;
  • the gate of the thirty-second thin film transistor is electrically connected to the second node, the drain is electrically connected to the scan driving signal, and the source is electrically connected to a first constant voltage negative potential;
  • the gate and the drain of the seventy-fifth thin film transistor are electrically connected to the first node, the source is electrically connected to the third node; and the gate of the seventy-s
  • the second constant voltage negative potential is lower than the first constant voltage negative potential
  • Each of the thin film transistors is an oxide semiconductor thin film transistor.
  • the oxide semiconductor thin film transistor-based GOA circuit further includes an empty reset module for performing an empty reset of the first node before each frame is generated.
  • the clearing reset module includes a ninth thin film transistor, the gate of the ninth thin film transistor is connected to the scan enable signal, the drain is electrically connected to the first node, and the source is electrically connected to the first Constant voltage negative potential.
  • the clear reset module includes a ninth thin film transistor, the gate of the ninth thin film transistor is connected to the scan enable signal, the drain is electrically connected to the first node, and the source is electrically connected to the corresponding The mth group clock signal of the N-stage GOA unit circuit.
  • the clear reset module includes a ninth thin film transistor, and the ninth thin film crystal
  • the gate of the body tube is connected to the reset signal, the drain is electrically connected to the first node, and the source is electrically connected to the mth group clock signal corresponding to the circuit of the Nth stage GOA unit; the reset signal is at the scan enable signal Produced before.
  • the clock signal includes a total of M groups, and M is an integer multiple of 4, when N>M, an empty reset module is set in the Nth stage GOA unit circuit.
  • an empty reset module is set in each level of the GOA unit circuit.
  • the clock signal comprises a total of four groups: a first group of clock signals, a second group of clock signals, a third group of clock signals, and a fourth group of clock signals; when the mth group of clock signals is a third clock When the signal is a signal, the m+2 group clock signal is a first group clock signal, and when the clock signal is a fourth group clock signal, the m+2 group clock signal is a second group clock signal;
  • the waveform duty ratio of the four groups of clock signals is 25/75;
  • the empty reset module is set in the fifth to last stage GOA unit circuit.
  • the dual inverter includes: a 51st thin film transistor, the gate and the source of the 51st thin film transistor are electrically connected to a constant voltage high potential, and the drain is electrically connected to the fourth node; a fifty-two thin film transistor, the gate of the fifty-second thin film transistor is electrically connected to the first node, the drain is electrically connected to the fourth node, and the source is electrically connected to the first constant voltage negative potential; a thirteenth thin film transistor, the gate of the fifty-third thin film transistor is electrically connected to the fourth node, the source is electrically connected to the constant voltage high potential, and the drain is electrically connected to the second node; a transistor, a gate of the fifty-fourth thin film transistor is electrically connected to the first node, a drain is electrically connected to the second node, a source is electrically connected to the fifth node, and a seventh thirty-th thin film transistor is The gate of the seventy-third thin film transistor is electrically connected to the fourth node, the source is electrically
  • the gate of the eleventh thin film transistor is connected to a scan enable signal.
  • the present invention also provides a GOA circuit based on an oxide semiconductor thin film transistor, comprising a plurality of cascaded GOA unit circuits, each stage GOA unit circuit comprising: a pull-up control module, a pull-up module, a downlink module, and a first Pull-down module, bootstrap capacitor module, and pull-down maintenance module;
  • N be a positive integer, in addition to the first stage GOA unit circuit, in the Nth stage GOA unit circuit:
  • the pull-up control module includes an eleventh thin film transistor, and the eleventh thin film transistor
  • the gate receives the level-transmitting signal of the upper-stage N-1th GOA unit circuit, the source is electrically connected to the constant voltage high potential, and the drain is electrically connected to the first node;
  • the pull-up module includes: a 21st thin film transistor, a gate of the 21st thin film transistor is electrically connected to the first node, and a source is electrically connected to the mth corresponding to the circuit of the Nth stage GOA unit Group clock signal, drain output scan drive signal;
  • the down-transmission module includes: a 22nd thin film transistor, a gate of the 22nd thin film transistor is electrically connected to the first node, and a source is electrically connected to the mth corresponding to the circuit of the Nth stage GOA unit Group clock signal, drain output stage signal;
  • the first pull-down module includes a forty-th thin film transistor and a forty-first thin film transistor; the gate and the source of the forty-th thin film transistor are electrically connected to the first node, and the drain is electrically connected to the drain a drain of the forty-th thin film transistor; a gate input of the forty-th thin film transistor corresponding to the m+2th group clock signal of the lower two-pole N+2th GOA unit circuit, and a source input scan driving signal;
  • the bootstrap capacitor module includes a capacitor, one end of the capacitor is electrically connected to the first node, and the other end is electrically connected to the scan driving signal;
  • the pull-down maintaining module includes: a dual inverter composed of a plurality of thin film transistors, a forty-second thin film transistor, a thirty-second thin film transistor, a seventy-fifth thin film transistor, and a seventy-sixth thin film transistor;
  • the input end of the dual inverter is electrically connected to the first node, and the output end is electrically connected to the second node;
  • the gate of the forty-second thin film transistor is electrically connected to the second node, and the drain is electrically connected In the first node, the source is electrically connected to the third node;
  • the gate of the thirty-second thin film transistor is electrically connected to the second node, the drain is electrically connected to the scan driving signal, and the source is electrically connected to a first constant voltage negative potential;
  • the gate and the drain of the seventy-fifth thin film transistor are electrically connected to the first node, the source is electrically connected to the third node; and the gate of the seventy-s
  • the second constant voltage negative potential is lower than the first constant voltage negative potential
  • Each of the thin film transistors is an oxide semiconductor thin film transistor
  • the method further includes an empty reset module, configured to perform an empty reset on the first node before each frame is generated;
  • the dual inverter includes: a 51st thin film transistor, the gate and the source of the 51st thin film transistor are electrically connected to a constant voltage high potential, and the drain is electrically connected to the fourth node a fifty-second thin film transistor, the gate of the fifty-second thin film transistor is electrically connected to the first node, the drain is electrically connected to the fourth node, and the source is electrically connected to the first constant voltage negative potential; a fifty-third thin film transistor, the gate of the fifty-third thin film transistor is electrically connected to the fourth node, The source is electrically connected to the constant voltage high potential, and the drain is electrically connected to the second node; the fifty-fourth thin film transistor, the gate of the fifty-fourth thin film transistor is electrically connected to the first node, and the drain is electrically Connected to the second node, the source is electrically connected to the fifth node; the seventh thirteenth thin film transistor, the gate of the seventy-third thin film transistor is electrically connected to the fourth node, and the source
  • the gate of the eleventh thin film transistor is connected to the scan enable signal
  • the emptiness reset module includes a ninth thin film transistor, the gate of the ninth thin film transistor is connected to the reset signal, the drain is electrically connected to the first node, and the source is electrically connected to the corresponding Nth stage.
  • the mth group of clock signals of the GOA unit circuit; the reset signal is generated prior to the scan enable signal.
  • the GOA circuit based on an oxide semiconductor thin film transistor provided by the present invention not only prevents leakage, improves reliability of a GOA circuit, but also passes a forty-th thin film transistor in the first pull-down module
  • the gate is shorted to the source to avoid the crosstalk current generated by the GOA unit circuit during the inactive period, and the constant voltage is avoided by electrically connecting the gate and the drain of the 75th thin film transistor in the pull-down sustaining module to the first node.
  • the effect of the high potential on the pull-down maintenance of the first node is performed by setting the clear reset module to clear and reset the first node before each frame is generated, to remove the interference of the residual charge on the GOA circuit, and to ensure the normal output of the GOA circuit and The normal display of the picture.
  • FIG. 1 is a circuit diagram of a conventional GOA circuit based on an oxide semiconductor thin film transistor
  • FIG. 2 is a circuit diagram of a first embodiment of a GOA circuit based on an oxide semiconductor thin film transistor of the present invention
  • FIG. 3 is a second embodiment of a GOA circuit based on an oxide semiconductor thin film transistor of the present invention Circuit diagram
  • FIG. 4 is a circuit diagram of a third embodiment of a GOA circuit based on an oxide semiconductor thin film transistor of the present invention.
  • FIG. 5 is a connection diagram of a first-stage GOA unit circuit in the first, second, and third embodiments of the GOA circuit based on the oxide semiconductor thin film transistor of the present invention
  • FIG. 6 is a schematic diagram showing waveforms of input signals and key nodes of the first, second, and third embodiments of the GOA circuit based on the oxide semiconductor thin film transistor of the present invention
  • FIG. 7 is a schematic diagram of a connection structure of a second and third embodiment of a GOA circuit based on an oxide semiconductor thin film transistor according to the present invention.
  • FIG. 8 is a circuit diagram of a fourth embodiment of a GOA circuit based on an oxide semiconductor thin film transistor of the present invention.
  • FIG. 9 is a connection diagram of a first stage GOA unit circuit in a fourth embodiment of a GOA circuit based on an oxide semiconductor thin film transistor of the present invention.
  • FIG. 10 is a schematic diagram showing waveforms of an input signal and a key node of a fourth embodiment of a GOA circuit based on an oxide semiconductor thin film transistor of the present invention
  • FIG. 11 is a schematic diagram showing a connection structure of a fourth embodiment of a GOA circuit based on an oxide semiconductor thin film transistor of the present invention.
  • the present invention provides a GOA circuit based on an oxide semiconductor thin film transistor.
  • 2 is a circuit diagram of a first embodiment of a GOA circuit based on an oxide semiconductor thin film transistor according to the present invention, including a plurality of cascaded GOA unit circuits, each stage of the GOA unit circuit including: a pull-up control module 100, The pull-up module 200, the downlink module 300, the first pull-down module 400, the bootstrap capacitor module 500, and the pull-down maintenance module 600.
  • N be a positive integer, in addition to the first stage GOA unit circuit, in the Nth stage GOA unit circuit:
  • the pull-up control module 100 includes an eleventh thin film transistor T11, and the gate of the eleventh thin film transistor T11 receives the graded signal ST(N-1) of the upper-stage N-1th GOA unit circuit, the source The pole is electrically connected to the constant voltage high potential DCH, and the drain is electrically connected to the first node Q(N).
  • the pull-up module 200 includes: a 21st thin film transistor T21, the gate of the 21st thin film transistor T21 is electrically connected to the first node Q(N), and the source is electrically connected to the corresponding Nth The mth group clock signal CK(m) of the stage GOA unit circuit and the drain output scan drive signal G(N).
  • the down-going module 300 includes: a twenty-second thin film transistor T22, the gate of the twenty-second thin film transistor T22 is electrically connected to the first node Q(N), and the source is electrically connected to the corresponding Nth The mth group clock signal CK(m) of the stage GOA unit circuit and the drain output stage signal ST(N).
  • the first pull-down module 400 includes a forty-th thin film transistor T40 and a forty-first thin film transistor T41; the gate and the source of the forty-th thin film transistor T40 are electrically connected to the first node Q (N).
  • the drain is electrically connected to the drain of the 41st thin film transistor T41; the gate input of the 41st thin film transistor T41 corresponds to the m+2 group of the lower two-pole N+2 stage GOA unit circuit
  • the bootstrap capacitor module 500 includes a capacitor Cb. One end of the capacitor Cb is electrically connected to the first node Q(N), and the other end is electrically connected to the scan driving signal G(N).
  • the pull-down maintaining module 600 includes: a dual inverter F composed of a plurality of thin film transistors, a forty-second thin film transistor T42, a thirty-second thin film transistor T32, a seventy-fifth thin film transistor T75, and a seventieth a thin film transistor T76; an input end of the dual inverter F is electrically connected to the first node Q(N), and an output end is electrically connected to the second node P(N); the forty-second thin film transistor T42 The gate is electrically connected to the second node P(N), the drain is electrically connected to the first node Q(N), and the source is electrically connected to the third node T(N); the thirty-second film The gate of the transistor T32 is electrically connected to the second node P(N), the drain is electrically connected to the scan driving signal G(N), and the source is electrically connected to the first constant voltage negative potential VSS; The gate and the drain of the five thin film transistor T75 are electrically connected to the first no
  • the dual inverter F includes a fifty-first thin film transistor T51, and the gate and the source of the fifty-first thin film transistor T51 are electrically connected to a constant voltage high potential DCH, and the drain is electrically Connected to the fourth node S(N); the fifty-second thin film transistor T52, the gate of the fifty-second thin film transistor T52 is electrically connected to the first node Q(N), and the drain is electrically connected to the fourth The node S (N), the source is electrically connected to the first constant voltage negative potential VSS; the fifty-third thin film transistor T53, the gate of the fifty-third thin film transistor T53 is electrically connected to the fourth node S (N) The source is electrically connected to the constant voltage high potential DCH, the drain is electrically connected to the second node P(N); the fifty-fourth thin film transistor T54, the gate electrical property of the fifty-fourth thin film transistor T54 Connected to the first node Q(N), the drain is electrically connected to the second node P(N),
  • Each of the thin film transistors is an oxide semiconductor thin film transistor.
  • the oxide semiconductor thin film transistor is an IGZO thin film transistor.
  • the gate of the eleventh thin film transistor T11 is connected to the scan enable signal STV
  • the twentieth The source of the thin film transistor T21 and the source of the twelfth thin film transistor T22 are electrically connected to the first group of clock signals CK(1)
  • the gate input of the forty-first thin film transistor T41 corresponds to the lower two poles and the third The third group of clock signals CK(3) of the stage GOA unit circuit, the source input scan drive signal G(1).
  • the working process of the GOA circuit based on the oxide semiconductor thin film transistor of the present invention is as follows: the first stage GOA unit circuit is started from the scan start signal STV, and the scan driving is sequentially performed step by step. The scan driving is performed to the Nth stage GOA unit circuit.
  • the level signal ST(N-1) of the upper N-1th stage GOA unit circuit is at a high potential, the eleventh thin film transistor T11 is turned on, and the constant voltage is high.
  • the DCH raises the first node Q(N) to a high potential through the eleventh thin film transistor T11, and charges the capacitor Cb.
  • stage pass signal ST(N-1) of the N-1th stage GOA unit circuit is turned to a low level, the eleventh thin film transistor T11 is turned off, and the first node Q(N) is maintained at a high potential by the capacitor Cb, so that The twenty-first thin film transistor T21 and the twenty-second thin film transistor T22 are turned on.
  • the mth group clock signal CK(m) corresponding to the Nth stage GOA unit circuit is turned to a high level, and the drain of the 21st thin film transistor T21 outputs a high potential scan driving signal G(N), The drain of the twenty-two thin film transistor T22 outputs a high-level pass signal ST(N), while the m-th group clock signal CK(m) continues to charge the capacitor Cb through the twenty-first thin film transistor T21, so that the first node Q (N) rises to a higher potential.
  • the scan driving signal G(N) transitions to a low potential with the mth group clock signal CK(m), corresponding to the m+2th group clock signal CK(m+2) of the lower two-pole N+2th GOA unit circuit.
  • the forty-first thin film transistor T41 and the fortieth thin film transistor T40 are turned on, and the first node Q(N) is discharged through the pull-down module 400 to be turned into a low potential.
  • a time slot in which the scan driving signal G(N) is high is generally referred to as an active period.
  • the source of the eleventh thin film transistor T11 is connected to the constant voltage high potential DCH, so the first node Q(N) does not pass the eleventh thin film transistor T11.
  • the two thin film transistors T32 are both turned off, ensuring that the first node Q(N) and the scan driving signal G(N) have stable output high potential;
  • the high potential of the node Q(N) is transmitted to the source of the forty-second thin film transistor T42 through the seventy-fifth thin film transistor T75, so that the first node Q(N) does not generate leakage through the forty-second thin film transistor T42;
  • the forty-th thin film transistor T41 is in an off state at this time, and the source of the forty-th thin film transistor T41 inputs a high potential scan driving signal G(N), and the first node Q(N) does not pass the fourth.
  • the series path of the eleven thin film transistor T41 and the fortieth thin film transistor T40 is leaked.
  • the inverter F output is high, that is, the second node P(N) is high, and the forty-second thin film transistor T42,
  • the thirty-two thin film transistor T32 and the seventy-seven thin film transistor T76 are both turned on, and the first node Q(N) is further pulled down by the forty-second thin film transistor T42 and the seventy-sixth thin film transistor T76 and maintained at the first The second constant voltage negative potential DCL; the scan driving signal G(N) is further pulled down by the thirty-second thin film transistor T32 and maintained at the first constant voltage negative potential VSS.
  • the gate of the forty-th thin film transistor T40 is short-circuited with the source, the gate-source voltage Vgs of the fortieth thin film transistor T40 is equal to 0V.
  • the gate of the fortieth thin film transistor T40 is connected to the scan driving signal G(N+2) of the N+2 stage GOA unit circuit, and the crosstalk current caused by the second constant voltage negative potential DCL can be avoided. It flows through the fortieth thin film transistor T40.
  • the source of the forty-second thin film transistor T42 is electrically connected to the drain of the seventy-fifth thin film transistor T75.
  • the drain of the seventy-fifth thin film transistor T75 is electrically connected to the constant voltage high potential DCH, so that the influence of the constant voltage high potential DCH on the pull-down maintenance of the first node Q(N) during the non-active period can be avoided.
  • the second constant voltage negative potential DCL is set lower than the first constant voltage negative potential VSS to facilitate separate independent control.
  • the fifty-second thin film transistor T52 and the fifty-fourth thin film transistor T54 in the main inverter of the dual inverter F are both turned on, and fifth The thirteen thin film transistor T53 is turned off, the seventy-fourth thin film transistor T74 in the auxiliary main inverter is turned on, the seventy-third thin film transistor T73 is turned off, and the potential of the second node P(N) is pulled down to be lower than the first
  • the second constant voltage negative potential DCL with a constant voltage negative potential VSS ensures that the first node Q(N) and the scan drive signal G(N) have a stable output high potential; when the non-active period, the first node Q(N) is At a low potential, the fifty-second thin film transistor T52 and the fifty-fourth thin film transistor T54 in the main inverter of the dual
  • a second embodiment of the GOA circuit of the film transistor differs from the first embodiment in that an empty reset module 700 is added.
  • the clear reset module 700 includes a ninth thin film transistor T9.
  • the gate of the ninth thin film transistor T9 is connected to the scan enable signal STV, and the drain is electrically connected to the first node Q(N).
  • the pole is electrically connected to the first constant voltage negative potential VSS.
  • the clear reset module 700 is configured to perform the clear reset of the first node Q(N) by using the scan enable signal STV before each frame picture is generated, to remove the interference of the residual charge on the GOA circuit, and before the first frame is generated. It is also possible to clear the first node Q(N), prevent the influence of the first frame picture floating on the output of the GOA circuit, and ensure the normal output of the GOA circuit and the normal display of the picture.
  • the clock signal includes M groups, and M is an integer multiple of 4.
  • N>M the clear reset module 700 is set in the Nth stage GOA unit circuit.
  • FIG. 6 and FIG. 7 take the four groups of the clock signal as an example.
  • the clear reset module 700 is set in the fifth-level to the last-level GOA unit circuit.
  • the fifth stage to the last stage of the GOA unit circuit are required to access the scan start signal STV for controlling the clear reset module 700; and the clear reset module 700 is not provided in the first stage to the fourth stage GOA unit circuit, Only the first stage GOA unit circuit needs to access the scan enable signal STV for starting the scan drive.
  • the four groups of clock signals are: a first group of clock signals CK(1), a second group of clock signals CK(2), a third group of clock signals CK(3), and a fourth group of clock signals CK ( 4); when the mth group clock signal CK(m) is the third clock signal CK(3), the m+2 group clock signal CK(m+2) is the first group clock signal CK(1) When the clock signal CK(m) is the fourth group clock signal CK(4), the m+2 group clock signal CK(m+2) is the second group clock signal CK(2);
  • the waveform duty ratio of the four sets of clock signals is 25/75 to avoid the influence of the clock signal waveform on the first pull-down module 400, and the waveform at the first node Q(N) is "convex" shaped.
  • the clear reset module 700 is set in the ninth stage to the last stage GOA unit circuit, and correspondingly, the ninth stage is The last stage of the GOA unit circuit needs to access the scan start signal STV for controlling the clear reset module 700; and the first level to the eighth stage GOA unit circuit are not provided with the clear reset module 700, only the first stage The GOA unit circuit needs to access a scan enable signal STV for starting the scan drive.
  • FIG. 4, FIG. 5, FIG. 6, and FIG. 7 as a third embodiment of the GOA circuit based on the oxide semiconductor thin film transistor of the present invention.
  • the third embodiment is different from the second embodiment only in that The source of the ninth thin film transistor T9 is electrically connected to the mth group clock signal CK(m) corresponding to the Nth stage GOA unit circuit, which has the advantage of reducing the ninth thin film transistor T9 to the first node Q(N) The effect of leakage during the action.
  • the rest are the same as the second embodiment, here No longer.
  • FIG. 8 , FIG. 9 , FIG. 10 and FIG. 11 are a fourth embodiment of a GOA circuit based on an oxide semiconductor thin film transistor according to the present invention.
  • the fourth embodiment also provides an empty reset module 700, and a third implementation.
  • the gate of the ninth thin film transistor T9 in the reset reset module 700 is connected to the reset signal Reset, that is, the fourth embodiment needs to add a reset signal Reset different from the scan enable signal STV, and As shown in FIG. 10, the reset signal Reset is generated before the scan enable signal STV.
  • the empty reset module 700 can be set at each of the first to last stage GOA unit circuits.
  • the first stage GOA unit circuit accesses the reset signal Reset for controlling the clear reset module 700 and the scan for starting the scan driver.
  • the start signal STV; each of the second to last stage GOA unit circuits is connected to the reset signal Reset for controlling the clear reset module 700, and the reset signal Reset can be implemented before each frame is generated.
  • the effect of the output ensures the normal output of the GOA circuit and the normal display of the picture.
  • the GOA circuit based on the oxide semiconductor thin film transistor of the present invention can not only prevent leakage, improve the reliability of the GOA circuit, but also pass the gate and source of the fortieth thin film transistor in the first pull-down module. Extremely short to avoid the crosstalk current generated by the GOA unit circuit during the inactive period, and the constant voltage high potential pair is avoided by electrically connecting the gate and the drain of the 75th thin film transistor in the pull-down sustaining module to the first node.
  • the effect of a node pull-down maintenance is to clear and reset the first node before each frame picture is generated by setting the clear reset module to clear the interference of the residual charge on the GOA circuit, and ensure the normal output of the GOA circuit and the normal display of the picture. .

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Abstract

一种基于氧化物半导体薄膜晶体管的GOA电路，不仅能够防止漏电，提高GOA电路的可靠性，还通过将第一下拉模块（400）内的第四十薄膜晶体管（T40）的栅极与源极短接来避免GOA单元电路在非作用期间产生串扰电流，通过将下拉维持模块（600）中第七十五薄膜晶体管（T75）的栅极与漏极均电性连接于第一节点（Q(N)）来避免恒压高电位（DCH）对第一节点（Q(N)）下拉维持的影响，通过设置清空重置模块（700）在每一帧画面产生前对第一节点（Q(N)）进行清空重置，以清除残余电荷对GOA电路的干扰，保证GOA电路的正常输出和画面的正常显示。

Description

基于氧化物半导体薄膜晶体管的GOA电路 技术领域
本发明涉及液晶显示器驱动领域，尤其涉及一种基于氧化物半导体薄膜晶体管的GOA电路。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)与彩色滤光片基板(Color Filter，CF)之间灌入液晶分子，并在两片基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
主动式液晶显示器中，每个像素电性连接一个薄膜晶体管(TFT)，薄膜晶体管的栅极(Gate)连接至水平扫描线，漏极(Drain)连接至垂直方向的数据线，源极(Source)则连接至像素电极。在水平扫描线上施加足够的电压，会使得电性连接至该条水平扫描线上的所有TFT打开，从而数据线上的信号电压能够写入像素，控制不同液晶的透光度进而达到控制色彩与亮度的效果。Gate Driver on Array，简称GOA，是利用现有的薄膜晶体管液晶显示器的阵列(Array)制程将栅极行扫描驱动电路制作在TFT阵列基板上，实现对栅极逐行扫描的驱动方式。GOA技术能减少外接IC的焊接(bonding)工序，有机会提升产能并降低产品成本，而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
随着氧化物半导体薄膜晶体管，如铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)薄膜晶体管的发展，基于氧化物半导体薄膜晶体管的面板周边集成电路也成为关注的焦点。虽然氧化物半导体具有较高的载流子迁移率，但是其阈值电压值在0V左右，而且亚阈值区域的摆幅较小，而GOA电路在关态时很多TFT元件的栅极与源极之间的电压Vgs通常为0V，这样就会增加基于氧化物半导体薄膜晶体管的GOA电路的设计难度，一些适用 于非晶硅半导体薄膜晶体管的扫描驱动电路应用到基于氧化物半导体薄膜晶体管的GOA电路时就会存在一些功能性问题。
另外，在某些外在因素的诱导和应力作用下，氧化物半导体薄膜晶体管有时候也会产生阈值电压往负值减小的趋势，这样将会直接导致基于氧化物半导体薄膜晶体管的GOA电路无法工作，例如，在高温下，氧化物半导体薄膜晶体管的阈值电压会往负值移动，这样会导致GOA电路失效；同样，在一些光照的电应力作用下，氧化物半导体薄膜晶体管的阈值电压会往负值移动。因此，设计基于氧化物半导体薄膜晶体管的GOA电路必须要考虑TFT阈值电压漂移的影响。
图1所示为一种现有可行的针对上述问题的基于氧化物半导体薄膜晶体管的GOA电路，包括上拉控制模块100、上拉模块200、下传模块300、第一下拉模块400、自举电容模块500、及下拉维持模块600。但该现有的基于氧化物半导体薄膜晶体管的GOA电路仍存在一定的问题，例如：设N为正整数，在第N级GOA单元电路中，由于设置了第一恒压负电位VSS与第二恒压负电位DCL，该第N级GOA单元电路在非作用期间存在串扰电流的问题；由于下拉维持模块600中的一薄膜晶体管T75的漏极电性连接于恒压高电位DCH，恒压高电位DCH会影响非作用期间对第一节点Q(N)的下拉维持；此外，显示各帧画面时，第一节点Q(N)处存在残余电荷，可能影响GOA电路的正常输出，造成画面显示异常。
发明内容
本发明的目的在于提供一种基于氧化物半导体薄膜晶体管的GOA电路，不仅能够防止漏电，提高GOA电路的可靠性，还能够避免串扰电流的产生，避免恒压高电位对第一节点下拉维持的影响，清除残余电荷对GOA电路的干扰，保证GOA电路的正常输出和画面的正常显示。
为实现上述目的，本发明提供一种基于氧化物半导体薄膜晶体管的GOA电路，包括级联的多个GOA单元电路，每一级GOA单元电路均包括：上拉控制模块、上拉模块、下传模块、第一下拉模块、自举电容模块、及下拉维持模块；
设N为正整数，除第一级GOA单元电路以外，在第N级GOA单元电路中：
所述上拉控制模块包括第十一薄膜晶体管，所述第十一薄膜晶体管的栅极接收上一级第N-1级GOA单元电路的级传信号，源极电性连接于恒压高电位，漏极电性连接于第一节点；
所述上拉模块包括：第二十一薄膜晶体管，所述第二十一薄膜晶体管的栅极电性连接于第一节点，源极电性连接于对应该第N级GOA单元电路的第m组时钟信号，漏极输出扫描驱动信号；
所述下传模块包括：第二十二薄膜晶体管，所述第二十二薄膜晶体管的栅极电性连接于第一节点，源极电性连接于对应该第N级GOA单元电路的第m组时钟信号，漏极输出级传信号；
所述第一下拉模块包括第四十薄膜晶体管、与第四十一薄膜晶体管；所述第四十薄膜晶体管的栅极与源极均电性连接于第一节点，漏极电性连接于第四十一薄膜晶体管的漏极；所述第四十一薄膜晶体管的栅极输入对应于下两极第N+2级GOA单元电路的第m+2组时钟信号，源极输入扫描驱动信号；
所述自举电容模块包括电容，所述电容的一端电性连接于第一节点，另一端电性连接于扫描驱动信号；
所述下拉维持模块包括：一由多个薄膜晶体管构成的双重反相器、第四十二薄膜晶体管、第三十二薄膜晶体管、第七十五薄膜晶体管、与第七十六薄膜晶体管；所述双重反相器的输入端电性连接于第一节点，输出端电性连接于第二节点；所述第四十二薄膜晶体管的栅极电性连接于第二节点，漏极电性连接于第一节点，源极电性连接于第三节点；所述第三十二薄膜晶体管的栅极电性连接于第二节点，漏极电性连接于扫描驱动信号，源极电性连接于第一恒压负电位；所述第七十五薄膜晶体管的栅极与漏极均电性连接于第一节点，源极电性连接于第三节点；所述第七十六薄膜晶体管的栅极电性连接于第二节点，漏极电性连接于第三节点，源极电性连接于第二恒压负电位；
所述第二恒压负电位低于第一恒压负电位；
各个薄膜晶体管均为氧化物半导体薄膜晶体管。
所述基于氧化物半导体薄膜晶体管的GOA电路还包括一清空重置模块，用于在每一帧画面产生前对第一节点进行清空重置。
可选的，所述清空重置模块包括一第九薄膜晶体管，所述第九薄膜晶体管的栅极接入扫描启动信号，漏极电性连接于第一节点，源极电性连接于第一恒压负电位。
可选的，所述清空重置模块包括一第九薄膜晶体管，所述第九薄膜晶体管的栅极接入扫描启动信号，漏极电性连接于第一节点，源极电性连接于对应第N级GOA单元电路的第m组时钟信号。
可选的，所述清空重置模块包括一第九薄膜晶体管，所述第九薄膜晶 体管的栅极接入重置信号，漏极电性连接于第一节点，源极电性连接于对应第N级GOA单元电路的第m组时钟信号；所述重置信号在扫描启动信号之前产生。
可选的，设所述时钟信号共包括M组，M为4的整数倍，则当N＞M时，在第N级GOA单元电路中设置清空重置模块。
可选的，在每一级GOA单元电路中均设置清空重置模块。
可选的，所述时钟信号共包括四组:第一组时钟信号、第二组时钟信号、第三组时钟信号、及第四组时钟信号；当所述第m组时钟信号为第三时钟信号时，所述第m+2组时钟信号为第一组时钟信号，当所述时钟信号为第四组时钟信号时，所述第m+2组时钟信号为第二组时钟信号；所述四组时钟信号的波形占空比为25/75；
在第五级至最后一级GOA单元电路中设置清空重置模块。
所述双重反相器包括：第五十一薄膜晶体管，所述第五十一薄膜晶体管的栅极与源极均电性连接于恒压高电位，漏极电性连接于第四节点；第五十二薄膜晶体管，所述第五十二薄膜晶体管的栅极电性连接于第一节点，漏极电性连接于第四节点，源极电性连接于第一恒压负电位；第五十三薄膜晶体管，所述第五十三薄膜晶体管的栅极电性连接于第四节点，源极电性连接于恒压高电位，漏极电性连接于第二节点；第五十四薄膜晶体管，所述第五十四薄膜晶体管的栅极电性连接于第一节点，漏极电性连接于第二节点，源极电性连接于第五节点；第七十三薄膜晶体管，所述第七十三薄膜晶体管的栅极电性连接于第四节点，源极电性连接于恒压高电位，漏极电性连接于第五节点；第七十四薄膜晶体管，所述第七十四薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二恒压负电位，漏极电性连接于第五节点；其中所述第五十一薄膜晶体管、第五十二薄膜晶体管、第五十三薄膜晶体管、与第五十四薄膜晶体管构成主反相器，所述第七十三薄膜晶体管、与第七十四薄膜晶体管构成辅助反相器。
在第一级GOA单元电路中，所述第十一薄膜晶体管的栅极接入扫描启动信号。
本发明还提供一种基于氧化物半导体薄膜晶体管的GOA电路，包括级联的多个GOA单元电路，每一级GOA单元电路均包括：上拉控制模块、上拉模块、下传模块、第一下拉模块、自举电容模块、及下拉维持模块；
设N为正整数，除第一级GOA单元电路以外，在第N级GOA单元电路中：
所述上拉控制模块包括第十一薄膜晶体管，所述第十一薄膜晶体管的 栅极接收上一级第N-1级GOA单元电路的级传信号，源极电性连接于恒压高电位，漏极电性连接于第一节点；
所述上拉模块包括：第二十一薄膜晶体管，所述第二十一薄膜晶体管的栅极电性连接于第一节点，源极电性连接于对应该第N级GOA单元电路的第m组时钟信号，漏极输出扫描驱动信号；
所述下传模块包括：第二十二薄膜晶体管，所述第二十二薄膜晶体管的栅极电性连接于第一节点，源极电性连接于对应该第N级GOA单元电路的第m组时钟信号，漏极输出级传信号；
所述第一下拉模块包括第四十薄膜晶体管、与第四十一薄膜晶体管；所述第四十薄膜晶体管的栅极与源极均电性连接于第一节点，漏极电性连接于第四十一薄膜晶体管的漏极；所述第四十一薄膜晶体管的栅极输入对应于下两极第N+2级GOA单元电路的第m+2组时钟信号，源极输入扫描驱动信号；
所述自举电容模块包括电容，所述电容的一端电性连接于第一节点，另一端电性连接于扫描驱动信号；
所述下拉维持模块包括：一由多个薄膜晶体管构成的双重反相器、第四十二薄膜晶体管、第三十二薄膜晶体管、第七十五薄膜晶体管、与第七十六薄膜晶体管；所述双重反相器的输入端电性连接于第一节点，输出端电性连接于第二节点；所述第四十二薄膜晶体管的栅极电性连接于第二节点，漏极电性连接于第一节点，源极电性连接于第三节点；所述第三十二薄膜晶体管的栅极电性连接于第二节点，漏极电性连接于扫描驱动信号，源极电性连接于第一恒压负电位；所述第七十五薄膜晶体管的栅极与漏极均电性连接于第一节点，源极电性连接于第三节点；所述第七十六薄膜晶体管的栅极电性连接于第二节点，漏极电性连接于第三节点，源极电性连接于第二恒压负电位；
所述第二恒压负电位低于第一恒压负电位；
各个薄膜晶体管均为氧化物半导体薄膜晶体管；
还包括一清空重置模块，用于在每一帧画面产生前对第一节点进行清空重置；
其中，所述双重反相器包括：第五十一薄膜晶体管，所述第五十一薄膜晶体管的栅极与源极均电性连接于恒压高电位，漏极电性连接于第四节点；第五十二薄膜晶体管，所述第五十二薄膜晶体管的栅极电性连接于第一节点，漏极电性连接于第四节点，源极电性连接于第一恒压负电位；第五十三薄膜晶体管，所述第五十三薄膜晶体管的栅极电性连接于第四节点， 源极电性连接于恒压高电位，漏极电性连接于第二节点；第五十四薄膜晶体管，所述第五十四薄膜晶体管的栅极电性连接于第一节点，漏极电性连接于第二节点，源极电性连接于第五节点；第七十三薄膜晶体管，所述第七十三薄膜晶体管的栅极电性连接于第四节点，源极电性连接于恒压高电位，漏极电性连接于第五节点；第七十四薄膜晶体管，所述第七十四薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二恒压负电位，漏极电性连接于第五节点；其中所述第五十一薄膜晶体管、第五十二薄膜晶体管、第五十三薄膜晶体管、与第五十四薄膜晶体管构成主反相器，所述第七十三薄膜晶体管、与第七十四薄膜晶体管构成辅助反相器；
其中，在第一级GOA单元电路中，所述第十一薄膜晶体管的栅极接入扫描启动信号；
其中，所述清空重置模块包括一第九薄膜晶体管，所述第九薄膜晶体管的栅极接入重置信号，漏极电性连接于第一节点，源极电性连接于对应第N级GOA单元电路的第m组时钟信号；所述重置信号在扫描启动信号之前产生。
本发明的有益效果：本发明提供的一种基于氧化物半导体薄膜晶体管的GOA电路，不仅能够防止漏电，提高GOA电路的可靠性，还通过将第一下拉模块内的第四十薄膜晶体管的栅极与源极短接来避免GOA单元电路在非作用期间产生串扰电流，通过将下拉维持模块中第七十五薄膜晶体管的栅极与漏极均电性连接于第一节点来避免恒压高电位对第一节点下拉维持的影响，通过设置清空重置模块在每一帧画面产生前对第一节点进行清空重置，以清除残余电荷对GOA电路的干扰，保证GOA电路的正常输出和画面的正常显示。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为一种现有的基于氧化物半导体薄膜晶体管的GOA电路的电路图；
图2为本发明基于氧化物半导体薄膜晶体管的GOA电路的第一实施例的电路图；
图3为本发明基于氧化物半导体薄膜晶体管的GOA电路的第二实施例 的电路图；
图4为本发明基于氧化物半导体薄膜晶体管的GOA电路的第三实施例的电路图；
图5为本发明基于氧化物半导体薄膜晶体管的GOA电路的第一、第二、第三实施例中第一级GOA单元电路的连接关系图；
图6为本发明基于氧化物半导体薄膜晶体管的GOA电路的第一、第二、第三实施例的输入信号与关键节点的波形示意图；
图7为本发明基于氧化物半导体薄膜晶体管的GOA电路的第二、第三实施例的连接架构示意图；
图8为本发明基于氧化物半导体薄膜晶体管的GOA电路的第四实施例的电路图；
图9为本发明基于氧化物半导体薄膜晶体管的GOA电路的第四实施例中第一级GOA单元电路的连接关系图；
图10为本发明基于氧化物半导体薄膜晶体管的GOA电路的第四实施例的输入信号与关键节点的波形示意图；
图11为本发明基于氧化物半导体薄膜晶体管的GOA电路的第四实施例的连接架构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
本发明提供一种基于氧化物半导体薄膜晶体管的GOA电路。请参阅图2，为本发明基于氧化物半导体薄膜晶体管的GOA电路的第一实施例的电路图，包括级联的多个GOA单元电路，每一级GOA单元电路均包括：上拉控制模块100、上拉模块200、下传模块300、第一下拉模块400、自举电容模块500、及下拉维持模块600。
设N为正整数，除第一级GOA单元电路以外，在第N级GOA单元电路中：
所述上拉控制模块100包括第十一薄膜晶体管T11，所述第十一薄膜晶体管T11的栅极接收上一级第N-1级GOA单元电路的级传信号ST(N-1)，源极电性连接于恒压高电位DCH，漏极电性连接于第一节点Q(N)。
所述上拉模块200包括：第二十一薄膜晶体管T21，所述第二十一薄膜晶体管T21的栅极电性连接于第一节点Q(N)，源极电性连接于对应该第N级GOA单元电路的第m组时钟信号CK(m)，漏极输出扫描驱动信号G(N)。
所述下传模块300包括：第二十二薄膜晶体管T22，所述第二十二薄膜晶体管T22的栅极电性连接于第一节点Q(N)，源极电性连接于对应该第N级GOA单元电路的第m组时钟信号CK(m)，漏极输出级传信号ST(N)。
所述第一下拉模块400包括第四十薄膜晶体管T40、与第四十一薄膜晶体管T41；所述第四十薄膜晶体管T40的栅极与源极均电性连接于第一节点Q(N)，漏极电性连接于第四十一薄膜晶体管T41的漏极；所述第四十一薄膜晶体管T41的栅极输入对应于下两极第N+2级GOA单元电路的第m+2组时钟信号CK(m+2)，源极输入扫描驱动信号G(N)。
所述自举电容模块500包括电容Cb，所述电容Cb的一端电性连接于第一节点Q(N)，另一端电性连接于扫描驱动信号G(N)。
所述下拉维持模块600包括：一由多个薄膜晶体管构成的双重反相器F、第四十二薄膜晶体管T42、第三十二薄膜晶体管T32、第七十五薄膜晶体管T75、与第七十六薄膜晶体管T76；所述双重反相器F的输入端电性连接于第一节点Q(N)，输出端电性连接于第二节点P(N)；所述第四十二薄膜晶体管T42的栅极电性连接于第二节点P(N)，漏极电性连接于第一节点Q(N)，源极电性连接于第三节点T(N)；所述第三十二薄膜晶体管T32的栅极电性连接于第二节点P(N)，漏极电性连接于扫描驱动信号G(N)，源极电性连接于第一恒压负电位VSS；所述第七十五薄膜晶体管T75的栅极与漏极均电性连接于第一节点Q(N)，源极电性连接于第三节点T(N)；所述第七十六薄膜晶体管T76的栅极电性连接于第二节点P(N)，漏极电性连接于第三节点T(N)，源极电性连接于第二恒压负电位DCL。具体地，所述双重反相器F包括：第五十一薄膜晶体管T51，所述第五十一薄膜晶体管T51的栅极与源极均电性连接于恒压高电位DCH，漏极电性连接于第四节点S(N)；第五十二薄膜晶体管T52，所述第五十二薄膜晶体管T52的栅极电性连接于第一节点Q(N)，漏极电性连接于第四节点S(N)，源极电性连接于第一恒压负电位VSS；第五十三薄膜晶体管T53，所述第五十三薄膜晶体管T53的栅极电性连接于第四节点S(N)，源极电性连接于恒压高电位DCH，漏极电性连接于第二节点P(N)；第五十四薄膜晶体管T54，所述第五十四薄膜晶体管T54的栅极电性连接于第一节点Q(N)，漏极电性连接于第二节点P(N)，源极电性连接于第五节点K(N)；第七十三薄膜晶体管T73，所述第七十三薄膜晶体管T73的栅极电性连接于第四节点S(N)，源极电性连接于恒压高电位DCH，漏极电性连接于第五节点K(N)；第七十四薄膜晶体管T74，所述第七十四薄膜晶体管T74的栅极电性连接于第一节点Q(N)，源极电性连接于第二恒压负电位DCL，漏极电性连接于第五节点K(N)；其 中所述第五十一薄膜晶体管T51、第五十二薄膜晶体管T52、第五十三薄膜晶体管T53、与第五十四薄膜晶体管T54构成主反相器，所述第七十三薄膜晶体管T73、与第七十四薄膜晶体管T74构成辅助反相器。
各个薄膜晶体管均为氧化物半导体薄膜晶体管，优选的，所述氧化物半导体薄膜晶体管为IGZO薄膜晶体管。
特别地，请参阅图5，在本发明的第一实施例中，在第一级GOA单元电路内，所述第十一薄膜晶体管T11的栅极接入扫描启动信号STV，所述第二十一薄膜晶体管T21的源极及第二十二薄膜晶体管T22的源极均电性连接于第一组时钟信号CK(1)，第四十一薄膜晶体管T41的栅极输入对应于下两极第三级GOA单元电路的第三组时钟信号CK(3)，源极输入扫描驱动信号G(1)。
请同时参阅图2与图6，本发明基于氧化物半导体薄膜晶体管的GOA电路第一实施例的工作过程为：自扫描启动信号STV启动第一级GOA单元电路，依次逐级进行扫描驱动。扫描驱动进行至第N级GOA单元电路，上一级第N-1级GOA单元电路的级传信号ST(N-1)为高电位时，第十一薄膜晶体管T11导通，恒压高电位DCH通过第十一薄膜晶体管T11将第一节点Q(N)抬升到高电位，并对电容Cb充电。随后，第N-1级GOA单元电路的级传信号ST(N-1)转为低电位，第十一薄膜晶体管T11断开，第一节点Q(N)通过电容Cb维持在高电位，使得第二十一薄膜晶体管T21与第二十二薄膜晶体管T22导通。接着，对应于该第N级GOA单元电路的第m组时钟信号CK(m)转为高电平，第二十一薄膜晶体管T21的漏极输出高电位的扫描驱动信号G(N)，第二十二薄膜晶体管T22的漏极输出高电位的级传信号ST(N)，同时第m组时钟信号CK(m)通过第二十一薄膜晶体管T21继续给电容Cb充电，使得第一节点Q(N)上升到一更高电位。然后，扫描驱动信号G(N)随着第m组时钟信号CK(m)转变为低电位，对应于下两极第N+2级GOA单元电路的第m+2组时钟信号CK(m+2)为高电位，第四十一薄膜晶体管T41与第四十薄膜晶体管T40导通，第一节点Q(N)通过下拉模块400放电，转变为低电位。
一般将扫描驱动信号G(N)为高电位的时隙称为作用期间。在作用期间，由于第一节点Q(N)为高电位，第十一薄膜晶体管T11的源极接入恒压高电位DCH，因此第一节点Q(N)不会通过第十一薄膜晶体管T11产生漏电；同时，由于第一节点Q(N)为高电位，经双重反相器F反相后得到第二节点P(N)为低电位，第四十二薄膜晶体管T42、及第三十二薄膜晶体管T32均断开，确保第一节点Q(N)和扫描驱动信号G(N)稳定的输出高电位；第一 节点Q(N)的高电位通过第七十五薄膜晶体管T75传递至第四十二薄膜晶体管T42的源极，因此第一节点Q(N)不会通过第四十二薄膜晶体管T42产生漏电；第四十一薄膜晶体管T41此时为断开状态，且第四十一薄膜晶体管T41的源极输入高电位的扫描驱动信号G(N)，第一节点Q(N)也不会通过第四十一薄膜晶体管T41与第四十薄膜晶体管T40的串联路径漏电。
在非作用期间，即当第一节点Q(N)转变为低电位时，反相器F输出为高电位，即第二节点P(N)为高电位，第四十二薄膜晶体管T42、第三十二薄膜晶体管T32、及第七十六薄膜晶体管T76均导通，第一节点Q(N)通过第四十二薄膜晶体管T42与第七十六薄膜晶体管T76被进一步拉低并维持在第二恒压负电位DCL；扫描驱动信号G(N)通过第三十二薄膜晶体管T32被进一步拉低并维持在第一恒压负电位VSS。此时，由于第四十薄膜晶体管T40采用了二级体接法，即将第四十薄膜晶体管T40的栅极与源极短接，所述第四十薄膜晶体管T40的栅源极电压Vgs等于0V，相比现有技术将第四十薄膜晶体管T40的栅极连接第N+2级GOA单元电路的扫描驱动信号G(N+2)，能够避免由第二恒压负电位DCL引起的串扰电流流经该第四十薄膜晶体管T40。由于第七十五薄膜晶体管T75的漏极电性连接于第一节点Q(N)，第四十二薄膜晶体管T42的源极电性连接于第七十五薄膜晶体管T75的漏极，相比现有技术将第七十五薄膜晶体管T75的漏极电性连接于恒压高电位DCH，能够避免恒压高电位DCH在非作用期间对第一节点Q(N)下拉维持的影响。
进一步地，设置所述第二恒压负电位DCL低于第一恒压负电位VSS，以便于进行分开独立控制。当作用期间第一节点Q(N)为高电位时，所述双重反相器F的主反相器中的第五十二薄膜晶体管T52与第五十四薄膜晶体管T54均导通，第五十三薄膜晶体管T53断开，辅助主反相器中的第七十四薄膜晶体管T74导通，第七十三薄膜晶体管T73关闭，第二节点P(N)的电位被拉低到比第一恒压负电位VSS更低的第二恒压负电位DCL，确保第一节点Q(N)和扫描驱动信号G(N)稳定的输出高电位；当非作用期间第一节点Q(N)为低电位时，所述双重反相器F的主反相器中的第五十二薄膜晶体管T52与第五十四薄膜晶体管T54均断开，第五十一薄膜晶体管T51与第五十三薄膜晶体管T53均导通，辅助主反相器中的第七十四薄膜晶体管T74断开，第七十三薄膜晶体管T73导通，防止第五十四薄膜晶体管T54漏电，使得第二节点P(N)的电位保持在恒压高电位DCH，能够维持第一节点Q(N)和扫描驱动信号G(N)的低电位。
请同时参阅图3、图5、图6、与图7，为本发明基于氧化物半导体薄 膜晶体管的GOA电路的第二实施例，该第二实施例与第一实施例的区别在于，增设了一清空重置模块700。具体的，所述清空重置模块700包括一第九薄膜晶体管T9，所述第九薄膜晶体管T9的栅极接入扫描启动信号STV，漏极电性连接于第一节点Q(N)，源极电性连接于第一恒压负电位VSS。该清空重置模块700用于在每一帧画面产生前利用扫描启动信号STV对第一节点Q(N)进行清空重置，清除残余电荷对GOA电路的干扰，同时在第一帧画面产生前也可以清空第一节点Q(N)，预防第一帧画面悬空对GOA电路输出的影响，保证GOA电路的正常输出和画面的正常显示。
特别需要说明的是，设所述时钟信号共包括M组，M为4的整数倍，则当N＞M时，在第N级GOA单元电路中设置清空重置模块700。例如，图6与图7以所述时钟信号共包括四组为例，从第五级GOA单元电路开始，在第五级至最后一级GOA单元电路中均设置清空重置模块700，相应的，第五级至最后一级GOA单元电路均需接入用于控制清空重置模块700的扫描启动信号STV；而第一级至第四级GOA单元电路中均不设置清空重置模块700，仅有第一级GOA单元电路需接入用于启动扫描驱动的扫描启动信号STV。具体地，所述四组时钟信分别为:第一组时钟信号CK(1)、第二组时钟信号CK(2)、第三组时钟信号CK(3)、及第四组时钟信号CK(4)；当所述第m组时钟信号CK(m)为第三时钟信号CK(3)时，所述第m+2组时钟信号CK(m+2)为第一组时钟信号CK(1)，当所述时钟信号CK(m)为第四组时钟信号CK(4)时，所述第m+2组时钟信号CK(m+2)为第二组时钟信号CK(2)；所述四组时钟信号的波形占空比为25/75，以避免时钟信号波形对第一下拉模块400的影响，第一节点Q(N)处的波形呈“凸”字形。
同理，若所述时钟信号共包括八组，则从第九级GOA单元电路开始，在第九级至最后一级GOA单元电路中均设置清空重置模块700，相应的，第九级至最后一级GOA单元电路均需接入用于控制清空重置模块700的扫描启动信号STV；而第一级至第八级GOA单元电路中均不设置清空重置模块700，仅有第一级GOA单元电路需接入用于启动扫描驱动的扫描启动信号STV。
其余电路结构与工作过程均与第一实施例相同，此处不再赘述。
请同时参阅图4、图5、图6、与图7，为本发明基于氧化物半导体薄膜晶体管的GOA电路的第三实施例，该第三实施例与第二实施例的区别仅在于，将第九薄膜晶体管T9的源极电性连接于对应第N级GOA单元电路的第m组时钟信号CK(m)，这样做的好处是能够降低第九薄膜晶体管T9对第一节点Q(N)在作用期间的漏电影响。其余均与第二实施例相同，此处 不再赘述。
请同时参阅图8、图9、图10与图11，为本发明基于氧化物半导体薄膜晶体管的GOA电路的第四实施例，该第四实施例同样设置清空重置模块700，与第三实施例不同的是，所述清空重置模块700内第九薄膜晶体管T9的栅极接入重置信号Reset，即该第四实施例需要增加一个不同于扫描启动信号STV的重置信号Reset，且如图10所示，所述重置信号Reset在扫描启动信号STV之前产生。这种情况下，可在第一级至最后一级GOA单元电路中的每一级均设置清空重置模块700。
以所述时钟信号共包括四组为例，如图9、图11所示，第一级GOA单元电路接入用于控制清空重置模块700的重置信号Reset与用于启动扫描驱动的扫描启动信号STV；第二级至最后一级GOA单元电路中的每一级接入用于控制清空重置模块700的重置信号Reset，同样能够实现在每一帧画面产生前利用重置信号Reset对第一节点Q(N)进行清空重置，清除残余电荷对GOA电路的干扰，同时在第一帧画面产生前也可以清空第一节点Q(N)，预防第一帧画面悬空对GOA电路输出的影响，保证GOA电路的正常输出和画面的正常显示。
综上所述，本发明的基于氧化物半导体薄膜晶体管的GOA电路，不仅能够防止漏电，提高GOA电路的可靠性，还通过将第一下拉模块内的第四十薄膜晶体管的栅极与源极短接来避免GOA单元电路在非作用期间产生串扰电流，通过将下拉维持模块中第七十五薄膜晶体管的栅极与漏极均电性连接于第一节点来避免恒压高电位对第一节点下拉维持的影响，通过设置清空重置模块在每一帧画面产生前对第一节点进行清空重置，以清除残余电荷对GOA电路的干扰，保证GOA电路的正常输出和画面的正常显示。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (14)

  1. 一种基于氧化物半导体薄膜晶体管的GOA电路，包括级联的多个GOA单元电路，每一级GOA单元电路均包括：上拉控制模块、上拉模块、下传模块、第一下拉模块、自举电容模块、及下拉维持模块；
    设N为正整数，除第一级GOA单元电路以外，在第N级GOA单元电路中：
    所述上拉控制模块包括第十一薄膜晶体管，所述第十一薄膜晶体管的栅极接收上一级第N-1级GOA单元电路的级传信号，源极电性连接于恒压高电位，漏极电性连接于第一节点；
    所述上拉模块包括：第二十一薄膜晶体管，所述第二十一薄膜晶体管的栅极电性连接于第一节点，源极电性连接于对应该第N级GOA单元电路的第m组时钟信号，漏极输出扫描驱动信号；
    所述下传模块包括：第二十二薄膜晶体管，所述第二十二薄膜晶体管的栅极电性连接于第一节点，源极电性连接于对应该第N级GOA单元电路的第m组时钟信号，漏极输出级传信号；
    所述第一下拉模块包括第四十薄膜晶体管、与第四十一薄膜晶体管；所述第四十薄膜晶体管的栅极与源极均电性连接于第一节点，漏极电性连接于第四十一薄膜晶体管的漏极；所述第四十一薄膜晶体管的栅极输入对应于下两极第N+2级GOA单元电路的第m+2组时钟信号，源极输入扫描驱动信号；
    所述自举电容模块包括电容，所述电容的一端电性连接于第一节点，另一端电性连接于扫描驱动信号；
    所述下拉维持模块包括：一由多个薄膜晶体管构成的双重反相器、第四十二薄膜晶体管、第三十二薄膜晶体管、第七十五薄膜晶体管、与第七十六薄膜晶体管；所述双重反相器的输入端电性连接于第一节点，输出端电性连接于第二节点；所述第四十二薄膜晶体管的栅极电性连接于第二节点，漏极电性连接于第一节点，源极电性连接于第三节点；所述第三十二薄膜晶体管的栅极电性连接于第二节点，漏极电性连接于扫描驱动信号，源极电性连接于第一恒压负电位；所述第七十五薄膜晶体管的栅极与漏极均电性连接于第一节点，源极电性连接于第三节点；所述第七十六薄膜晶体管的栅极电性连接于第二节点，漏极电性连接于第三节点，源极电性连接于第二恒压负电位；
    所述第二恒压负电位低于第一恒压负电位；
    各个薄膜晶体管均为氧化物半导体薄膜晶体管。
  2. 如权利要求1所述的基于氧化物半导体薄膜晶体管的GOA电路，还包括一清空重置模块，用于在每一帧画面产生前对第一节点进行清空重置。
  3. 如权利要求2所述的基于氧化物半导体薄膜晶体管的GOA电路，其中，所述清空重置模块包括一第九薄膜晶体管，所述第九薄膜晶体管的栅极接入扫描启动信号，漏极电性连接于第一节点，源极电性连接于第一恒压负电位。
  4. 如权利要求2所述的基于氧化物半导体薄膜晶体管的GOA电路，其中，所述清空重置模块包括一第九薄膜晶体管，所述第九薄膜晶体管的栅极接入扫描启动信号，漏极电性连接于第一节点，源极电性连接于对应第N级GOA单元电路的第m组时钟信号。
  5. 如权利要求2所述的基于氧化物半导体薄膜晶体管的GOA电路，其中，所述清空重置模块包括一第九薄膜晶体管，所述第九薄膜晶体管的栅极接入重置信号，漏极电性连接于第一节点，源极电性连接于对应第N级GOA单元电路的第m组时钟信号；所述重置信号在扫描启动信号之前产生。
  6. 如权利要求3所述的基于氧化物半导体薄膜晶体管的GOA电路，其中，设所述时钟信号共包括M组，M为4的整数倍，则当N＞M时，在第N级GOA单元电路中设置清空重置模块。
  7. 如权利要求4所述的基于氧化物半导体薄膜晶体管的GOA电路，其中，设所述时钟信号共包括M组，M为4的整数倍，则当N＞M时，在第N级GOA单元电路中设置清空重置模块。
  8. 如权利要求5所述的基于氧化物半导体薄膜晶体管的GOA电路，其中，在每一级GOA单元电路中均设置清空重置模块。
  9. 如权利要求6所述的基于氧化物半导体薄膜晶体管的GOA电路，其中，所述时钟信号共包括四组:第一组时钟信号、第二组时钟信号、第三组时钟信号、及第四组时钟信号；当所述第m组时钟信号为第三时钟信号时，所述第m+2组时钟信号为第一组时钟信号，当所述时钟信号为第四组时钟信号时，所述第m+2组时钟信号为第二组时钟信号；所述四组时钟信号的波形占空比为25/75；
    在第五级至最后一级GOA单元电路中设置清空重置模块。
  10. 如权利要求7所述的基于氧化物半导体薄膜晶体管的GOA电路， 其中，所述时钟信号共包括四组:第一组时钟信号、第二组时钟信号、第三组时钟信号、及第四组时钟信号；当所述第m组时钟信号为第三时钟信号时，所述第m+2组时钟信号为第一组时钟信号，当所述时钟信号为第四组时钟信号时，所述第m+2组时钟信号为第二组时钟信号；所述四组时钟信号的波形占空比为25/75；
    在第五级至最后一级GOA单元电路中设置清空重置模块。
  11. 如权利要求1所述的基于氧化物半导体薄膜晶体管的GOA电路，其中，所述双重反相器包括：第五十一薄膜晶体管，所述第五十一薄膜晶体管的栅极与源极均电性连接于恒压高电位，漏极电性连接于第四节点；第五十二薄膜晶体管，所述第五十二薄膜晶体管的栅极电性连接于第一节点，漏极电性连接于第四节点，源极电性连接于第一恒压负电位；第五十三薄膜晶体管，所述第五十三薄膜晶体管的栅极电性连接于第四节点，源极电性连接于恒压高电位，漏极电性连接于第二节点；第五十四薄膜晶体管，所述第五十四薄膜晶体管的栅极电性连接于第一节点，漏极电性连接于第二节点，源极电性连接于第五节点；第七十三薄膜晶体管，所述第七十三薄膜晶体管的栅极电性连接于第四节点，源极电性连接于恒压高电位，漏极电性连接于第五节点；第七十四薄膜晶体管，所述第七十四薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二恒压负电位，漏极电性连接于第五节点；其中所述第五十一薄膜晶体管、第五十二薄膜晶体管、第五十三薄膜晶体管、与第五十四薄膜晶体管构成主反相器，所述第七十三薄膜晶体管、与第七十四薄膜晶体管构成辅助反相器。
  12. 如权利要求1所述的基于氧化物半导体薄膜晶体管的GOA电路，其中，在第一级GOA单元电路中，所述第十一薄膜晶体管的栅极接入扫描启动信号。
  13. 一种基于氧化物半导体薄膜晶体管的GOA电路，包括级联的多个GOA单元电路，每一级GOA单元电路均包括：上拉控制模块、上拉模块、下传模块、第一下拉模块、自举电容模块、及下拉维持模块；
    设N为正整数，除第一级GOA单元电路以外，在第N级GOA单元电路中：
    所述上拉控制模块包括第十一薄膜晶体管，所述第十一薄膜晶体管的栅极接收上一级第N-1级GOA单元电路的级传信号，源极电性连接于恒压高电位，漏极电性连接于第一节点；
    所述上拉模块包括：第二十一薄膜晶体管，所述第二十一薄膜晶体管的栅极电性连接于第一节点，源极电性连接于对应该第N级GOA单元电路 的第m组时钟信号，漏极输出扫描驱动信号；
    所述下传模块包括：第二十二薄膜晶体管，所述第二十二薄膜晶体管的栅极电性连接于第一节点，源极电性连接于对应该第N级GOA单元电路的第m组时钟信号，漏极输出级传信号；
    所述第一下拉模块包括第四十薄膜晶体管、与第四十一薄膜晶体管；所述第四十薄膜晶体管的栅极与源极均电性连接于第一节点，漏极电性连接于第四十一薄膜晶体管的漏极；所述第四十一薄膜晶体管的栅极输入对应于下两极第N+2级GOA单元电路的第m+2组时钟信号，源极输入扫描驱动信号；
    所述自举电容模块包括电容，所述电容的一端电性连接于第一节点，另一端电性连接于扫描驱动信号；
    所述下拉维持模块包括：一由多个薄膜晶体管构成的双重反相器、第四十二薄膜晶体管、第三十二薄膜晶体管、第七十五薄膜晶体管、与第七十六薄膜晶体管；所述双重反相器的输入端电性连接于第一节点，输出端电性连接于第二节点；所述第四十二薄膜晶体管的栅极电性连接于第二节点，漏极电性连接于第一节点，源极电性连接于第三节点；所述第三十二薄膜晶体管的栅极电性连接于第二节点，漏极电性连接于扫描驱动信号，源极电性连接于第一恒压负电位；所述第七十五薄膜晶体管的栅极与漏极均电性连接于第一节点，源极电性连接于第三节点；所述第七十六薄膜晶体管的栅极电性连接于第二节点，漏极电性连接于第三节点，源极电性连接于第二恒压负电位；
    所述第二恒压负电位低于第一恒压负电位；
    各个薄膜晶体管均为氧化物半导体薄膜晶体管；
    还包括一清空重置模块，用于在每一帧画面产生前对第一节点进行清空重置；
    其中，所述双重反相器包括：第五十一薄膜晶体管，所述第五十一薄膜晶体管的栅极与源极均电性连接于恒压高电位，漏极电性连接于第四节点；第五十二薄膜晶体管，所述第五十二薄膜晶体管的栅极电性连接于第一节点，漏极电性连接于第四节点，源极电性连接于第一恒压负电位；第五十三薄膜晶体管，所述第五十三薄膜晶体管的栅极电性连接于第四节点，源极电性连接于恒压高电位，漏极电性连接于第二节点；第五十四薄膜晶体管，所述第五十四薄膜晶体管的栅极电性连接于第一节点，漏极电性连接于第二节点，源极电性连接于第五节点；第七十三薄膜晶体管，所述第七十三薄膜晶体管的栅极电性连接于第四节点，源极电性连接于恒压高电 位，漏极电性连接于第五节点；第七十四薄膜晶体管，所述第七十四薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二恒压负电位，漏极电性连接于第五节点；其中所述第五十一薄膜晶体管、第五十二薄膜晶体管、第五十三薄膜晶体管、与第五十四薄膜晶体管构成主反相器，所述第七十三薄膜晶体管、与第七十四薄膜晶体管构成辅助反相器；
    其中，在第一级GOA单元电路中，所述第十一薄膜晶体管的栅极接入扫描启动信号；
    其中，所述清空重置模块包括一第九薄膜晶体管，所述第九薄膜晶体管的栅极接入重置信号，漏极电性连接于第一节点，源极电性连接于对应第N级GOA单元电路的第m组时钟信号；所述重置信号在扫描启动信号之前产生。
  14. 如权利要求13所述的基于氧化物半导体薄膜晶体管的GOA电路，其中，在每一级GOA单元电路中均设置清空重置模块。
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