KR910019258A - 반도체장치 및 그 제조방법 - Google Patents

반도체장치 및 그 제조방법 Download PDF

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KR910019258A
KR910019258A KR1019900021169A KR900021169A KR910019258A KR 910019258 A KR910019258 A KR 910019258A KR 1019900021169 A KR1019900021169 A KR 1019900021169A KR 900021169 A KR900021169 A KR 900021169A KR 910019258 A KR910019258 A KR 910019258A
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isolation insulating
insulating layer
semiconductor
semiconductor layer
active region
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KR1019900021169A
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KR940008221B1 (ko
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도시노리 모리하라
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시기 모리야
미쓰비시 뎅끼 가부시끼가이샤
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66651—Lateral single gate silicon transistors with a single crystalline channel formed on the silicon substrate after insulating device isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
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    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76248—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using lateral overgrowth techniques, i.e. ELO techniques
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions

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  • Manufacturing & Machinery (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
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  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

내용 없음

Description

반도체장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명의 한 실시예에 있어서의 반도체장치의 구조를 모식적으로 표시하는 단면도, 제 2A내지 제 2F도는 본 발명의 한 실시예에 있어서의 반도체 장치의 제조공정을 순차모식적으로 표시하는 단면도, 제 3A도 내지 제 3C도는 각각 본 실시예에 있어서의 효과를 설명하기 위한 도면이며, 그 중 제 3A도는 본 실시예의 반도체장치를 그 게이트부(10)를 횡단하는 단면으로 절단한 단면도, 제 3B는 게이트부(10)에 대략 평행이고 또한 게이트부(10)를 포함하지 않는 연직면(鉛直面)으로 절단한 단면도, 제 3C도는 활성영역에 패드(29)를 형성한 경우의 단면도.

Claims (2)

  1. 반도체기판의 주면상에 있어서, 활성영역을 포위하고 전둘레에 걸쳐서 거의 균일한 높이로 형성되고, 이 활성영역을 다른것과 분리절연하는 소자분리 절연층과, 상기 소자분리절연층에서 포위된 활성영역전역에 상기 소자 분리절연층과 단차가 생기지 않도록 상기 소자분리절연층과 거의 동일한 높이로 평탄하게 형성된 반도체층과를 구비하고 이 반도체층의 표면을 소자형성영역으로 한 것을 특징으로 하는 반도체장치.
  2. 반도체기판의 주면상의 소정위치에 활성영역을 포위하여 다른것과 분리절연하는 소자분리절연층을 선택적으로 패터닝 형성하는 공정과, 상기 소자분리절연층을 형성한 후에 상기 반도체기판의 주면상 전역에 반도체층을 형성하는 공정과, 상기 반도체층 표면전역애 레지스트막을 거의 평탄하게 되도록 도포하는 공정과, 상기 반도체층과 상기 레지스트막을 거의 동일한 선택비를 에칭하는 것에 의하여 상기 소자분리 절연층을 전둘레에 걸쳐서 노출시키는 것과 아울러 상기 반도체층을 상기 소자분리절연층과 단차가 생기지 않는 높이로 편탄하게 하는 공정과 상기 반도체층표면에 소자를 형성하는 공정과를 구비한 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원내용에 의하여 공개하는 것임.
KR1019900021169A 1990-04-13 1990-12-20 반도체장치 및 그 제조방법 KR940008221B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2-98949 1990-04-13
JP2098949A JPH03296247A (ja) 1990-04-13 1990-04-13 半導体装置およびその製造方法

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KR910019258A true KR910019258A (ko) 1991-11-30
KR940008221B1 KR940008221B1 (ko) 1994-09-08

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US (1) US5378644A (ko)
JP (1) JPH03296247A (ko)
KR (1) KR940008221B1 (ko)
DE (1) DE4112045C2 (ko)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2979731B2 (ja) * 1991-06-26 1999-11-15 日本電気株式会社 半導体装置
US6064077A (en) 1991-08-30 2000-05-16 Stmicroelectronics, Inc. Integrated circuit transistor
JPH05183159A (ja) * 1992-01-07 1993-07-23 Fujitsu Ltd 半導体装置及びその製造方法
JP2658959B2 (ja) * 1995-03-31 1997-09-30 日本電気株式会社 半導体装置およびその製造方法
KR970053015A (ko) * 1995-12-07 1997-07-29 김주용 반도체 소자의 트랜지스터 제조방법
JP2751905B2 (ja) * 1995-12-30 1998-05-18 日本電気株式会社 半導体装置およびその製造方法
DE19622276C2 (de) 1996-06-03 1998-07-09 Siemens Ag Halbleiterstruktur für einen MOS-Transistor und Verfahren zur Herstellung der Halbleiterstruktur
US6617226B1 (en) 1999-06-30 2003-09-09 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
KR100578787B1 (ko) * 2004-06-12 2006-05-11 삼성전자주식회사 반도체 장치 및 그 제조 방법
US7566602B2 (en) * 2004-06-12 2009-07-28 Samsung Electronics Co., Ltd. Methods of forming single crystalline layers and methods of manufacturing semiconductor devices having such layers
GB2439357C (en) * 2006-02-23 2008-08-13 Innos Ltd Integrated circuit manufacturing

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4378627A (en) * 1980-07-08 1983-04-05 International Business Machines Corporation Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes
JPS5768049A (en) * 1980-10-15 1982-04-26 Fujitsu Ltd Semiconductor device and manufacture thereof
DE3467953D1 (en) * 1983-04-21 1988-01-14 Toshiba Kk Semiconductor device having an element isolation layer and method of manufacturing the same
DE3478170D1 (en) * 1983-07-15 1989-06-15 Toshiba Kk A c-mos device and process for manufacturing the same
JPS61164262A (ja) * 1985-01-17 1986-07-24 Toshiba Corp 半導体装置
KR900007686B1 (ko) * 1986-10-08 1990-10-18 후지쓰 가부시끼가이샤 선택적으로 산화된 실리콘 기판상에 에피택셜 실리콘층과 다결정 실리콘층을 동시에 성장시키는 기상 증착방법
JPS63108709A (ja) * 1986-10-25 1988-05-13 Toyota Central Res & Dev Lab Inc 半導体装置およびその製造方法
US5086011A (en) * 1987-01-27 1992-02-04 Advanced Micro Devices, Inc. Process for producing thin single crystal silicon islands on insulator
JPS63224218A (ja) * 1987-03-13 1988-09-19 Nec Corp シリコン単結晶膜の改善方法
JPS6433920A (en) * 1987-07-30 1989-02-03 Nec Corp Growth method of semiconductor film
JP2643262B2 (ja) * 1988-03-23 1997-08-20 日本電気株式会社 半導体装置の製造方法
US4923824A (en) * 1988-04-27 1990-05-08 Vtc Incorporated Simplified method of fabricating lightly doped drain insulated gate field effect transistors
FR2631488B1 (fr) * 1988-05-10 1990-07-27 Thomson Hybrides Microondes Circuit integre hyperfrequence de type planar, comportant au moins un composant mesa, et son procede de fabrication
JP2507557B2 (ja) * 1988-09-29 1996-06-12 三菱電機株式会社 半導体装置の製造方法
KR940021169A (ko) * 1993-03-15 1994-10-17 윤종용 용융 땜납(Solder)의 산화방지방법

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JPH03296247A (ja) 1991-12-26
DE4112045A1 (de) 1991-10-17
US5378644A (en) 1995-01-03
DE4112045C2 (de) 1994-03-10
KR940008221B1 (ko) 1994-09-08

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