JP2015510696A - Mosfet終端トレンチ - Google Patents
Mosfet終端トレンチ Download PDFInfo
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 50
- 229920005591 polysilicon Polymers 0.000 claims abstract description 50
- 238000000034 method Methods 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 239000004065 semiconductor Substances 0.000 claims description 108
- 238000000151 deposition Methods 0.000 claims description 17
- 239000003989 dielectric material Substances 0.000 claims description 10
- 238000007517 polishing process Methods 0.000 claims description 9
- 239000004020 conductor Substances 0.000 description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- 238000004519 manufacturing process Methods 0.000 description 16
- 230000015556 catabolic process Effects 0.000 description 10
- 235000012239 silicon dioxide Nutrition 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 8
- 230000005684 electric field Effects 0.000 description 7
- 230000003247 decreasing effect Effects 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 230000000903 blocking effect Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000004807 localization Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
Description
Tox=BV/Emax
ここで、Toxは終端トレンチライナ酸化物の厚みであり、BVはMOSFET阻止電圧であり、Emaxは最大酸化物電界である。さらに、一実施形態において、強反転限界2002に基づいた酸化物の厚みは、以下の関係式で与えられる。
Tox=εox*(BV−2*φf)/(sqrt(2*εs*q*Nd*2*φf))
ここで、Toxは終端トレンチライナ酸化物の厚み、BVはMOSFET阻止電圧、Emaxは最大酸化物電界、εoxは酸化物の誘電率、εsはシリコンの誘電率、Ndはピークエピタキシャルドーピング、φfはバルク電位である。一実施形態において、終端トレンチ酸化物の厚みを選択するために使用される実際の基準は、終端のデザインに応じたものでありえ、基準の一方または両方を用いたものであってもよいことが指摘される。
基板にコアトレンチおよび終端トレンチを形成するステップであって、前記終端トレンチは前記コアトレンチより幅が広い形成ステップと、
前記コアトレンチを充填し、前記終端トレンチの側壁および底部をライニングする第1の酸化物を堆積するステップと、
前記終端トレンチ内に第1のポリシリコンを堆積するステップと、
前記第1のポリシリコンの上方に第2の酸化物を堆積するステップと、
前記第2の酸化物および前記終端トレンチの上方にマスクを堆積するステップと、
前記コアトレンチから前記第1の酸化物を除去するステップと、
前記コアトレンチの側壁および底部をライニングする第3の酸化物を堆積するステップであって、前記終端トレンチ内の前記第1の酸化物は、前記コアトレンチ内の前記第3の酸化物より厚い堆積ステップと、
を備えた方法。
概念2
前記終端トレンチは、前記コアトレンチのおよそ2倍である、概念1に記載の方法。
概念3
前記終端トレンチ内の前記第1の酸化物は、前記コアトレンチ内の前記第3の酸化物のおよそ2倍の厚みである、概念1又は2に記載の方法。
概念4
マスクの前記堆積ステップ前に、前記第2の酸化物を平坦化するために酸化物研磨プロセスを実行するステップをさらに含む、概念1乃至3のいずれか1つに記載の方法。
概念5
前記コアトレンチ内に第2のポリシリコンを堆積するステップをさらに含む、概念1乃至4のいずれか1つに記載の方法。
概念6
前記第1および第2のポリシリコンの上方に第4の酸化物層を堆積するステップをさらに含む、概念5に記載の方法。
概念7
半導体デバイスであって、
基板に形成された終端トレンチを備え、
前記終端トレンチは、
前記終端トレンチの側壁および底部をライニングする第1の酸化物と、
前記第1の酸化物間に位置する第1のポリシリコンと、を含み、
前記基板に形成されたコアトレンチを備え、
前記コアトレンチは、
前記コアトレンチの側壁および底部をライニングする第2の酸化物と、
前記第2の酸化物の間に位置する第2のポリシリコンと、を含み、
前記終端トレンチの幅は、前記コアトレンチより広い、半導体デバイス。
概念8
前記終端トレンチの幅は、前記コアトレンチのおよそ2倍である、概念7に記載の半導体デバイス。
概念9
前記終端トレンチ内の前記第1の酸化物の厚みは、前記コアトレンチ内の前記第2の酸化物の厚みのおよそ2倍である、概念7又は8のいずれかに記載の半導体デバイス。
概念10
前記コアトレンチおよび前記終端トレンチは、前記基板のメサによって分離され、前記メサは、電圧接地に接続されたドープ領域を備える、概念7、8又は9に記載の半導体デバイス。
概念11
前記コアトレンチは、
前記第2の酸化物間に位置する第3のポリシリコンと、
前記第2のポリシリコンと前記第3のポリシリコンとの間に位置する誘電体材料と、
をさらに備える、概念7−10のいずれか1つに記載の半導体デバイス。
概念12
前記基板に形成されるゲートコアトレンチをさらに備え、前記ゲートコアトレンチは、前記コアトレンチの半分未満の深さである、概念7−11のいずれか1つに記載の半導体デバイス。
概念13
前記第1の酸化物および前記第2の酸化物と接触状態にある第3の酸化物を備える、概念7に記載の半導体デバイス。
Claims (15)
- 基板にコアトレンチおよび終端トレンチを形成するステップであって、前記終端トレンチは前記コアトレンチより幅が広い形成ステップと、
前記コアトレンチを充填し、前記終端トレンチの側壁および底部をライニングする第1の酸化物を堆積するステップと、
前記終端トレンチ内に第1のポリシリコンを堆積するステップと、
前記第1のポリシリコンの上方に第2の酸化物を堆積するステップと、
前記第2の酸化物および前記終端トレンチの上方にマスクを堆積するステップと、
前記コアトレンチから前記第1の酸化物を除去するステップと、
前記コアトレンチの側壁および底部をライニングする第3の酸化物を堆積するステップであって、前記終端トレンチ内の前記第1の酸化物は、前記コアトレンチ内の前記第3の酸化物より厚い堆積ステップと、
を備えた方法。 - 前記終端トレンチは、前記コアトレンチのおよそ2倍である、請求項1に記載の方法。
- 前記終端トレンチ内の前記第1の酸化物は、前記コアトレンチ内の前記第3の酸化物のおよそ2倍の厚みである、請求項2に記載の方法。
- 前記終端トレンチ内の前記第1の酸化物は、前記コアトレンチ内の前記第3の酸化物のおよそ2倍の厚みである、請求項1に記載の方法。
- マスクの前記堆積ステップ前に、前記第2の酸化物を平坦化するために酸化物研磨プロセスを実行するステップをさらに含む、請求項1に記載の方法。
- 前記コアトレンチ内に第2のポリシリコンを堆積するステップをさらに含む、請求項1に記載の方法。
- 前記第1および第2のポリシリコンの上方に第4の酸化物層を堆積するステップをさらに含む、請求項6に記載の方法。
- 半導体デバイスであって、
基板に形成された終端トレンチを備え、
前記終端トレンチは、
前記終端トレンチの側壁および底部をライニングする第1の酸化物と、
前記第1の酸化物間に位置する第1のポリシリコンと、を含み、
前記基板に形成されたコアトレンチを備え、
前記コアトレンチは、
前記コアトレンチの側壁および底部をライニングする第2の酸化物と、
前記第2の酸化物の間に位置する第2のポリシリコンと、を含み、
前記終端トレンチの幅は、前記コアトレンチより広い、半導体デバイス。 - 前記終端トレンチの幅は、前記コアトレンチのおよそ2倍である、請求項8に記載の半導体デバイス。
- 前記終端トレンチ内の前記第1の酸化物の厚みは、前記コアトレンチ内の前記第2の酸化物の厚みのおよそ2倍である、請求項9に記載の半導体デバイス。
- 前記終端トレンチ内の前記第1の酸化物の厚みは、前記コアトレンチ内の前記第2の酸化物の厚みのおよそ2倍である、請求項8に記載の半導体デバイス。
- 前記コアトレンチおよび前記終端トレンチは、前記基板のメサによって分離され、前記メサは、電圧接地に接続されたドープ領域を備える、請求項8に記載の半導体デバイス。
- 前記コアトレンチは、
前記第2の酸化物間に位置する第3のポリシリコンと、
前記第2のポリシリコンと前記第3のポリシリコンとの間に位置する誘電体材料と、
をさらに備える、請求項8に記載の半導体デバイス。 - 前記基板に形成されるゲートコアトレンチをさらに備え、前記ゲートコアトレンチは、前記コアトレンチの半分未満の深さである、請求項8に記載の半導体デバイス。
- 前記第1の酸化物および前記第2の酸化物と接触状態にある第3の酸化物を備える、請求項8に記載の半導体デバイス。
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US9614043B2 (en) | 2017-04-04 |
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