JP6231377B2 - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
- Publication number
- JP6231377B2 JP6231377B2 JP2013267788A JP2013267788A JP6231377B2 JP 6231377 B2 JP6231377 B2 JP 6231377B2 JP 2013267788 A JP2013267788 A JP 2013267788A JP 2013267788 A JP2013267788 A JP 2013267788A JP 6231377 B2 JP6231377 B2 JP 6231377B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- trench
- gate
- insulating
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 112
- 238000004519 manufacturing process Methods 0.000 title claims description 38
- 239000000758 substrate Substances 0.000 claims description 47
- 238000000151 deposition Methods 0.000 claims description 16
- 238000010438 heat treatment Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 10
- 239000010410 layer Substances 0.000 description 213
- 238000005229 chemical vapour deposition Methods 0.000 description 18
- 239000011810 insulating material Substances 0.000 description 17
- 239000011229 interlayer Substances 0.000 description 15
- 238000005192 partition Methods 0.000 description 7
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000002994 raw material Substances 0.000 description 3
- 210000000746 body region Anatomy 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- MXSJNBRAMXILSE-UHFFFAOYSA-N [Si].[P].[B] Chemical compound [Si].[P].[B] MXSJNBRAMXILSE-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/408—Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Formation Of Insulating Films (AREA)
- Electrodes Of Semiconductors (AREA)
Description
(半導体装置100の構造)
図1に示すように、本実施例の半導体装置100は、半導体基板10中に、電流が流れる素子領域110と、その素子領域110を取り囲む終端領域120とを有している。本実施例の半導体装置100は、パワーMOSFETである。
次いで、本実施例の半導体装置100の製造方法を説明する。まず、図4に示すように、複数のゲートトレンチ20と、複数の終端トレンチ30とが形成された半導体基板10を準備する。本実施例では、半導体基板10はSiCによって形成されている。なお、図4では、ゲートトレンチ20は1本のみを図示している。図4の時点で、各ゲートトレンチ20の下端部には、フローティング領域26が形成されている。また、各終端トレンチ30の下端部には、フローティング領域36が形成されている。また、半導体基板10には、ドリフト領域12、ボディ領域13、及び、ソース領域11が形成されている。
続いて、図10を参照して、第2実施例の半導体装置200について、第1実施例と異なる点を中心に説明する。本実施例の半導体装置200は、その基本的構成は第1実施例の半導体装置100(図2参照)と共通する。図10では、第1実施例の半導体装置100と共通する要素については同じ符号を用いて示している。
半導体装置200の製造方法も、基本的には第1実施例の製造方法と同様である。ただし、本実施例では、第1の絶縁層32の上面に第2の絶縁層34を堆積させた後に(図6参照)、第2の絶縁層34の上面に第3の絶縁層238を堆積させる工程を実行する。第3の絶縁層238は、第1の絶縁層32及び第2の絶縁層34と同様に、TEOSを原料とするCVDを行うことによって形成される。第3の絶縁層238を形成する際には、第2の絶縁層34を形成する場合よりも低い圧力の下でCVDを実行する。これにより、第2の絶縁層34の上面に、密な絶縁層である第3の絶縁層238を形成することができる。低い圧力の下でのCVDでは絶縁材料の埋め込み性が悪いが、第3の絶縁層238は平坦な表面上に形成されるので、埋め込み性は問題とならない。
12:ドリフト領域
14:ドレイン領域
18:ドレイン電極
20:ゲートトレンチ
22:ゲート絶縁膜
24:ゲート電極
26:フローティング領域
28:隔壁
30:終端トレンチ
31:隔壁
32、32a、32b:第1の絶縁層
34、34a、34b:第2の絶縁層
36:フローティング領域
40:層間絶縁膜
42:コンタクトホール
44:ゲート配線
100:半導体装置
110:素子領域
120:終端領域
200:半導体装置
238:第3の絶縁層
Claims (2)
- 素子領域と、前記素子領域を取り囲む終端領域が形成されている半導体基板を有しており、
前記素子領域は、
前記半導体基板の表面に形成されているゲートトレンチと、
前記ゲートトレンチの内面を覆うゲート絶縁膜と、
前記ゲート絶縁膜の内側に設けられているゲート電極、
を有しており、
前記終端領域は、
前記半導体基板の表面に形成されている終端トレンチと、
前記終端トレンチの内面全体と前記終端領域内の前記半導体基板の上面を覆う第1の絶縁層と、
前記終端トレンチ内の前記第1の絶縁層の表面に配置されているとともに、前記終端トレンチ内に充填され、かつ、前記終端領域内の前記半導体基板の上面に形成された前記第1の絶縁層の上面に形成されている、第2の絶縁層と、
前記第2の絶縁層の上面に形成されている第3の絶縁層と、
前記第3の絶縁層の上方に配置され、前記ゲート電極と電気的に接続されているゲート配線、
を有しており、
前記第1の絶縁層の屈折率は、前記第2の絶縁層の屈折率よりも大きく、かつ、
前記第3の絶縁層の屈折率は、前記第2の絶縁層の屈折率よりも大きい、
半導体装置。 - ゲートトレンチと前記ゲートトレンチを取り囲む終端トレンチを有する半導体基板の前記ゲートトレンチの内部と前記終端トレンチの内部と前記半導体基板の上面に、第1の圧力の下で第1の絶縁層を堆積する工程と、
前記第1の絶縁層が堆積された後に、前記ゲートトレンチの内部と前記終端トレンチの内部と前記半導体基板の上面に堆積された前記第1の絶縁層の上面に、前記第1の圧力より高い第2の圧力の下で、第2の絶縁層を堆積する工程と、
前記第2の絶縁層の上面に前記第2の圧力より低い第3の圧力で第3の絶縁層を堆積する工程と、
前記ゲートトレンチが形成されている範囲内の前記半導体基板の上面の前記第1、第2及び第3の絶縁層と、前記ゲートトレンチ内の前記第1及び前記第2の絶縁層の一部とを除去する工程と、
前記除去が行われた後で、前記半導体基板を熱処理する工程と、
前記熱処理の後で、前記ゲートトレンチの内面を覆うゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜の内側にゲート電極を形成する工程と、
前記第3の絶縁層の上方に、前記ゲート電極と電気的に接続されるようにゲート配線を形成する工程、
を有する半導体装置の製造方法。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013267788A JP6231377B2 (ja) | 2013-12-25 | 2013-12-25 | 半導体装置及び半導体装置の製造方法 |
US15/105,278 US9941366B2 (en) | 2013-12-25 | 2014-10-14 | Semiconductor device and manufacturing method of semiconductor device |
DE112014005992.7T DE112014005992B4 (de) | 2013-12-25 | 2014-10-14 | Halbleitervorrichtung und Herstellungsverfahren einer Halbleitervorrichtung |
PCT/JP2014/077320 WO2015098244A1 (ja) | 2013-12-25 | 2014-10-14 | 半導体装置及び半導体装置の製造方法 |
CN201480071043.7A CN105874576B (zh) | 2013-12-25 | 2014-10-14 | 半导体装置及半导体装置的制造方法 |
TW103138545A TW201526237A (zh) | 2013-12-25 | 2014-11-06 | 半導體裝置及半導體裝置的製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013267788A JP6231377B2 (ja) | 2013-12-25 | 2013-12-25 | 半導体装置及び半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2015126027A JP2015126027A (ja) | 2015-07-06 |
JP6231377B2 true JP6231377B2 (ja) | 2017-11-15 |
Family
ID=53478123
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013267788A Expired - Fee Related JP6231377B2 (ja) | 2013-12-25 | 2013-12-25 | 半導体装置及び半導体装置の製造方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US9941366B2 (ja) |
JP (1) | JP6231377B2 (ja) |
CN (1) | CN105874576B (ja) |
DE (1) | DE112014005992B4 (ja) |
TW (1) | TW201526237A (ja) |
WO (1) | WO2015098244A1 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6221922B2 (ja) | 2014-04-25 | 2017-11-01 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
JP6862321B2 (ja) * | 2017-09-14 | 2021-04-21 | 株式会社東芝 | 半導体装置 |
JP2020047729A (ja) * | 2018-09-18 | 2020-03-26 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
CN113039649B (zh) * | 2018-11-19 | 2024-07-02 | 三菱电机株式会社 | 半导体装置 |
CN112349737B (zh) * | 2020-10-27 | 2024-03-22 | 武汉新芯集成电路制造有限公司 | 半导体器件及其形成方法、图像传感器 |
JP7437568B1 (ja) | 2022-12-19 | 2024-02-22 | 新電元工業株式会社 | 半導体装置 |
WO2024134916A1 (ja) * | 2022-12-19 | 2024-06-27 | 新電元工業株式会社 | 半導体装置 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0878407A (ja) * | 1994-09-05 | 1996-03-22 | Toshiba Corp | 薄膜の形成方法 |
US6180490B1 (en) | 1999-05-25 | 2001-01-30 | Chartered Semiconductor Manufacturing Ltd. | Method of filling shallow trenches |
US6291331B1 (en) | 1999-10-04 | 2001-09-18 | Taiwan Semiconductor Manufacturing Company | Re-deposition high compressive stress PECVD oxide film after IMD CMP process to solve more than 5 metal stack via process IMD crack issue |
US7291884B2 (en) * | 2001-07-03 | 2007-11-06 | Siliconix Incorporated | Trench MIS device having implanted drain-drift region and thick bottom oxide |
JP4500598B2 (ja) * | 2004-06-24 | 2010-07-14 | トヨタ自動車株式会社 | 絶縁ゲート型半導体装置の製造方法 |
JP4447474B2 (ja) * | 2005-01-20 | 2010-04-07 | トヨタ自動車株式会社 | 半導体装置およびその製造方法 |
JP4735235B2 (ja) * | 2005-12-19 | 2011-07-27 | トヨタ自動車株式会社 | 絶縁ゲート型半導体装置およびその製造方法 |
JP4847360B2 (ja) * | 2006-02-02 | 2011-12-28 | キヤノン株式会社 | 液体吐出ヘッド基体、その基体を用いた液体吐出ヘッドおよびそれらの製造方法 |
JP5100329B2 (ja) * | 2007-11-22 | 2012-12-19 | 三菱電機株式会社 | 半導体装置 |
JP2011171500A (ja) | 2010-02-18 | 2011-09-01 | Elpida Memory Inc | 半導体装置及びその製造方法 |
JP2011216651A (ja) | 2010-03-31 | 2011-10-27 | Renesas Electronics Corp | 半導体装置の製造方法 |
US9082812B2 (en) | 2011-03-16 | 2015-07-14 | Fuji Electric Co., Ltd. | Semiconductor device including a counter layer, for power conversion and method of manufacturing the same |
US20130087852A1 (en) * | 2011-10-06 | 2013-04-11 | Suku Kim | Edge termination structure for power semiconductor devices |
US9614043B2 (en) * | 2012-02-09 | 2017-04-04 | Vishay-Siliconix | MOSFET termination trench |
-
2013
- 2013-12-25 JP JP2013267788A patent/JP6231377B2/ja not_active Expired - Fee Related
-
2014
- 2014-10-14 US US15/105,278 patent/US9941366B2/en active Active
- 2014-10-14 CN CN201480071043.7A patent/CN105874576B/zh active Active
- 2014-10-14 DE DE112014005992.7T patent/DE112014005992B4/de active Active
- 2014-10-14 WO PCT/JP2014/077320 patent/WO2015098244A1/ja active Application Filing
- 2014-11-06 TW TW103138545A patent/TW201526237A/zh unknown
Also Published As
Publication number | Publication date |
---|---|
CN105874576B (zh) | 2019-04-02 |
DE112014005992B4 (de) | 2018-06-14 |
CN105874576A (zh) | 2016-08-17 |
WO2015098244A1 (ja) | 2015-07-02 |
US9941366B2 (en) | 2018-04-10 |
TW201526237A (zh) | 2015-07-01 |
US20160315157A1 (en) | 2016-10-27 |
JP2015126027A (ja) | 2015-07-06 |
DE112014005992T5 (de) | 2016-09-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6231377B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
TWI593108B (zh) | 帶有保護遮罩氧化物的***柵溝槽功率金屬氧化物半導體場效應電晶體 | |
TWI542009B (zh) | 用於功率mosfet應用的端接溝槽及其製備方法 | |
JP2017162909A (ja) | 半導体装置 | |
CN110301037A (zh) | 三维存储器结构及其制造方法 | |
JP2014033053A (ja) | 半導体装置及びその製造方法 | |
CN107004700A (zh) | 半导体装置及其制造方法 | |
TW201607032A (zh) | 半導體裝置 | |
JP2015153789A (ja) | SiC基板を利用する半導体装置とその製造方法 | |
TW201719894A (zh) | 具有底部閘極之金氧半場效電晶體功率元件及其製作方法 | |
JP6160477B2 (ja) | 半導体装置 | |
JP2010161240A (ja) | 半導体装置 | |
WO2014128914A1 (ja) | 半導体装置 | |
JP2016134546A (ja) | 半導体装置と、その製造方法 | |
JP2015153783A (ja) | 半導体装置と半導体装置の製造方法 | |
CN106935645B (zh) | 具有底部栅极的金氧半场效晶体管功率元件 | |
JP2011204927A5 (ja) | ||
JP2016111084A (ja) | 半導体装置とその製造方法 | |
TW202337026A (zh) | 半導體結構以及埋入式場板結構的製造方法 | |
JP5502468B2 (ja) | 半導体装置の製造方法および半導体装置 | |
CN210272375U (zh) | 具有截止环结构的功率半导体器件 | |
JP6267102B2 (ja) | 半導体装置および半導体装置の製造方法 | |
CN110544725B (zh) | 具有截止环结构的功率半导体器件及其制作方法 | |
JP2009026809A (ja) | 半導体装置とその製造方法 | |
CN102222619B (zh) | 半导体装置的制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20160420 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20170411 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20170524 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20170926 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20171019 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 6231377 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313117 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |