TW201438232A - 半導體功率元件及其製作方法 - Google Patents

半導體功率元件及其製作方法 Download PDF

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TW201438232A
TW201438232A TW102110729A TW102110729A TW201438232A TW 201438232 A TW201438232 A TW 201438232A TW 102110729 A TW102110729 A TW 102110729A TW 102110729 A TW102110729 A TW 102110729A TW 201438232 A TW201438232 A TW 201438232A
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epitaxial layer
region
power device
semiconductor power
conductivity type
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TW102110729A
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Yung-Fa Lin
Chia-Hao Chang
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Anpec Electronics Corp
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Priority to TW102110729A priority Critical patent/TW201438232A/zh
Priority to CN201310159523.6A priority patent/CN104078502A/zh
Priority to US13/902,850 priority patent/US8963260B2/en
Publication of TW201438232A publication Critical patent/TW201438232A/zh
Priority to US14/509,071 priority patent/US9111770B2/en

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Abstract

一種半導體功率元件的製作方法，包含有一晶胞區域，設於一半導體基底上；至少一電晶體元件，設於該晶胞區域內；一周邊耐壓區域，環繞該晶胞區域；複數個島狀的第一磊晶層，設於該周邊耐壓區域內；以及一格狀的第二磊晶層，設於該周邊耐壓區域內，環繞各該島狀磊晶層，將該複數個島狀的第一磊晶層彼此區隔開。

Description

半導體功率元件及其製作方法
本發明係有關一種半導體功率元件及其製作方法，特別是有關於一種具有超級接面(super junction)結構的半導體功率元件(例如功率電晶體)及其製作方法。
已知，在功率元件中，其基底的設計通常為P型與N型半導體交替設置，因此在基底中會存在有多個垂直於基底表面的PN接面，且該些PN接面互相平行，又稱為超級接面結構，此種結構具有耐壓低阻抗之優點。
然而，利用上述超級接面結構設計功率元件時，由於元件耐壓終止區(withstanding termination region)的基底的濃度已經提高，故過去的浮置環(floating ring)或場效電板(field plate)的終止區設計，其耐壓效果已明顯不足。
本發明之目的，即提供一種改良的半導體功率元件及其製作方法，以解決先前技藝之不足與缺點。
為達上述目的，本發明提出一種半導體功率元件的製作方法，包含有一晶胞區域，設於一半導體基底上；至少一電晶體元件，設於該晶胞區域內；一周邊耐壓區域，環繞該晶胞區域；複數個島狀的第一磊晶層，設於該周邊耐壓區域內；以及一格狀的第二磊晶層，設於該周邊耐壓區域內，環繞各該島狀磊晶層，將該複數個島狀的第一磊晶層彼此區隔開。
其中該複數個島狀磊晶層具有第一導電型，該半導體基底具有第二導電型，該格狀磊晶層具有該第二導電型。
其中可進一步包含有一第二導電型的第三磊晶層，介於該第一磊晶層、第二磊晶層與該半導體基底之間。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者。
1~5‧‧‧超級接面功率電晶體
10‧‧‧半導體基底
11‧‧‧磊晶層
22‧‧‧閘極氧化層
24‧‧‧閘極
26‧‧‧場氧化層
30‧‧‧層間介電層
34‧‧‧金屬層
34a‧‧‧接觸插塞
60‧‧‧晶片區域
90‧‧‧切割道
100‧‧‧晶胞區域
101‧‧‧過渡區
102‧‧‧周邊耐壓區域
110‧‧‧磊晶層
110’‧‧‧端部
110a‧‧‧磊晶層
111‧‧‧圖案化硬遮罩
111a‧‧‧開口
112‧‧‧磊晶層
112a‧‧‧溝槽結構
112b‧‧‧溝槽結構
120‧‧‧島狀磊晶層
130‧‧‧離子井
132‧‧‧源極摻雜區
230‧‧‧接觸洞
330‧‧‧摻雜帶
430‧‧‧摻雜帶
602‧‧‧閘極結構
630‧‧‧護環摻雜區
634‧‧‧金屬層
634a‧‧‧接觸插塞
702‧‧‧場效電板
第1圖為超級接面功率電晶體的佈局上視圖。
第2圖為第1圖的局部放大示意圖。
第3圖為沿著第2圖中切線I-I’所視的剖面示意圖。
第4圖為超級接面功率電晶體的局部放大上視圖。
第5圖為沿著第4圖中切線II-II’所視的剖面示意圖。
第6圖為依據本發明第三實施例所繪示的超級接面功率電晶體剖面示意圖。
第7圖為依據本發明第四實施例所繪示的超級接面功率電晶體剖面示意圖。
第8圖為超級接面功率電晶體的局部放大上視圖。
第9圖為沿著第8圖中切線III-III’所視的剖面示意圖。
第10圖至第19圖例示超級接面功率電晶體的製作方法，其中以製作第6圖中的超級接面功率電晶體為例做說明。
第20圖為晶圓在磊晶層中進行溝槽蝕刻後的上視示意圖。
以下將藉由所附圖式詳細說明本發明技術特徵，其中各圖式中相同的元件或部位沿用相同的符號來表示。需注意的是，各圖式係以說明為目的，並未依照原尺寸作圖。此外，下文提及之「第一導電型」以及「第二導電型」係用以描述不同材料間之相對導電型種類。舉例而言，其可分別對應至P型以及N型，然而，其也可分別對應至N型以及P型。
請參閱第1圖至第3圖，其為依據本發明第一實施例所繪示的超級接面功率電晶體示意圖，其中第1圖為超級接面功率電晶體的佈局上視圖，第2圖為第1圖的局部放大示意圖，第3圖為沿著第2圖中切線I-I’所視的剖面示意圖。首先，如第1圖所示，超級接面功率電晶體1的佈局結構，包括一晶胞區域(cell region)100以及一環繞晶胞區域100的周邊耐壓區域(termination region)102，其中晶胞區域100係用於設置具有開關功能之電晶體元件，而周邊耐壓區域102係具有延緩高強度電場向外擴散之耐壓結構。為簡化說明，第1圖中僅顯示位於晶胞區域100內直線交替排列的第一導電型(例如P型)磊晶層110及第二導電型(例如N型)磊晶層112，以及位於周邊耐壓區域102內的複數個第一導電型(例如P型)島狀磊晶層120。
如第2圖及第3圖所示，根據第一實施例，超級接面功率電晶體1包括一半導體基底10，具有第二導電型，例如，重摻雜N+矽基底，其可作為超級接面功率電晶體1的汲極。在半導體基底10上設有一第二導電型(例如N型)磊晶層11，在磊晶層11上則為一垂直交替磊晶層，其包括第一導電型(例如P型)磊晶層110、第一導電型(例如P型)島狀磊晶層120，及第二導電型(例如N型)磊晶層112。其中，根據第一實施例，磊晶層110及磊晶層112在晶胞區域100內呈直線交替排列，彼此互相平行，構成超級接面結構。島狀磊晶層120則是位於周邊耐壓區域102，一圈一圈的層層環繞晶胞區域100，呈陣列排列。在圖中，島狀磊晶層120的圈數僅顯示有六圈，但僅為例示，不限於六圈。根據第一實施例，磊晶層112在周邊耐壓區域102中則為格狀或井字形，圍繞著各島狀磊晶層120。
在晶胞區域100內，還有第一導電型(例如P型)離子井130位於各個磊晶層110上部區域，以及源極摻雜區132，位於離子井130內。根據第一實施例，最外面、靠近周邊耐壓區域102的磊晶層110a上的離子井130內，不會形成源極摻雜區132。
根據第一實施例，在晶胞區域100內，閘極24正位於磊晶層112 上，以及閘極氧化層22，位於閘極24與磊晶層112之間。根據第一實施例，在周邊耐壓區域102內，另有連續、環狀的第一導電型(例如P型)摻雜帶330，將各圈的島狀磊晶層120串連起來，其中摻雜帶330可以僅部分重疊於各圈的島狀磊晶層120。層間介電層30覆蓋晶胞區域100及周邊耐壓區域102，位於層間介電層30上的金屬層34透過形成在接觸洞230內的接觸插塞34a，與晶胞區域100內的源極摻雜區132及離子井130電連接。根據第一實施例，在周邊耐壓區域102，另有一場氧化層26，位於層間介電層30下方。
第4圖及第5圖為依據本發明第二實施例所繪示的超級接面功率電晶體示意圖，其中第4圖為超級接面功率電晶體的局部放大上視圖，第5圖為沿著第4圖中切線II-II’所視的剖面示意圖。如第4圖所示，超級接面功率電晶體2的佈局結構，包括一晶胞區域100以及一環繞晶胞區域100的周邊耐壓區域102，根據第二實施例，在晶胞區域100以及周邊耐壓區域102之間，另有一過渡區101。
如第4圖及第5圖所示，超級接面功率電晶體2同樣包括一半導體基底10，具有第二導電型，例如，重摻雜N+矽基底，其可作為超級接面功率電晶體2的汲極。在半導體基底10上設有一第二導電型(例如N型)磊晶層11，在磊晶層11上則設有第一導電型(例如P型)磊晶層110、第一導電型(例如P型)島狀磊晶層120，及第二導電型(例如N型)磊晶層112。其中，根據第一實施例，磊晶層110及磊晶層112在晶胞區域100內呈直線交替排列，彼此互相平行，島狀磊晶層120則是位於周邊耐壓區域12，呈陣列排列。在晶胞區域100內，還有第一導電型(例如P型)離子井130位於各個磊晶層110上部區域，以及源極摻雜區132，位於離子井130內。最外面的磊晶層110a上的離子井130內，不會形成源極摻雜區132。
根據第二實施例，在晶胞區域100內，閘極24位於磊晶層112上，以及閘極氧化層22，位於閘極24與磊晶層112之間。同樣的，在周邊耐壓區域102內，各圈的島狀磊晶層120被連續、環狀的第一導電型(例如P 型)摻雜帶330串連起來。層間介電層30覆蓋晶胞區域100及周邊耐壓區域102，位於層間介電層30上的金屬層34透過接觸洞230內的接觸插塞34a，與晶胞區域100內的源極摻雜區132及離子井130電連接。在周邊耐壓區域102，另有一場氧化層26，位於層間介電層30下方。
在過渡區101內，具有橫跨磊晶層110a及最靠近晶胞區域100的第一圈、第二圈島狀磊晶層120的第一導電型(例如P型)摻雜帶430。此摻雜帶430為一環狀佈局，在此例中為矩形，範圍可以涵蓋最內第一圈、第二圈島狀磊晶層120，磊晶層110a，以及晶胞區域100內的磊晶層110的端部110’。根據第二實施例，摻雜帶430透過接觸洞230內的接觸插塞34a電連接金屬層34。過渡區101可以進一步減緩晶胞區域100與周邊耐壓區域102之間的電場強度。
第6圖為依據本發明第三實施例所繪示的超級接面功率電晶體剖面示意圖。第6圖中的第三實施例超級接面功率電晶體3與第5圖的第二實施例主要差異在於：(1)過渡區101內，橫跨磊晶層110a及最靠近晶胞區域100的第一圈、第二圈島狀磊晶層120的第一導電型(例如P型)護環摻雜區630，其中護環摻雜區630的摻雜濃度、深度可大於磊晶層110a上的離子井130；(2)離子井130與護環摻雜區630重疊；(3)在護環摻雜區630上設有一閘極結構602，且閘極結構602橫跨過渡區101與周邊耐壓區域102，並延伸至場氧化層26上，其中閘極結構602經由接觸插塞634a電連接金屬層634。
第7圖為依據本發明第四實施例所繪示的超級接面功率電晶體剖面示意圖。第7圖中的第四實施例超級接面功率電晶體4與第6圖的第三實施例主要差異在於：在場氧化層26上，靠近閘極結構602處，另設有一場效電板702，其中，閘極結構602與場效電板702可以是環狀的，且可以由多晶矽所構成。根據第四實施例，場效電板702係位於周邊耐壓區域102。
第8圖及第9圖為依據本發明第五實施例所繪示的超級接面功率電晶體示意圖，其中第8圖為超級接面功率電晶體5的局部放大上視圖，第 9圖為沿著第8圖中切線III-III’所視的剖面示意圖。第8~9圖中的第五實施例超級接面功率電晶體5與第7圖的第四實施例主要差異在於：位於周邊耐壓區域102的島狀磊晶層120係為各自獨立的，不再經由連續、環狀的第一導電型(例如P型)摻雜帶330串連起來。從第9圖可看出，周邊耐壓區域102的島狀磊晶層120之上為磊晶層112。
第10圖至第19圖例示超級接面功率電晶體的製作方法，其中以製作第6圖中的超級接面功率電晶體為例做說明。首先，如第10圖所示，提供一半導體基底10，具有第二導電型，例如，重摻雜N+矽基底，其可作為超級接面功率電晶體1的汲極。在半導體基底10上形成有一第二導電型(例如N型)磊晶層11，接著在磊晶層11上形成一第一導電型(例如P型)磊晶層110。
如第11圖所示，於磊晶層110上形成一圖案化硬遮罩111。接著利用圖案化硬遮罩111作為蝕刻遮罩，進行乾蝕刻製程，經由圖案化硬遮罩111的開口111a向下蝕刻出溝槽結構112a及溝槽結構112b，同時定義出晶胞區域100內直線排列的第一導電型磊晶層110，以及周邊耐壓區域102內的複數個第一導電型島狀磊晶層120。其中溝槽結構112a為平行於第一導電型磊晶層110的直線型溝槽，而溝槽結構112b則為環繞第一導電型島狀磊晶層120的網狀或格狀溝槽，如第20圖所示。值得注意的是，溝槽結構112a及溝槽結構112b的蝕刻步驟是整片晶圓同時定義，而且是跨越不同晶片區域60來進行，如第20圖所示，在晶片區域60之間，為切割道90，而溝槽結構112b可形成在切割道90，並與溝槽結構112a對齊。
如第12圖所示，形成溝槽結構112a及溝槽結構112b之後，可以選擇於溝槽表面形成犧牲氧化層(圖未示)，再將犧牲氧化層去除。然後，在溝槽結構112a及溝槽結構112b內填滿第二導電型(例如N型)磊晶層112，並且使磊晶層112覆蓋第一導電型磊晶層110。另外，也可繼續進行化學機械研磨(chmical mechanical polishing,CMP)製程，先研磨掉部分厚度的磊晶層 112，進行氧化製程，形成一氧化膜(圖未示)，然後去除該氧化膜，接著再進行一次第一導電型磊晶製程。
如第13圖所示，進行離子佈植製程，在周邊耐壓區域102內，形成連續、環狀的第一導電型(例如P型)摻雜帶330。摻雜帶330係形成在磊晶層112中，將各圈的島狀磊晶層120串連起來，其中摻雜帶330可以僅部分重疊於各圈的島狀磊晶層120。
如第14圖所示，接著於磊晶層112上形成場氧化層26，再以微影製程及蝕刻製程大致將晶胞區域100及過渡區101內的場氧化層26去除，顯露出位於晶胞區域100及過渡區101內的磊晶層112，留下位於周邊耐壓區域102內的場氧化層26。
如第15圖所示，利用微影製程及蝕刻製程，於過渡區101內的磊晶層112植入第一導電型(例如P型)摻質，例如，硼，形成第一導電型護環摻雜區630。此護環摻雜區630為一環狀佈局。
如第16圖所示，接著進行一氧化製程，於磊晶層112表面形成一閘極氧化層22。然後，進行化學氣相沈積(chemical vapor deposition,CVD)製程，全面沈積一多晶矽層，再以微影及蝕刻製程，將多晶矽層蝕刻定義為晶胞區域100內的閘極24以及周邊耐壓區域102內的閘極結構602。
如第17圖所示，利用微影及離子佈植製程，將第一導電型(例如P型)離子井130植入於晶胞區域100內各個磊晶層110上部區域以及磊晶層110a的上部區域，其中磊晶層110a上的離子井130與護環摻雜區630重疊。上述形成離子井130的離子佈植製程係自動對準於閘極24，而在周邊耐壓區域102內則是被光阻覆蓋，不會形成離子井130。
如第18圖所示，接著再次利用微影及離子佈植製程，於離子井130內形成源極摻雜區132。最後，如第19圖所示，沈積層間介電層30，使其覆蓋在閘極24及閘極結構602上。接著，利用微影及蝕刻製程，於層間介電層30中形成接觸洞230，再以金屬層34填滿接觸洞230構成接觸插塞34a 及634a，使金屬層34與晶胞區域100內的源極摻雜區132及離子井130電連接，而且使金屬層634與閘極結構602電連接。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
3‧‧‧超級接面功率電晶體
10‧‧‧半導體基底
11‧‧‧磊晶層
22‧‧‧閘極氧化層
24‧‧‧閘極
26‧‧‧場氧化層
30‧‧‧層間介電層
34‧‧‧金屬層
34a‧‧‧接觸插塞
100‧‧‧晶胞區域
101‧‧‧過渡區
102‧‧‧周邊耐壓區域
110‧‧‧磊晶層
110a‧‧‧磊晶層
112‧‧‧磊晶層
120‧‧‧島狀磊晶層
130‧‧‧離子井
132‧‧‧源極摻雜區
230‧‧‧接觸洞
602‧‧‧閘極結構
630‧‧‧護環摻雜區
634‧‧‧金屬層
634a‧‧‧接觸插塞

Claims (15)

  1. 一種半導體功率元件，包含有：一晶胞區域，設於一半導體基底上；至少一電晶體元件，設於該晶胞區域內；一周邊耐壓區域，環繞該晶胞區域；複數個島狀的第一磊晶層，設於該周邊耐壓區域內；以及一格狀的第二磊晶層，設於該周邊耐壓區域內，環繞各該島狀磊晶層，將該複數個島狀的第一磊晶層彼此區隔開。
  2. 如申請專利範圍第1項所述之半導體功率元件，其中該複數個島狀磊晶層具有第一導電型，該半導體基底具有第二導電型，該格狀磊晶層具有該第二導電型。
  3. 如申請專利範圍第2項所述之半導體功率元件，其中該第一導電型為P型，該第二導電型為N型。
  4. 如申請專利範圍第2項所述之半導體功率元件，其中另包含有一第三磊晶層，介於該第一磊晶層、第二磊晶層與該半導體基底之間。
  5. 如申請專利範圍第4項所述之半導體功率元件，其中該第三磊晶層具有該第二導電型。
  6. 如申請專利範圍第1項所述之半導體功率元件，其中該電晶體元件至少包含一直線型的該第一磊晶層與至少一直線型的該第二磊晶層、一離子井設於該第一磊晶層上部區域，以及源極摻雜區，位於該離子井內。
  7. 如申請專利範圍第1項所述之半導體功率元件，其中另包含有至少一連續、環狀的摻雜帶，位於該周邊耐壓區域內，將該複數個島狀的第一磊晶層串連起來。
  8. 如申請專利範圍第7項所述之半導體功率元件，其中該摻雜帶具有該第一導電型。
  9. 如申請專利範圍第1項所述之半導體功率元件，其中另包含有一過渡區，位於該晶胞區域以及該周邊耐壓區域之間。
  10. 如申請專利範圍第9項所述之半導體功率元件，其中該過渡區為環狀佈局。
  11. 如申請專利範圍第9項所述之半導體功率元件，其中另包含有一護環摻雜區，位於該過渡區。
  12. 如申請專利範圍第11項所述之半導體功率元件，其中該護環摻雜區具有該第一導電型。
  13. 如申請專利範圍第11項所述之半導體功率元件，其中在該護環摻雜區上設有一閘極結構，且該閘極結構橫跨該過渡區與該周邊耐壓區域，並延伸至一場氧化層上。
  14. 如申請專利範圍第13項所述之半導體功率元件，其中另包含有一場效電板，位於該場氧化層上。
  15. 如申請專利範圍第14項所述之半導體功率元件，其中該閘極結構與該場效電板均為多晶矽層。
TW102110729A 2013-03-26 2013-03-26 半導體功率元件及其製作方法 TW201438232A (zh)

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