TWI463571B - 半導體裝置的製造方法 - Google Patents

半導體裝置的製造方法 Download PDF

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TWI463571B
TWI463571B TW100145294A TW100145294A TWI463571B TW I463571 B TWI463571 B TW I463571B TW 100145294 A TW100145294 A TW 100145294A TW 100145294 A TW100145294 A TW 100145294A TW I463571 B TWI463571 B TW I463571B
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trenches
epitaxial layer
semiconductor device
conductivity type
doped regions
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TW201324621A (zh
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Tsung Hsiung Lee
Shang Hui Tu
Rudy Octavius Sihombing
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Vanguard Int Semiconduct Corp
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Priority to US13/464,584 priority patent/US9076887B2/en
Priority to JP2012139426A priority patent/JP5551213B2/ja
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Description

半導體裝置的製造方法
本發明係有關於一種半導體裝置的製造方法，特別係有關於一種具有超接面結構之半導體裝置的製造方法。
習知的垂直式擴散金氧半場效電晶體(VDMOSFET)主要是由N型磊晶(epitaxy)漂移(drift region)區與其上方P型基體(base)摻合區形成P-N接面，而半導體元件的耐壓主要是P-N接面來承受。在提高半導體元件的操作電壓時，必須降低N型磊晶漂移區的摻質濃度和提升其厚度。相對的，上述提升P-N接面的耐壓的方式同時也會增加元件的導通電阻(Ron)，而導通電阻也會受到N型磊晶漂移區的摻質濃度與厚度的限制。而具有超接面(Super-junction)結構的垂直式擴散金氧半場效電晶體可以提高N型磊晶漂移區的摻質濃度，進而改善元件的導通電阻(Ron)。
習知技術係利用多層磊晶(multi-epi technology，COOLMOSTM )技術來形成超接面(Super-junction)結構，上述多層磊晶技術需要進行多次包括磊晶、植入P型摻質、高溫擴散的製程循環。因此，上述多層磊晶技術會有製程步驟多、成本高等缺點，且元件尺寸較難微縮。
因此，在此技術領域中，有需要一種具有超接面結構之半導體裝置的製造方法，以滿足上述需求且克服習知技術的缺點。
有鑑於此，本發明一實施例係提供一種半導體裝置的製造方法，上述半導體裝置的製造方法包括提供一半導體基底，具有一第一導電類型；於上述半導體基底上形成一磊晶層，具有上述第一導電類型；於上述磊晶層中形成複數個第一溝槽；順應性於上述些第一溝槽的側壁和底面上形成複數個第一絕緣襯墊層；進行一第一摻雜製程，將具有上述第一導電類型的一第一摻質沿上述些第一溝槽的側壁摻雜上述磊晶層，以形成複數個第一摻雜區；將一第一絕緣材料填入上述些第一溝槽；於上述磊晶層中形成複數個第二溝槽；順應性於上述些第二溝槽的側壁和底面上形成複數個第二絕緣襯墊層；進行一第二摻雜製程，將具有一第二導電類型的一第二摻質沿上述些第二溝槽的側壁摻雜上述磊晶層，以形成複數個第二摻雜區；將一第二絕緣材料填入上述些第二溝槽。
以下以各實施例詳細說明並伴隨著圖式說明之範例，做為本發明之參考依據。在圖式或說明書描述中，相似或相同之部分皆使用相同之圖號。且在圖式中，實施例之形狀或是厚度可擴大，並以簡化或是方便標示。再者，圖式中各元件之部分將以分別描述說明之，值得注意的是，圖中未繪示或描述之元件，為所屬技術領域中具有通常知識者所知的形式。
第1~7圖為本發明一實施例之半導體裝置的的製程剖面圖。本發明實施例的半導體裝置包括具有超接面(super junction)結構的金氧半薄膜電晶體(MOSFET)，例如為超接面垂直式擴散金氧半場效電晶體(VDMOSFET)。如第1圖所示，首先，提供一半導體基底200，具有一第一導電類型。接著，進行一磊晶成長製程，於該半導體基底上形成一磊晶層202。在本發明一實施例中，半導體基底200和磊晶層202具有相同的導電類型，且半導體基底200的摻質濃度大於磊晶層202的摻質濃度。因此，在本例中，半導體基底200可為一N型重摻雜(N+)半導體基底200，而磊晶層202可為一N型輕摻雜(N-)磊晶層202。如第1圖所示，磊晶層202可包括一主動區300和圍繞主動區300的一終端區302。在本發明一實施例中，主動區300係提供半導體元件形成於其上，而終端區302係做為不同半導體裝置之間的絕緣。
接著，請參考第2圖，說明第一溝槽204的形成方式。可進行例如低壓化學氣相沉積(LPCVD)形成一硬遮罩(Hard Mask)，接著進行一微影製程和圖案化製程，於磊晶層202的主動區300上覆蓋一遮罩圖案(圖未顯示)，定義出第一溝槽的形成位置，再進行一非等向性蝕刻製程，移除未被遮罩圖案覆蓋的部分磊晶層202，以於磊晶層202的主動區300中形成複數個第一溝槽204。在本發明一實施例中，第一溝槽204的底面205可接觸半導體基底200和磊晶層202的界面201，或位於磊晶層202內(意即接近界面201)。
移除上述遮罩圖案後，接著，進行例如熱氧化(thermal oxidation)生長法，順應性於第一溝槽204的側壁207和底面205上形成第一絕緣襯墊層206。在本發明一實施例中，第一絕緣襯墊層206可為氧化襯墊層，其可降低磊晶層202的應力，且可做為後續摻雜製程的屏蔽氧化層(pre-implant oxide)，以降低通道效應。
接著，請參考第3圖，進行一摻雜製程208，將具有第一導電類型的一第一摻質沿每一個第一溝槽204的兩個相對側壁207分別摻雜部分磊晶層202，以形成複數個第一摻雜區210。在本發明一實施例中，主要由第一溝槽204的寬度和深度決定摻雜製程208的摻雜角度θ1，例如可介於0至10度(°)之間。另外，在本發明一實施例中，而第一摻質可為包括磷(P)、或鉮(As)的N型摻質。在本發明一實施例中，進行摻雜製程208之後，可進行一擴散製程，其製程溫度大約為800℃至1500℃，以使第一摻雜區210中的第一摻質均勻分佈。進行擴散製程之後的第一摻雜區210的導電類型為N型，而第一摻雜區210的摻質濃度大於磊晶層202的摻質濃度，且小於半導體基底200的摻質濃度。如第3圖所示，第一摻雜區210大體上包圍第一溝槽204，而第一摻雜區210的深度大於第一溝槽204的深度，因此第一溝槽204的底面係位於第一摻雜區210內。
接著，請參考第4圖，可進行例如低壓化學氣相沉積法(LPCVD)之一沉積製程，或例如旋塗式玻璃法(SOG)之一塗佈製程，將一第一絕緣材料212填入第一溝槽204，並覆蓋第一絕緣襯墊層206。然後再進行例如化學機械研磨製程(CMP)的一平坦化製程，移除磊晶層202的頂面203上多餘的第一絕緣材料212。在本發明一實施例中，第一絕緣材料212可包括氧化材料或無摻雜多晶矽材料，且進行平坦化製程之後的第一絕緣材料212的頂面213與磊晶層202的頂面203對齊。
請再參考第4圖，接著說明第二溝槽218的形成方式，為了方便說明，在本例中只顯示一個第二溝槽218。然而，在其他實施例中，第二溝槽218的數量可為兩個或兩個以上，依元件設計而定。可進行例如低壓化學氣相沉積(LPCVD)形成一硬遮罩(Hard Mask)，接著進行一微影製程和圖案化製程，於磊晶層202的主動區300上覆蓋一遮罩圖案(圖未顯示)，定義出第二溝槽的形成位置。在本發明一實施例中，第一溝槽和第二溝槽係交錯設置，意即第二溝槽的兩側係分別相鄰第一溝槽。然而，再進行一非等向性蝕刻製程，移除未被遮罩圖案覆蓋的部分磊晶層202，以於磊晶層202的主動區300中形成第二溝槽218。在本發明一實施例中，第二溝槽218的底面219可接觸半導體基底200和磊晶層202的界面201，或位於磊晶層202內(意即接近界面201)。在本發明一實施例中，第一溝槽204和第二溝槽218可具有相同的寬度和深度，或者依元件特性調整溝槽寬度及深度。
移除上述遮罩圖案後，接著，進行例如熱氧化(thermal oxidation)生長，順應性於第二溝槽218的側壁221和底面219上形成第二絕緣襯墊層220。在本發明一實施例中，第二絕緣襯墊層220可為氧化襯墊層，其可降低磊晶層202的應力，且可做為後續摻雜製程的屏蔽氧化層(pre-implant oxide)，以降低通道效應。
接著，請參考第5圖，進行一摻雜製程216，將具有第二導電類型的一第二摻質沿每一個第二溝槽218的兩個相對側壁221分別摻雜部分磊晶層202，以於主動區300中形成相鄰第二溝槽218的側壁221的複數個第二摻雜區222。在本發明一實施例中，主要由第二溝槽218的寬度和深度決定第二摻雜製程216的摻雜角度θ2，例如可介於0至10度(°)之間。另外，在本發明一實施例中，而第二摻質可為包括硼(B)的P型摻質。在本發明一實施例中，進行摻雜製程216之後，可進行一擴散製程，其製程溫度大約為800℃至1500℃，以使第二摻雜區222中的第二摻質均勻分佈，以將第二摻雜區222的導電類型反轉為P型。因此，進行擴散製程之後的第二摻雜區222的導電類型為P型，而第二摻雜區222的摻質濃度大於磊晶層202的摻質濃度，且小於半導體基底200的摻質濃度。如第5圖所示，第二摻雜區222大體上包圍第二溝槽218，而第二摻雜區222的深度大於第二溝槽218的深度，因此第二溝槽218的底面係位於第二摻雜區222內。
接著，請參考第6圖，可進行例如低壓化學氣相沉積法(LPCVD)之一沉積製程，或例如旋塗式玻璃法(SOG)之一塗佈製程，將一第二絕緣材料230填入第二溝槽218，並覆蓋第二絕緣襯墊層220。然後再進行例如化學機械研磨製程(CMP)的一平坦化製程，移除磊晶層202的頂面203上多餘的第二絕緣材料230。在本發明一實施例中，第二絕緣材料230可包括氧化材料或無摻雜多晶矽材料，且進行平坦化製程之後的第二絕緣材料230的頂面213與磊晶層202的頂面203對齊。經過上述製程，每一個第一摻雜區210與一個第二摻雜區222彼此相鄰且具相反的導電類型，因而形成本發明一實施例的一超接面結構250。在其他實施例中，超接面結構250的第一摻雜區210與第二摻雜區222的導電類型可以互換。
第6~7圖係說明於超接面結構250上製造例如垂直式擴散金氧半場效電晶體(VDMOSFET)的半導體元件。接著，請參考第6圖，全面性於磊晶層202上依序形成一閘極氧化層(圖未顯示)和一閘極層(圖未顯示)。在本發明一實施例中，可利用例如熱氧化法(thermal oxidation)、化學氣相沉積法(chemical vapor deposition,CVD)或原子層化學氣相沉積法(atomic layer CVD,ALD)等薄膜沉積方式形成閘極氧化層。可利用例如化學氣相沉積法(CVD)、物理氣相沉積法(PVD)、原子層沉積法(ALD)、濺鍍法、電鍍法等薄膜沉積方式形成閘極層。在本發明一實施例中，閘極氧化層可包括例如氧化物(oxide)、氮化物(nitride)、氮氧化物(oxynitride)、碳氧化物(oxycarbide)或其組合。在本發明一實施例中，閘極層可為一多晶矽層。然後，可於磊晶層202的主動區300上覆蓋圖案化光阻層(圖未顯示)，以定義出如第6圖所示之閘極氧化層圖案224及閘極層圖案226的形成位置，再以圖案化光阻層為罩幕，利用非等向性蝕刻方式，移除部分閘極氧化層和閘極層，以於主動區300形成由閘極氧化層圖案224及閘極層圖案226構成的複數個閘極結構228。在本發明一實施例中，閘極結構228分別覆蓋第一溝槽204且覆蓋相鄰第一溝槽204的部分磊晶層202，且第二溝槽218從閘極結構228暴露出來。之後，將圖案化光阻層移除。如第6圖所示，閘極結構228的側壁係位於第一摻雜區210的邊界內，意即部分第一摻雜區210係從第一摻雜區210暴露出來。
接著，請參考第6圖，可以利用閘極結構228為罩幕，進行一第三摻雜製程，於未被閘極結構228覆蓋的磊晶層202的主動區300中形成具有第二導電類型的一第一井區232。如第6圖所示，第一井區232係位於兩個相鄰的閘極結構228之間，且與第二溝槽218部分重疊。如第6圖所示，第一井區232會與閘極結構228部分重疊，且第一井區232位於第二摻雜區222的上方。在本發明一實施例中，第一井區232可視為一P型井區232，且第一井區232鄰近磊晶層202表面的邊界位於第一摻雜區210內，且位於第一摻雜區210內的第一井區232導電類型被反轉為P型。之後，可使用圖案化光阻層(圖未顯示)為罩幕，進行一摻雜製程，於第一井區232中形成複數個源極區234。在本發明一實施例中，第一井區232內的源極區234的導電類型被反轉為N型，且源極區234的摻質濃度大於第一井區232的摻質濃度。如第6圖所示，源極區234分別相鄰不同閘極結構228的一側邊。並且，兩個相鄰的閘極結構228係共用一個第一井區232，因此，上述兩個相鄰的閘極結構228的兩個源極區234皆形成於同一個第一井區232中。每一個超接面結構250之第一摻雜區210與第二摻雜區222的界面可設計係位於源極區234的下方可依照元件特性調整第一摻雜區210與第二摻雜區222的界面位置。另外，N型半導體基底200係視為最終形成垂直式擴散金氧半場效電晶體(VDMOSFET)的汲極。
接著，請參考第7圖，可進行例如化學氣相沉積法(CVD)之一沉積製程，全面性形成一層間介電層(ILD)236，覆蓋磊晶層202和閘極結構228。之後，可於層間介電層(ILD)236上覆蓋圖案化光阻層(圖未顯示)，以定義出如第7圖所示之接觸孔開口238的形成位置，再以圖案化光阻層為罩幕，利用非等向性蝕刻方式，移除部分層間介電層236，以形成接觸孔開口238。如第7圖所示，部分源極區234和源極區234之間的部分第一井區232內的磊晶層202從接觸孔開口238暴露出來。
接著，請再參考第7圖，進行一摻雜製程，於從接觸孔開口238暴露出來的部分磊晶層202中形成具有第二導電類型的複數個接線區240。在本發明一實施例中，接線區240的導電類型為P型。如第7圖所示，接線區240分別相鄰第二溝槽218的不同側邊221，且每一個接線區240與一個源極區234相鄰，且位於第二摻雜區222的上方。
接著，請再參考第7圖，可進行例如濺鍍法之一沉積製程，全面性形成一導電材料，並填入接觸孔開口238，以形成複數個接觸孔插塞242。經過上述製程，係完成例如為垂直式擴散金氧半場效電晶體(VDMOSFET)之本發明實施例之具有超接面結構250的半導體裝置500。
本發明實施例之半導體裝置500的製造方法係以N型VDMOSFET做為實施例。然而在其他實施例中，上述第一導電類型和第二導電類型可以互換，以形成P型VDMOSFET。
本發明實施例係提供一種具有超接面結構250的半導體裝置500。本發明實施例的超接面結構250係於一低摻雜N型磊晶層中蝕刻形成一溝槽。然後，以低角度植入高摻質濃度(相較於N型磊晶層)的N型區域，回填絕緣材料於上述溝槽之後，再蝕刻形成另一溝槽。之後，以低角度植入高摻質濃度(相較於N型磊晶層)的P型區域，完成P-N柱狀的超接面結構。相較於習知技術，本發明實施例的超接面結構250可藉由控制N型區域和P型區域的摻質濃度來達到電荷平衡(charge balance)的功效。因而可以降低N型磊晶層的摻質濃度約可從2E15降至1E14~4E13左右，可依照元件設計選用所需要的濃度。另外，本發明實施例的超接面結構250不須進行額外的磊晶製程，因而可以節省製程成本。並且，形成於其上的半導體元件可以具有較小的元件尺寸。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定為準。
500．．．半導體裝置
200．．．半導體基底
201．．．界面
202．．．磊晶層
203、213．．．頂面
204．．．第一溝槽
205、219．．．底面
206．．．第一絕緣襯墊層
208、216．．．摻雜製程
207、221．．．側壁
210．．．第一摻雜區
212．．．第一絕緣材料
218．．．第二溝槽
220．．．第二絕緣襯墊層
222．．．第二摻雜區
224．．．閘極氧化層圖案
226．．．閘極層圖案
228．．．閘極結構
230．．．第二絕緣材料
232．．．第一井區
234．．．源極區
236．．．層間介電層
238．．．接觸孔開口
240．．．接線區
242．．．接觸孔插塞
250．．．超接面結構
300．．．主動區
302．．．終端區
θ1、θ2．．．角度
第1~7圖為本發明一實施例之半導體裝置的製造方法的剖面圖。
500．．．半導體裝置
200．．．半導體基底
201．．．界面
202．．．磊晶層
203、213．．．頂面
204．．．第一溝槽
205、219．．．底面
206．．．第一絕緣襯墊層
207、221．．．側壁
210．．．第一摻雜區
212．．．第一絕緣材料
218．．．第二溝槽
220．．．第二絕緣襯墊層
222．．．第二摻雜區
224．．．閘極氧化層圖案
226．．．閘極層圖案
228．．．閘極結構
230．．．第二絕緣材料
232．．．第一井區
234．．．源極區
236．．．層間介電層
238．．．接觸孔開口
240．．．接線區
242．．．接觸孔插塞
250．．．超接面結構
300．．．主動區
302．．．終端區

Claims (12)

  1. 一種半導體裝置的製造方法，包括下列步驟：提供一半導體基底，具有一第一導電類型；於該半導體基底上形成一磊晶層，具有該第一導電類型；於該磊晶層中形成複數個第一溝槽；順應性於該些第一溝槽的側壁和底面上形成複數個第一絕緣襯墊層；進行一第一摻雜製程，將具有該第一導電類型的一第一摻質沿該些第一溝槽的該些側壁摻雜該磊晶層，以形成複數個第一摻雜區，其中該些第一溝槽的該些底面係位於該些第一摻雜區內；將一第一絕緣材料填入該些第一溝槽；於該磊晶層中形成複數個第二溝槽；順應性於該些第二溝槽的側壁和底面上形成複數個第二絕緣襯墊層；進行一第二摻雜製程，將具有一第二導電類型的一第二摻質沿該些第二溝槽的該些側壁摻雜該磊晶層，以形成複數個第二摻雜區；以及將一第二絕緣材料填入該些第二溝槽。
  2. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中該第一導電類型為n型，且該第二導電類型為p型。
  3. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中該半導體基底的摻質濃度大於該磊晶層的摻 質濃度。
  4. 如申請專利範圍第1項所述之半導體裝置的製造方法，進行該第一摻雜製程之後更包括進行一第一擴散製程，使該第一摻質均勻分佈於每一個該些第一摻雜區中，且進行該第二摻雜製程之後更包括進行一第二擴散製程，使該第二摻質均勻分佈於每一個該些第二摻雜區中。
  5. 如申請專利範圍第4項所述之半導體裝置的製造方法，其中進行該第一擴散製程後，位於該些第一摻雜區中的該磊晶層具有該第一導電類型，且其中進行該第二擴散製程後，位於該些第二摻雜區中的該磊晶層具有該第二導電類型。
  6. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中該些第一溝槽和該些第二溝槽的該些底面在該磊晶層內。
  7. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中該第一和第二絕緣材料包括氧化材料或無摻雜多晶矽材料，且該第一和第二絕緣材料的頂面與該磊晶層的一頂面對齊。
  8. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中該些第一溝槽和該些第二溝槽係交錯設置。
  9. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中每一個該些第一摻雜區相鄰該些第二摻雜區的其中一個。
  10. 如申請專利範圍第1項所述之半導體裝置的製 造方法，其中該些第一摻雜區和該些第二摻雜區為柱狀。
  11. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中該些第一摻雜區和該些第二摻雜區的摻質濃度大於該磊晶層的摻質濃度。
  12. 如申請專利範圍第1項所述之半導體裝置的製造方法，將該第二絕緣材料填入該些第二溝槽之後包括：於該磊晶層上依序形成一閘極氧化層和一閘極層；移除部分該閘極氧化層和該閘極層，以形成複數個閘極結構，其中該些閘極結構分別覆蓋該些第一溝槽且覆蓋相鄰該些第一溝槽的部分該磊晶層，且該些第二溝槽從該些閘極結構暴露出來；於未被該些閘極結構覆蓋的該磊晶層中形成一第一井區，具有該第二導電類型；於該第一井區中形成複數個源極區，具有該第一導電類型，其中該些源極區分別相鄰該些閘極結構；形成一層間介電層，覆蓋該磊晶層和該些閘極結構；移除部分該層間介電層，形成一接觸孔開口，該些第二溝槽和相鄰該些第二溝槽的部分該磊晶層從些接觸孔開口暴露出來；於從該接觸孔開口暴露出來的部分該磊晶層中形成複數個接線區，具有該第二導電類型；以及將一導電材料填入該接觸孔開口，以形成一接觸孔插塞。
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