TWI415173B - 低米勒電容之超級接面功率電晶體製造方法 - Google Patents

低米勒電容之超級接面功率電晶體製造方法 Download PDF

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TWI415173B
TWI415173B TW100117647A TW100117647A TWI415173B TW I415173 B TWI415173 B TW I415173B TW 100117647 A TW100117647 A TW 100117647A TW 100117647 A TW100117647 A TW 100117647A TW I415173 B TWI415173 B TW I415173B
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manufacturing
power transistor
junction power
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TW100117647A
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TW201248700A (en
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Yung Fa Lin
Shou Yi Hsu
Meng Wei Wu
Main Gwo Chen
Yi Chun Shih
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Anpec Electronics Corp
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Priority to CN201110238139.6A priority patent/CN102789987B/zh
Priority to US13/234,132 priority patent/US8541278B2/en
Priority to US13/433,302 priority patent/US8748973B2/en
Publication of TW201248700A publication Critical patent/TW201248700A/zh
Priority to US13/894,443 priority patent/US8603879B2/en
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Priority to US14/217,501 priority patent/US8790971B1/en

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Description

低米勒電容之超級接面功率電晶體製造方法
本發明係有關於功率半導體元件技術領域，特別是有關於一種具有低米勒電容之超級接面(super-junction)功率金氧半場效電晶體(power MOSFET)元件的製作方法。
功率半導體元件常應用於電源管理的部分，例如，切換式電源供應器、電腦中心或周邊電源管理IC、背光板電源供應器或馬達控制等等用途，其種類包含有絕緣閘雙極性電晶體(insulated gate bipolar transistor，IGBT)、金氧半場效電晶體(metal-oxide-semiconductor field-effect transistor，MOSFET)與雙載子接面電晶體(bipolar junction transistor，BJT)等元件。其中，由於MOSFET可節省電能且可提供較快的元件切換速度，因此被廣泛地應用各領域之中。
在已知的功率元件中，有一種是在基底中設置成交替的P型磊晶層與N型磊晶層，如此在基底中形成複數個垂直於基底表面的PN接面，且該些PN接面互相平行，這樣的功率元件又稱為超級接面功率MOSFET元件。通常，在超級接面功率MOSFET元件上會設置閘極結構，用以控制元件之電流開關。然而，上述習知技術仍有缺點需要進一步改進，例如，電晶體的通道長度不易控制，造成較低的臨界電壓(thresbold voltage，Vt)。此外，過去的超級接面功率MOSFET元件具有較高的米勒電容，導致較高的切換損失(switching loss)，影響元件效能。
可知，目前業界仍需一種改良之超級接面之功率半導體元件之製作方法，以克服先前技藝之缺點與不足。
本發明的主要目的即在於提供一種功率半導體元件之製作方法，能夠簡化低米勒電容之超級接面功率電晶體之製程步驟。
根據本發明之較佳實施例，本發明披露一種低米勒電容之超級接面功率電晶體製造方法。首先提供一N型汲極基底，並於N型汲極基底形成一P型磊晶層。接著，於一晶胞區域內的P型磊晶層中形成至少一溝槽，並於溝槽的表面形成一緩衝層。填入一N型摻質來源層於溝槽內，並回蝕刻N型摻質來源層，以於溝槽之上端形成一凹陷結構。於凹陷結構的表面形成一閘極氧化層，同時，使N型摻質來源層內的N型摻質經由緩衝層擴散至P型磊晶層，俾形成一N型基體摻雜區。接著，於凹陷結構內填入一閘極導體，並於閘極導體周圍的P型磊晶層內形成一N型源極摻雜區。
根據本發明之另一較佳實施例，一種低米勒電容之超級接面功率電晶體製造方法，首先提供一N型汲極基底，並N型汲極基底形成一P型磊晶層。接著，於一週邊耐壓區域內的P型磊晶層中形成至少一溝槽，並於溝槽的表面形成一緩衝層。填入一N型摻質來源層於溝槽內，並回蝕刻該N型摻質來源層，以於該溝槽之上端形成一凹陷結構。於該凹陷結構的表面形成一閘極氧化層，同時，使該N型摻質來源層內的N型摻質經由該緩衝層擴散至該P型磊晶層，俾形成一N型基體摻雜區。接著，去除該週邊耐壓區域內的該閘極氧化層並且於該凹陷結構內填入一閘極導體。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者。
請參閱第1圖至第11圖，其為依據本發明較佳實施例所繪示的具有低米勒電容之超級接面功率電晶體之製造方法示意圖，其中圖式中相同的元件或部位沿用相同的符號來表示。需注意的是，圖式係以說明為目的，並未依照原尺寸作圖。
首先，如第1圖所示，提供一N型汲極基底120。N型汲極基底120上定義有一晶胞區域(cell region)140以及一週邊耐壓區域(termination region)160，其中晶胞區域140係用於設置具有開關功能之電晶體元件，而週邊耐壓區域160係屬於延緩晶胞區域140之高強度電場向外擴散之耐壓結構。接著，在本發明之較佳具體實施例中，於晶胞區域140以及一週邊耐壓區域160內，利用一磊晶製程於第一導電型基材120上形成一P型磊晶層180。其中，在完成P型磊晶層180之後，可選擇繼續進行一離子佈植製程，俾使P型磊晶層180上方之特定區域形成一P型井180a。且較佳者，該P型井180a之的摻雜濃度大於該P型磊晶層180的摻雜濃度。上述磊晶製程可以利用一化學氣相沈積製程或其它合適方法形成。接著，於P型磊晶層180上形成一硬遮罩層240，此硬遮罩層240之組成可以包含氮化矽(Si3N4)或二氧化矽(SiO2)。
如第2圖所示，接著，分別於晶胞區域140以及週邊耐壓區160進行一微影蝕刻製程，於硬遮罩層240以及P型磊晶層180中形成至少一溝槽260，包括溝槽260a及溝槽260b，其中溝槽260a設置於晶胞區域140內，而溝槽260b設置於週邊耐壓區域160內且該些溝槽260深入至N型汲極基底120。接著，於溝槽260的表面形成一緩衝層250，其中該緩衝層250係以熱氧化法形成者，且其組成包含有氧化矽。
如第3圖所示，接著沈積一N型摻質來源層270，例如，砷摻雜矽玻璃(arsenicsilicate glass，ASG)，使N型摻質來源層270填滿溝渠260，然後再進行回蝕刻，以去除硬遮罩層240(圖未示)表面上的N型摻質來源層270，並於溝槽260之上端形成一凹陷結構280，包括位於晶胞區域140內的凹陷結構280a，以及位於週邊耐壓區域160內的凹陷結構280b。其中，該凹陷結構280之深度約略等於P型井180a之接面深度。接著，進行一微影蝕刻製程，並可於晶胞區域140進行一斜向離子佈植製程，以於凹陷結構280a的表面形成一離子摻雜區，可藉由離子摻雜區調整位於P型井180a內之垂直通道(圖未示)的臨界電壓(threshold voltage，Vt)。繼之，去除硬遮罩層240(圖未示)，以暴露出P型磊晶層180之上表面。
如第4圖所示，接著，於凹陷結構280的表面形成一閘極氧化層360，同時，使N型摻質來源層270的N型摻質經由緩衝層250擴散至P型磊晶層180，俾形成一N型基體摻雜區290。其中N型基體摻雜區290包圍各溝渠260。接著，進行一蝕刻製程，以去除凹陷結構280b內之閘極氧化層360。接著，於晶胞區域140以及週邊耐壓區域160全面沈積一閘極導體370，使閘極導體370填入凹陷結構280中，其中，閘極導體370可包含多晶矽。
接著，如第5圖所示，進行一化學機械研磨製程(chemical mechanical polishing，CMP)，將位於P型磊晶層180上方之閘極導體370去除，並可以繼續施以回蝕刻製程，以完全去除P型磊晶層180上的閘極導體370，如此形成閘極導體370a及閘極導體370b。值得注意的是，此時填入凹陷結構280a內之閘極導體370a係直接接觸N型摻質來源層270，且被閘極氧化層360所環繞，並與P型磊晶層180或P型井180a隔離，而凹陷結構280b內之閘極導體370b係直接接觸P型磊晶層180或P型井180a。閘極導體370b可作為一耦合導體(coupling conductor)，俾使週邊耐壓區域160之電壓維持平緩下降之趨勢，並且使電壓截止在特定區域。
隨後，如第6圖所示，進行一微影製程，形成光阻圖案390，以於晶胞區域140內暴露出一主動區域380。接著，於此主動區域380進行一離子佈植製程，以於閘極導體370a之周圍的該P型磊晶層180或P型井180a內形成一N+ 型源極摻雜區400，其中該源極導體370a直接接觸N型摻質來源層270，最後，去除光阻圖案390，暴露出P型磊晶層180之上表面。至此，已完成垂直電晶體410結構，該結構包含閘極導體370a、閘極氧化層360、N+ 型源極摻雜區400以及N型基體摻雜區290。且該垂直電晶體410具有一通道420，其介於N+ 型源極摻雜區400以及N型基體摻雜區290之間。
接著，如第7圖所示，於晶胞區域140以及週邊耐壓區域160覆蓋一介電層430，該介電層430覆蓋住週邊耐壓區域160內之P型磊晶層180以及閘極導體370b，並進行一微影蝕刻製程，於晶胞區域140定義出至少一接觸洞440，並使接觸洞440之底部曝露出部分的P型磊晶層180或P型井180a。繼以進行一離子佈植製程，於接觸洞440之底部形成一P型重摻雜區540。接著進行退火(anneal)處理，以活化P型重摻雜區540之摻質。其中，上述P型重摻雜區540可提升金屬與半導體層接面之導電性，以利電流於接面之傳輸。
接著，如第8圖所示，於晶胞區域140以及週邊耐壓區域160沈積一金屬層550，此沈積製程可為電漿濺鍍或電子束沈積等等。同時，該金屬層550會填入接觸洞440內，而形成一源極導體560，其中，金屬層550可包含鈦(Ti)、氮化鈦(TiN)、鋁、鎢等金屬或金屬化合物。此外，於金屬層550沈積前，可先行形成一阻障層570，其組成可包含鈦、氮化鈦、鉭、氮化鉭等金屬或金屬化合物。阻障層570乃用以避免接觸洞440內之金屬層550電遷移(electro migration)或擴散至P型磊晶層180。接著，進行一微影蝕刻製程，以定義出一源極圖案550a，並繼續於週邊耐壓區域160內形成一保護層580。至此，業已完成低米勒電容之超級接面功率電晶體之製造方法。
第9圖至第11圖是根據本發明另一較佳實施例所繪示的低米勒電容之超級接面功率電晶體之製造方法示意圖。第二較佳實施例與第一較佳實施例之差別在於：於第二較佳實施例中，P型井180b並非形成於P型磊晶層180內，而是透過另一磊晶製程，俾使P型井180b形成於P型磊晶層180上方。而其它元件位置和特性，大致與第1圖至第3圖中所描述的功率元件相同，因此，下文僅針對不同之元件符號作說明，其它元件之描述，請參閱第1圖至第3圖之實施例。
如第9圖所示，首先，提供一N型汲極基底120。N型汲極基底120上定義有一晶胞區域140以及一週邊耐壓區域160，其中晶胞區域140係用於設置具有開關功能之電晶體元件，而週邊耐壓區域160係屬於阻擋晶胞區域140之高強度電場向外擴散之耐壓結構。接著，於晶胞區域140以及週邊耐壓區域160內，利用一磊晶製程於N型汲極基底120上形成一P型磊晶層180，其中，該磊晶製程可以利用一化學氣相沈積製程或其它合適方法形成。繼以全面沈積一硬遮罩層240於P型磊晶層180表面。
如第10圖所示，接著，分別於晶胞區域140以及週邊耐壓區160進行一微影蝕刻製程，於硬遮罩層240以及P型磊晶層180中形成至少一溝槽260，包括溝槽260a及溝槽260b，其中，溝槽260a設置於晶胞區域140內，而溝槽260b設置於週邊耐壓區域160內，且該些溝槽260深入至N型汲極基底120。接著，同樣於溝槽260的表面形成一緩衝層250，其中緩衝層250係以熱氧化法形成者，且其組成包含有氧化矽。接著沈積一N型摻質來源層270，例如，砷摻雜矽玻璃，使N型摻質來源層270填入溝渠260。再進行一回蝕刻製程，以去除硬遮罩層240上方之N型摻質來源層270(圖未示)，並使N型摻質來源層270之上表面略高於P型磊晶層180但略低於硬遮罩層240之表面。
如第11圖所示，去除硬遮罩層240，以暴露出P型磊晶層180之表面，然後再進行回蝕刻或化學機械研磨製程，用以去除凸出於P型磊晶層180表面的N型摻質來源層270，俾使N型摻質來源層270之表面約略與P型磊晶層180之表面切齊。接著，進行一磊晶製程，以於P型磊晶層180上方形成一P型井180b。接著，可再利用微影及蝕刻製程於P型井180b形成一凹陷結構280，曝露出N型摻質來源層270，其中，凹陷結構280之底部約略與P型磊晶層180之表面切齊。根據本較佳實施例，N型摻質來源層270之表面可幾乎與P型磊晶層180之表面切齊，因此可以提供較佳之臨界電壓特性。緊接著第11圖，後續步驟同第4圖至第8圖所示，不再重複。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
120．．．N型汲極基底
140．．．晶胞區域
160．．．週邊耐壓區域
180．．．P型磊晶層
180a．．．P型井
180b．．．P型井
240．．．硬遮罩層
250．．．緩衝層
260．．．溝槽
260a．．．溝槽
260b．．．溝槽
270．．．N型摻質來源層
280．．．凹陷結構
280a．．．凹陷結構
280b．．．凹陷結構
290．．．N型基體摻雜區
360．．．閘極氧化層
370．．．閘極導體
370a．．．閘極導體
370b．．．閘極導體
380．．．主動區域
390．．．光阻圖案
400．．．N+ 型源極摻雜區
410．．．垂直電晶體
420．．．通道
430．．．介電層
440．．．接觸洞
540．．．P型重摻雜區
550．．．金屬層
550a．．．源極圖案
560．．．源極導體
570．．．阻障層
580．．．保護層
第1圖至第8圖所繪示的是根據本發明之較佳實施例之低米勒電容之超級接面功率電晶體製造方法示意圖。
第9圖至第11圖所繪示的是根據本發明之另一較佳實施例之低米勒電容之超級接面功率電晶體製造方法示意圖。
120．．．N型汲極基底
140．．．晶胞區域
160．．．週邊耐壓區域
180．．．P型磊晶層
180a．．．P型井
250．．．緩衝層
260．．．溝槽
260a．．．溝槽
260b．．．溝槽
270．．．N型摻質來源層
280a．．．凹陷結構
280b．．．凹陷結構
290．．．N型基體摻雜區
360．．．閘極氧化層
370．．．閘極導體
370a．．．閘極導體
370b．．．閘極導體
380．．．主動區域
390．．．光阻圖案
400．．．N+ 型源極摻雜區
410．．．垂直電晶體
420．．．通道

Claims (23)

  1. 一種低米勒電容之超級接面功率電晶體製造方法，包含有：提供一N型汲極基底；於該N型汲極基底形成一P型磊晶層；於一晶胞區域內的該P型磊晶層中形成至少一溝槽；於該溝槽的表面形成一緩衝層；於該溝槽內的填入一N型摻質來源層；回蝕刻該N型摻質來源層，以於該溝槽之上端形成一凹陷結構；於該凹陷結構的表面形成一閘極氧化層，同時，使該N型摻質來源層內的N型摻質經由該緩衝層擴散至該P型磊晶層，俾形成一N型基體摻雜區；於該凹陷結構內填入一閘極導體；以及於該閘極導體周圍的該P型磊晶層內形成一N+ 型源極摻雜區。
  2. 如申請專利範圍第1項所述之低米勒電容之超級接面功率電晶體製造方法，其中該閘極導體、該閘極氧化層、該N+ 型源極摻雜區以及該N型基體摻雜區構成一垂直電晶體。
  3. 如申請專利範圍第2項所述之低米勒電容之超級接面功率電晶體製造方法，其中該垂直電晶體具有一通道，其介於該N+ 型源極摻雜區以及該N型基體摻雜區之間。
  4. 如申請專利範圍第1項所述之低米勒電容之超級接面功率電晶體製造方法，其中該溝槽深入至該N型汲極基底。
  5. 如申請專利範圍第1項所述之低米勒電容之超級接面功率電晶體製造方法，其中該緩衝層係以熱氧化法形成者。
  6. 如申請專利範圍第1項所述之低米勒電容之超級接面功率電晶體製造方法，其中該緩衝層包含有氧化矽。
  7. 如申請專利範圍第1項所述之低米勒電容之超級接面功率電晶體製造方法，其中該N型摻質層包含砷摻雜矽玻璃(arsenicsilicate glass，ASG)。
  8. 如申請專利範圍第1項所述之低米勒電容之超級接面功率電晶體製造方法，其中另包含於該P型磊晶層形成一P型井。
  9. 如申請專利範圍第8項所述之低米勒電容之超級接面功率電晶體製造方法，其中該P型井的摻雜濃度大於該P型磊晶層的摻雜濃度。
  10. 如申請專利範圍第8項所述之低米勒電容之超級接面功率電晶體製造方法，其中該凹陷結構的深度約略等於該P型井之一接面深度。
  11. 如申請專利範圍第1項所述之低米勒電容之超級接面功率電晶體製造方法，其中該閘極導體包含有多晶矽。
  12. 如申請專利範圍第1項所述之低米勒電容之超級接面功率電晶體製造方法，其中該閘極導體直接接觸該N型摻質來源層。
  13. 一種低米勒電容之超級接面功率電晶體製造方法，包含有：提供一N型汲極基底；於該N型汲極基底形成一P型磊晶層；於一週邊耐壓區域內的該P型磊晶層中形成至少一溝槽；於該溝槽的表面形成一緩衝層；於該溝槽內的填入一N型摻質來源層；回蝕刻該N型摻質來源層，以於該溝槽之上端形成一凹陷結構；於該凹陷結構的表面形成一閘極氧化層，同時，使該N型摻質來源層內的N型摻質經由該緩衝層擴散至該P型磊晶層，俾形成一N型基體摻雜區；去除該週邊耐壓區域內的該閘極氧化層；以及於該凹陷結構內填入一閘極導體。
  14. 如申請專利範圍第13項所述之低米勒電容之超級接面功率電晶體製造方法，其中該閘極導體直接接觸該P型磊晶層。
  15. 如申請專利範圍第13項所述之低米勒電容之超級接面功率電晶體製造方法，其中另包含於該P型磊晶層形成一P型井。
  16. 如申請專利範圍第15項所述之低米勒電容之超級接面功率電晶體製造方法，其中該閘極導體直接接觸該P型井。
  17. 如申請專利範圍第13項所述之低米勒電容之超級接面功率電晶體製造方法，其中該閘極導體包含有多晶矽。
  18. 如申請專利範圍第13項所述之低米勒電容之超級接面功率電晶體製造方法，其中該閘極導體直接接觸該N型摻質來源層。
  19. 如申請專利範圍第13項所述之低米勒電容之超級接面功率電晶體製造方法，其中該緩衝層係以熱氧化法形成者。
  20. 如申請專利範圍第13項所述之低米勒電容之超級接面功率電晶體製造方法，其中該緩衝層包含有氧化矽。
  21. 如申請專利範圍第13項所述之低米勒電容之超級接面功率電晶體製造方法，其中該N型摻質層包含砷摻雜矽玻璃(arsenicsilicate glass，ASG)。
  22. 如申請專利範圍第13項所述之低米勒電容之超級接面功率電晶體製造方法，其中該溝槽深入至該N型汲極基底。
  23. 如申請專利範圍第13項所述之低米勒電容之超級接面功率電晶體製造方法，其中另包含於該週邊耐壓區域形成一介電層，覆蓋住該P型磊晶層以及該閘極導體。
TW100117647A 2011-05-19 2011-05-19 低米勒電容之超級接面功率電晶體製造方法 TWI415173B (zh)

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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9614043B2 (en) 2012-02-09 2017-04-04 Vishay-Siliconix MOSFET termination trench
US9842911B2 (en) 2012-05-30 2017-12-12 Vishay-Siliconix Adaptive charge balanced edge termination
KR101504300B1 (ko) 2013-10-31 2015-03-20 메이플세미컨덕터(주) 600v급 슈퍼 정션 산화물 반도체 전계 효과 트랜지스터 및 이의 제조방법
US9887259B2 (en) 2014-06-23 2018-02-06 Vishay-Siliconix Modulated super junction power MOSFET devices
EP3183754A4 (en) 2014-08-19 2018-05-02 Vishay-Siliconix Super-junction metal oxide semiconductor field effect transistor
CN110416299B (zh) * 2018-04-28 2022-03-22 深圳尚阳通科技有限公司 超结器件及其制造方法
CN110416300B (zh) * 2018-04-28 2022-03-22 深圳尚阳通科技有限公司 超结n型mosfet及其制造方法
CN108807184B (zh) * 2018-06-25 2021-01-05 济南安海半导体有限公司 具有超级结结构的场效应晶体管及其制造方法
CN112038237B (zh) * 2020-09-10 2023-08-25 深圳市芯电元科技有限公司 一种沟槽mosfet的制造方法
US11569345B2 (en) * 2020-11-23 2023-01-31 Alpha And Omega Semiconductor (Cayman) Ltd. Gas dopant doped deep trench super junction high voltage MOSFET

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5468982A (en) * 1994-06-03 1995-11-21 Siliconix Incorporated Trenched DMOS transistor with channel block at cell trench corners
US7652326B2 (en) * 2003-05-20 2010-01-26 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6580123B2 (en) * 2000-04-04 2003-06-17 International Rectifier Corporation Low voltage power MOSFET device and process for its manufacture
US6444528B1 (en) * 2000-08-16 2002-09-03 Fairchild Semiconductor Corporation Selective oxide deposition in the bottom of a trench
KR100400079B1 (ko) * 2001-10-10 2003-09-29 한국전자통신연구원 트랜치 게이트 구조를 갖는 전력용 반도체 소자의 제조 방법
JP4176734B2 (ja) * 2004-05-14 2008-11-05 株式会社東芝 トレンチｍｏｓｆｅｔ
JP5302493B2 (ja) * 2005-03-30 2013-10-02 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 半導体装置
CN101771081B (zh) * 2009-12-18 2011-04-20 东南大学 N型超结横向双扩散半导体金属氧化物晶体管

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5468982A (en) * 1994-06-03 1995-11-21 Siliconix Incorporated Trenched DMOS transistor with channel block at cell trench corners
US7652326B2 (en) * 2003-05-20 2010-01-26 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture

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