US20090218233A1 - Method of Forming a Multilayer Structure - Google Patents

Method of Forming a Multilayer Structure Download PDF

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Publication number
US20090218233A1
US20090218233A1 US12/085,176 US8517606A US2009218233A1 US 20090218233 A1 US20090218233 A1 US 20090218233A1 US 8517606 A US8517606 A US 8517606A US 2009218233 A1 US2009218233 A1 US 2009218233A1
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Prior art keywords
layer
structures
substrate
seed layer
etching
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US12/085,176
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English (en)
Inventor
Mikael Fredenberg
Patrik Moller
Peter Wiwen-Nilsson
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Replisaurus Group Sas
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Replisaurus Technologies AB
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Assigned to REPLISAURUS TECHNOLOGIES AB reassignment REPLISAURUS TECHNOLOGIES AB ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: WIWEN-NILSSON, PETER, FREDENBERG, MIKAEL, MOLLER, PATRIK
Publication of US20090218233A1 publication Critical patent/US20090218233A1/en
Assigned to REPLISAURUS GROUP SAS reassignment REPLISAURUS GROUP SAS ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: REPLISAURUS TECHNOLOGIES AB, REPLISAURUS TECHNOLOGIES INC
Abandoned legal-status Critical Current

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    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C99/00—Subject matter not provided for in other groups of this subclass
    • B81C99/0075—Manufacture of substrate-free structures
    • B81C99/0085—Manufacture of substrate-free structures using moulds and master templates, e.g. for hot-embossing
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C23C14/3407—Cathode assembly for sputtering apparatus, e.g. Target
    • C23C14/3414—Metallurgical or chemical aspects of target preparation, e.g. casting, powder metallurgy
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D1/00—Electroforming
    • C25D1/003—3D structures, e.g. superposed patterned layers
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D1/00—Electroforming
    • C25D1/10—Moulds; Masks; Masterforms
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10—Electroplating with more than one layer of the same or of different metals
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/48—After-treatment of electroplated surfaces
    • C25D5/50—After-treatment of electroplated surfaces by heat-treatment
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • C25D7/126—Semiconductors first coated with a seed layer or a conductive layer for solar cells
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
    • C25F3/00—Electrolytic etching or polishing
    • C25F3/02—Etching
    • C25F3/14—Etching locally
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/07—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process being removed electrolytically
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0104—Tools for processing; Objects used during processing for patterning or coating
    • H05K2203/0117—Pattern shaped electrode used for patterning, e.g. plating or etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor

Definitions

  • the present invention relates to an etching and/or plating method for simplifying production of applications involving micro and nano structures in multiple layers.
  • the method is particularly useful for fabrication of PWB (printed wiring boards), PCB (printed circuit boards), MEMS (micro electro mechanical systems), IC (integrated circuit) interconnects, above IC interconnects, sensors, flat panel displays, magnetic and optical storage devices, etc.
  • PWB printed wiring boards
  • PCB printed circuit boards
  • MEMS micro electro mechanical systems
  • IC integrated circuit interconnects
  • sensors flat panel displays
  • magnetic and optical storage devices etc.
  • Different types of structures in conductive polymers, structures in semiconductors, structures in metals, and others are possible to produce using this method. Even 3D-structures in silicon, by using formation of porous silicon, are possible to produce.
  • WO 02/103085 relates to an electrochemical pattern replication method, ECPR, and a construction of a conductive electrode for production of applications involving micro and nano structures.
  • An etching or plating pattern which is defined by a conductive electrode, master electrode, is replicated on an electrically conductive material, a substrate.
  • the master electrode is put in close contact with the substrate and the etching/plating pattern is directly transferred onto the substrate by using a contact etching/plating process.
  • the contact etching/plating process is preformed in local etching/plating cells that are formed in closed or open cavities between the master electrode and the substrate.
  • Patent application US 2005/0202180 discloses electrochemical fabrication methods for forming single and multilayer mesoscale and microscale structures.
  • diamond machining e.g. fly cutting or turning
  • sacrificial and structural materials are described, which are useful in electrochemical fabrication and which can be diamond machined with minimal tool wear (e.g. Ni—P and Cu, Au and Cu, Cu and Sn, Au and Cu, Au and Sn and Au and Sn—Pb, where the first material or materials are the structural materials and the second is the sacrificial material).
  • Methods for reducing tool wear are also described when using diamond machining to planarize structures being electrochemically fabricated using difficult-to-machine materials, e.g.
  • a master electrode which may be used in the present invention, is described in Swedish patent application No. 0502539-2 entitled: “Electrode and method of forming the electrode”. The content of this patent specification is incorporated herein by reference.
  • a problem of prior art multilayer methods is the fact that during the planarization step, at least two materials are required to be removed at the same time.
  • the problem is larger if the two materials have different properties, such as if one of the material is hard, such as a metal, and the other material is soft, such as a plastics material, glass material or porous material, for example a dielectricum.
  • planarization takes place by a mechanical polishing action or chemical-mechanical polishing action, several problems may arise.
  • Such polishing action is performed by a plate which moves relative to the material to be planarized, such as by rotation, translation or rolling.
  • both soft material and hard material may be removed. This may result in that the soft material is removed at a higher rate than the hard material, known as erosion or dishing, resulting in recessions in the soft material between the hard material. The final result may be unsuitable for the following processing.
  • a further problem of prior art multilayer methods is the fact that the thickness of the structure layer may be difficult to control.
  • a yet further problem of prior art multilayer methods is the fact that it cannot fill vias or holes in the structure in an even manner.
  • Yet another problem is that it may be difficult to achieve a plane final result if the structures are relatively uneven from the start.
  • An object of the present invention is to provide a method for forming multilayer structures, in which the risk of erosion or dishing has been reduced or even eliminated.
  • a further object is to provide a method of forming multilayer structures, in which the number of steps may be reduced.
  • a still further object is to provide a method of forming multilayer structures, in which vias can be filled in a uniform manner.
  • a method of forming a multilayer structure by electroplating on a substrate comprising: a) arranging an electrically conducting seed layer on at least a part of the substrate or a substrate layer; b) applying a master electrode on said seed layer, said master electrode having an electrically conducting electrode layer, an anode material and an insulating pattern layer for forming at least one electrochemical cell comprising an electrolyte in the area enclosed by said anode material, said insulating pattern layer and said seed layer; wherein said anode material is being in electrical contact with said conducting electrode layer; c) applying a voltage between said conducting electrode layer and said seed layer so that said seed layer forms a cathode for transferring at least some of said anode material in said at least one cell to said seed layer for forming plated structures corresponding to the cavities of the insulating pattern layer on the master electrode; d) separating said master electrode from said substrate; e) removing said seed layer in non-plated areas; f) arranging
  • a method of forming a multilayer structure by electrochemical etching of a substrate comprising: a) arranging an electrically conducting seed layer on at least a part of the substrate or a substrate layer; b) applying a master electrode on said seed layer, said master electrode having an electrically conducting electrode layer and an insulating pattern layer for forming at least one electrochemical cell comprising an electrolyte in the area enclosed by said conducting electrode layer, said insulating pattern layer and said seed layer; c) applying a voltage between said conducting electrode layer and said seed layer so that said seed layer forms an anode for etching the seed layer and that said conducting electrode layer forms a cathode for depositing etched material in said at least one cell for forming etched structures corresponding to the insulating pattern layer on the master electrode; d) separating said master electrode from said substrate; e) removing possible remaining seed layer in between the etched structures; f) arranging a material in the areas between the etched structures for forming a material layer that
  • the method may further comprise: planarization of the material layer, until at least part of the structures is almost uncovered; removing further material by a removal method having substantially uniform removal rate over the entire surface until at least a part of the structures is uncovered.
  • the method may further comprise: between the steps d) and e) applying a further master electrode for forming electrochemical cells with the structures previously formed; and applying a voltage for forming a further layer of plated structures on top of the previously formed layer of structures.
  • the step of planarization may be performed by at least one polishing and/or etching step.
  • the step of polishing may comprise removing a portion of said material layer by an abrasive action.
  • the at least one polishing step may be performed by a method selected from the group comprising: mechanical-polishing, chemical-polishing, chemical-mechanical-polishing (CMP), contact planarization (CP), planarization with a doctor blade, and combinations thereof.
  • the polishing step may be performed by CMP or CP.
  • the at least one etching step may be performed by a method selected from the group comprising: dry-etching methods, ion-sputtering, reactive-ion-etching (RIE), plasma-assisted-etching, laser-ablation, ion-milling, and combinations thereof.
  • a method of forming a multilayer structure by electroplating on a substrate comprising: a) arranging an electrically conducting seed layer on at least a part of the substrate or a substrate layer; b) applying a master electrode on said seed layer, said master electrode having an electrically conducting electrode layer, an anode material and an insulating pattern layer for forming at least one electrochemical cell comprising an electrolyte in the area enclosed by said anode material, said insulating pattern layer and said seed layer; wherein said anode material is being in electrical contact with said conducting electrode layer; c) applying a voltage between said conducting electrode layer and said seed layer so that said seed layer forms a cathode for transferring at least some of said anode material in said at least one cell to said seed layer for forming plated structures corresponding to the cavities of the insulating pattern layer on the master electrode; d) separating said master electrode from said substrate; e) removing said seed layer in non-plated areas; f) arranging
  • a method of forming a multilayer structure by electrochemical etching of a substrate comprising: a) arranging an electrically conducting seed layer on at least a part of the substrate or a substrate layer; b) applying a master electrode on said seed layer, said master electrode having an electrically conducting electrode layer and an insulating pattern layer for forming at least one electrochemical cell comprising an electrolyte in the area enclosed by said conducting electrode layer, said insulating pattern layer and said seed layer; c) applying a voltage between said conducting electrode layer and said seed layer so that said seed layer forms an anode for etching the seed layer and that said conducting electrode layer forms a cathode for depositing etched material in said at least one cell for forming etched structures corresponding to the insulating pattern layer on the master electrode; d) separating said master electrode from said substrate; e) removing possible remaining seed layer in between the etched structures; f) arranging a material in the areas between the etched structures for forming a
  • the step of providing recesses in said material layer may be performed by a lithographic method selected from the group comprising: photolithography, laser lithography, E-beam lithography, nanoimprinting and combinations thereof.
  • the lithographic method may further comprise patterning an etch-mask and etching said material layer with dry-etching methods, such as ion-sputtering, reactive-ion-etching, plasma-assisted-etching, laser-ablation, ion-milling or combinations thereof.
  • the etch-mask may comprise a material selected from the group comprising: a resist, such as a photoresist; a hard-mask, such as SiN, SiO 2 , SiC, tetraethyl orthosilicate (TEOS), SiON, SiOC, SiCN:H, (non-porous) fluorine doped silicon glass (FSG), (non-porous) organic doped silicon glass (OSG), a low-k dielectric barrier/etch stop film such as BLOkTM, Pt, Ti, TiW, TiN, Al, Cr, Au, Ni, Cu, Ag, metals and by combinations thereof.
  • a resist such as a photoresist
  • a hard-mask such as SiN, SiO 2 , SiC, tetraethyl orthosilicate (TEOS), SiON, SiOC, SiCN:H, (non-porous) fluorine doped silicon glass (FSG), (non-porous) organic doped
  • the etch-mask may be dry-etched using a resist, such as a photoresist, as a mask; whereas said resist may be patterned with said lithographic method.
  • the etch-mask may be formed by said structure layer in said step c).
  • the step of arranging material in the areas between the plated or etched structures may be performed for forming a material layer having at least the thickness of two structure layers.
  • the material layer may be planarized before providing recesses.
  • the method may further comprise applying a barrier/capping layer before step a).
  • the method may further comprise applying a barrier/capping coating before step f).
  • the seed layer may be made of a material selected from the group comprising: Ru, Os, Hf, Re, Cr, Au, Ag, Cu, Sn, Ti, Ni, Al, alloys of these material, Si, conducting polymers such as polyaniline; solder materials, such as SnPb, SnAg, SnAgCu, SnCu; alloys, such as monel and permalloy; and combinations thereof.
  • the seed layer may be applied by a method selected from the group comprising: chemical-vapor-deposition (CVD), metallorganic-chemical-vapor-deposition (MOCVD), physical-vapor-deposition (PVD), atomic layer deposition (ALD), sputtering, electroless plating, electroplating, electro-grafting, and immersion deposition.
  • CVD chemical-vapor-deposition
  • MOCVD metalorganic-chemical-vapor-deposition
  • PVD physical-vapor-deposition
  • ALD atomic layer deposition
  • sputtering electroless plating, electroplating, electro-grafting, and immersion deposition.
  • the material layer may be a layer of a dielectric material and is applied by a method selected from the group comprising: spin-coating, spray-coating, powder-coating, dip-coating, roller-coating, sputtering, PVD, CVD, Plasma-Enhanced-Chemical-Vapor-Deposition (PECVD), electrodeposition, and combinations thereof.
  • a method selected from the group comprising: spin-coating, spray-coating, powder-coating, dip-coating, roller-coating, sputtering, PVD, CVD, Plasma-Enhanced-Chemical-Vapor-Deposition (PECVD), electrodeposition, and combinations thereof.
  • the dielectric material may comprise at least one layer of a material selected from the group comprising: low-k dielectric materials, ultra low-k dielectrics, dielectric materials with k-value less than 4, dielectric materials with k-value less than 2.5; organic compounds, insulating in-organic compounds, oxides, nitrides, polymer materials, polyimide, siloxane modified polyimide, BCB, SU-8, polytetrafluoroethylene (PTFE), silicones, elastomeric polymers, E-beam resists, ZEP (Sumitomo), photoresists, thinfilm resists, thickfilm resists, polycyclic olefins, polynorborene, polyethene, polycarbonate, PMMA, BARC materials, Lift-Off-Layer (LOL) materials, PDMS, polyurethane, epoxy polymers, fluoro elastomers, acrylate polymers, (natural) rubber, silicones, lacquers, nitrile rubber, EPDM
  • a method of forming a multilayer structure by electrochemical plating on a substrate wherein said substrate or said substrate layer comprises a via
  • the method comprising; a) arranging an electrically conducting seed layer on at least a part of the substrate or a substrate layer and said via; b) applying a master electrode, in which said insulating pattern layer is provided with cavities at least opposite to said vias, and wherein said cavities have a width which is slightly smaller, equal or slightly larger than the width of said via; and a predeposited anode material is arranged in said cavities; c) applying a voltage between said conducting electrode layer and said seed layer for transferring at least some parts of said anode material for forming plated structures in said vias.
  • the seed layer is made of a material selected from the group comprising: Ru, Os, Hf, Re, Cr, Au, Ag, Cu, Sn, Ti, Ni, Al, alloys of these material, Si, conducting polymers such as polyaniline; solder materials, such as SnPb, SnAg, SnAgCu, SnCu; alloys, such as monel and permalloy; and combinations thereof.
  • the seed layer may be applied by a method selected from the group comprising: chemical-vapor-deposition (CVD), metallorganic-chemical-vapor-deposition (MOCVD), physical-vapor-deposition (PVD), atomic layer deposition (ALD), sputtering, electroless plating, electroplating, electro-grafting, and immersion deposition.
  • CVD chemical-vapor-deposition
  • MOCVD metalorganic-chemical-vapor-deposition
  • PVD physical-vapor-deposition
  • ALD atomic layer deposition
  • sputtering electroless plating, electroplating, electro-grafting, and immersion deposition.
  • a method of forming a structure by electrochemical plating on a substrate provided with a conducting material structure comprising: a) arranging an electrically conducting seed layer on at least a part of the substrate; b) applying a master electrode on said seed layer, said master electrode having an electrically conducting electrode layer, an anode material and an insulating pattern layer for forming at least one electrochemical cell comprising an electrolyte in the area enclosed by said anode material, said insulating pattern layer and said seed layer, said cavity enclosing at least a part of said conducting material structure; wherein said anode material is being in electrical contact with said conducting electrode layer; c) applying a voltage between said conducting electrode layer and said seed layer so that said seed layer forms a cathode for transferring at least some of said anode material in said at least one cell to said seed layer for forming plated structures onto said seed layer and said conducting material structures corresponding to the cavities of the insulating pattern layer on the master electrode; d
  • the method may further comprise: b1) applying a further master electrode on said seed layer, said master electrode having an electrically conducting electrode layer, an anode material and an insulating pattern layer for forming at least one electrochemical cell comprising an electrolyte in the area enclosed by said anode material, said insulating pattern layer and said seed layer, said cavity enclosing at least a part of said conducting material structure and plated structures; wherein said anode material is being in electrical contact with said conducting electrode layer; c1) applying a voltage between said conducting electrode layer and said seed layer so that said seed layer forms a cathode for transferring at least some of said anode material in said at least one cell to said seed layer for forming plated structures onto said seed layer and said conducting material structures and plated structures corresponding to the cavities of the insulating pattern layer on the master electrode; d1) separating said master electrode from said substrate.
  • the method may further comprise: e) removing said seed layer in non-plated areas.
  • the planarization step may comprise performing a polishing step until said material surface is substantially planar and a subsequent etching step of said material surface until at least part of said structures is uncovered.
  • a planarizing material may be applied into said material layer prior to performing said planarization step of said material layer.
  • the planarizing material may be applied with a method selected from the group comprising: spin-coating, spray-coating, powder-coating, dip-coating, roller-coating, sputtering, PVD, CVD, PECVD, electrodeposition, and combinations thereof.
  • an end-point detection method may be used so as to determine when said planarization step is completed.
  • the end-point detection method may be selected from the group comprising: detecting when said structure material is being abraded or etched; determining the height of said material layer; and analyzing the color of said material layer.
  • the detection may be based on interferometry of spectral analysis of said abraded material or said height is being determined by laser measurements or said color of said material is analyzed by using a sensor and a camera.
  • the step of contact planarization may comprise: applying a plate above said material layer and applying a pressure on said plate for equalizing the material in said material layer, while in a flowable condition.
  • the flowable condition may be obtained by heating said material layer, whereupon the material is cooled after planarization.
  • the step of applying the plate is performed before curing said material, whereupon the material is cured after planarization, such as by applying infrared or ultraviolet radiation.
  • the seed layer is applied by a method selected from the group comprising: chemical-vapor-deposition (CVD), metallorganic-chemical-vapor-deposition (MOCVD), physical-vapor-deposition (PVD), atomic layer deposition (ALD), sputtering, electroless plating, electroplating, electro-grafting, immersion deposition, and combinations thereof.
  • CVD chemical-vapor-deposition
  • MOCVD metalorganic-chemical-vapor-deposition
  • PVD physical-vapor-deposition
  • ALD atomic layer deposition
  • sputtering electroless plating, electroplating, electro-grafting, immersion deposition, and combinations thereof.
  • the method further comprises applying a barrier/capping layer before step a) and/or before step f).
  • the barrier/capping material may comprise at least one layer of material that prevents corrosion, diffusion or electromigration of layers, which are interfacing with said barrier/capping material.
  • the barrier/capping material may be selected from the group comprising: Ti, TiN, TiW, Cr, Ni, NiB, NiP, NiCo NiBW, NiM-P, Pd, Pt, Au, Ag, W, Ru, Ta, TaN, Re, Os, Hf, Rh, Wo, Co, CoReP, CoP, CoWP, CoWB, CoWBP, alloys thereof and combinations thereof.
  • the barrier/capping material may be applied by a method selected from the group comprising: electrodeposition, MOCVD, CVD, PVD, ALD, sputtering, electroless deposition, immersion deposition, electrografting and combinations thereof.
  • the barrier/capping material may be applied with a mask-less selective deposition method, such as electroless deposition, wherein deposition is obtained only in surfaces active to said deposition process, such as on said structure layer and not on said arranged material layer.
  • the said barrier/capping material may be used as a seed layer in said step a).
  • the seed layer may be made of a material selected from the group comprising: Ru, Os, Hf, Re, Cr, Au, Ag, Cu, Sn, Ti, TiN, TiW, Ni, NiB, NiP, NiCo NiBW, NiM-P, Al, Pd, Pt, W, Ta, TaN, Rh, Wo, Co, CoReP, CoP, CoWP, CoWB, CoWBP alloys of these material, Si, conducting polymers such as polyaniline; solder materials, such as SnPb, SnAg, SnAgCu, SnCu; alloys, such as monel and permalloy; and alloys thereof and combinations thereof.
  • the seed layer may be cleaned and activated, wherein said cleaning and activation comprise using organic solvents, such as acetone or alcohols; and/or inorganic solvents, such as nitric acid, sulfuric acid, phosphoric acid, hydrochloric acid, acetic acid, hydrofluoric acid; strong oxidizing agents, such as peroxides, such as hydrogen-peroxide; persulfates, such as sodium-persulfate or ammonium-persulfate; ferric-chloride; and/or oxygen plasma; argon plasma; hydrogen plasma; and/or by mechanically removing impurities.
  • organic solvents such as acetone or alcohols
  • inorganic solvents such as nitric acid, sulfuric acid, phosphoric acid, hydrochloric acid, acetic acid, hydrofluoric acid
  • strong oxidizing agents such as peroxides, such as hydrogen-peroxide
  • persulfates such as sodium-persulfate or ammonium-persulfate
  • the method may further comprise applying an adhesion layer before applying said seed layer and/or before applying said barrier/capping material; wherein said adhesion layer increase the adhesion of said seed layer or barrier/capping layer to said arranged material layer or structures.
  • the adhesion layer may comprise at least one material selected from the group comprising: Cr, Ti, TiW, AP-3000 (Dow Chemicals), AP-100 (Silicon Resources), AP-200 (Silicon Resources), AP-300 (Silicon Resources) and combinations thereof.
  • the forming of at least one electrochemical cell comprises a method for aligning said insulating pattern layer to a patterned layer on said substrate.
  • the aligning method may comprise using alignment marks on the front side and/or backside of said master electrode, which marks are aligned to corresponding alignment marks on said substrate.
  • the aligning method may be performed prior to forming at least one electrochemical cell.
  • the formed electrochemical cell may comprise a solution of cations, such as copper or nickel ions, and anions, such as sulfate ions, for electrochemical etching and/or plating.
  • the electrolyte may comprise suppressors, levelers and/or accelerators, for instance PEG (poly-ethylene glycol) together with chloride ions and/or with SPS (bis-(3-sulfopropyl)-disulfide), MPSA and/or sodium-lauryl-sulphate.
  • PEG poly-ethylene glycol
  • SPS bis-(3-sulfopropyl)-disulfide
  • MPSA bis-(3-sulfopropyl)-disulfide
  • sodium-lauryl-sulphate for instance PEG (poly-ethylene glycol) together with chloride ions and/or with SPS (bis-(3-sulfopropyl)-disulfide), MPSA and/or sodium-lauryl-sulphate.
  • the structure layer may be a material selected from the group comprising: Au, Ag, Ni, Cu, Sn, Pb, SnAg, SnAgCu, AgCu and combinations thereof.
  • the structure layer may comprise Cu or Ni.
  • the anode material may be arranged onto said conducting electrode layer in the cavities of said insulating pattern layer using a method selected from the group comprising: electroplating, electroless plating, immersion plating, CVD, MOCVD, powder-coating, chemical grafting, electrografting and combinations thereof.
  • the method for arranging said anode material may comprise electroplating or electroless plating.
  • the forming of structures is stopped, by disconnecting said voltage, prior to dissolving all or substantially of the anode material. At least 5% of the anode material may be remaining when said forming of structures is stopped.
  • the depth of said etched structures or the thickness of said plated structures may be controlled by monitoring the time and current passing through said at least one electrochemical cell.
  • the separation step d) may be performed by holding said substrate in a fixed position and moving said master electrode in a direction perpendicular to the substrate surface; or by holding said master electrode in a fixed position and moving said substrate in a direction perpendicular to the master electrode surface; or by performing the separation in a less parallel manner so as to ease the separation; or by a combination thereof.
  • the step e) removing said seed layer may be performed by wet-etching, dry-etching, electrochemical etching or by combinations thereof.
  • the method further comprises applying a protective coating which is covering all or substantially all of said seed layer, barrier/capping layer and/or structure layer; treating said protective coating with an anisotropic etch, thereby uncovering the top of said seed layer, barrier/capping layer and/or structure layer between the structures while leaving a protective layer on the side walls of said structures; removing said seed layer and/or barrier layer between said structures.
  • the material layer may be at least one layer of a dielectric material and may be applied by a method selected from the group comprising: spin-coating, spray-coating, powder-coating, dip-coating, roller-coating, sputtering, PVD, CVD, Plasma-Enhanced-Chemical-Vapor-Deposition (PECVD), electrodeposition, and combinations thereof.
  • the material layer may be at least one layer of a metal and may be applied by a method selected from the group comprising: electrodeposition, MOCVD, CVD, PVD, ALD, sputtering, electroless deposition, immersion deposition, electrografting and combinations thereof.
  • the dielectric material may comprise at least one layer of a material selected from the group comprising: low-k dielectric materials, ultra low-k dielectrics, dielectric materials with k-value less than 4, dielectric materials with k-value less than 2.5; organic compounds, insulating in-organic compounds, oxides, nitrides, polymer materials, polyimide, siloxane modified polyimide, BCB, SU-8, polytetrafluoroethylene (PTFE), silicones, elastomeric polymers, E-beam resists, ZEP (Sumitomo), photoresists, thinfilm resists, thickfilm resists, polycyclic olefins, polynorborene, polyethene, polycarbonate, PMMA, BARC materials, Lift-Off-Layer (LOL) materials, PDMS, polyurethane, epoxy polymers, fluoro elastomers, acrylate polymers, (natural) rubber, silicones, lacquers, nitrile rubber, EPDM
  • the method further comprises: arranging an etch-stop layer on top of the structures before the step f) of arranging the material.
  • the etch-stop layer may comprise at least one layer of a material selected from the group comprising: SiC, SiN, films, low-k dielectric barrier/etch stop films, such as BLOkTM; Ti, TiN, TiW, Cr, Ni, NiB, NiP, NiCo NiBW, NiM-P, Pd, Pt, Au, Ag, W, Ru, Ta, TaN, Re, Os, Hf, Rh, Wo, Co, CoReP, CoP, CoWP, CoWB, CoWBP, alloys thereof and combinations thereof.
  • the material layer may be a porous low-k dielectric material and a pore sealing operation may be performed prior to applying further layers of material onto it.
  • the material layer may be a sacrificial polymer, wherein said sacrificial polymer is being decomposed into gaseous phase when treated with heat or radiation.
  • the sacrificial polymer may be a copolymer of butylnorbornene and triethoxysilyl norbornene, such as Unity Sacrificial PolymerTM (Promerus).
  • the method may further comprise: forming a structure layer before step h); wherein forming a structure layer may comprise lithography methods; deposition methods such as electrodeposition, electroless deposition; wet-etching or dry-etching methods.
  • FIGS. 1( a ) to 1 ( h ) are schematic cross-sectional views disclosing several method steps of a first embodiment comprising etching.
  • FIGS. 2( a ) to 2 ( p ) are schematic cross-sectional views disclosing several method steps of a second embodiment comprising plating.
  • FIGS. 3( a ) to 3 ( l ) are schematic cross-sectional views disclosing several method steps of a third embodiment comprising etching and in which a dielectric material layer is applied with a thickness of two layers.
  • FIGS. 4( a ) to 4 ( m ) are schematic cross-sectional views disclosing several method steps of a fourth embodiment comprising plating and in which a dielectric material layer is applied with a thickness of two layers.
  • FIGS. 5( a ) to 5 ( l ) are schematic cross-sectional views disclosing several method steps of a fifth embodiment comprising plating and in which a dielectric material layer is applied with a thickness of two layers followed by plating also with a thickness of two layers.
  • FIGS. 6( a ) to 6 ( n ) are schematic cross-sectional views disclosing several method steps of a sixth embodiment comprising plating and in which a dielectric material layer is planarized in two steps.
  • FIGS. 7( a ) to 7 ( b ) are schematic cross-sectional views disclosing method steps of a seventh embodiment comprising plating and in which a via is filled with plating material.
  • FIGS. 8( a ) to ( b ) are schematic cross-sectional views disclosing method steps of an eight embodiment comprising plating and in which a via is filled with plating material.
  • FIGS. 9( a ) to ( c ) are schematic cross-sectional views disclosing method steps of a ninth embodiment comprising plating and in which a via is filled with plating material.
  • FIGS. 10( a ) to ( c ) are schematic cross-sectional views disclosing method steps of a tenth embodiment comprising plating and in which a via is filled with plating material.
  • FIGS. 11( a ) to ( c ) are schematic cross-sectional views disclosing method steps of an eleventh embodiment comprising plating and in which a via is filled with plating material.
  • FIGS. 12( a ) to ( b ) are schematic cross-sectional views disclosing method steps of a twelfth embodiment comprising plating and in which a via is filled with plating material.
  • FIGS. 13( a ) to ( c ) are schematic cross-sectional views disclosing method steps of a thirteenth embodiment comprising plating and in which a via is filled with plating material.
  • FIGS. 14( a ) to ( c ) are schematic cross-sectional views disclosing method steps of a fourteenth embodiment comprising plating and in which a via is filled with plating material.
  • FIGS. 15( a ) to ( b ) are schematic cross-sectional views disclosing method steps of a fifteenth embodiment comprising plating and in which a conducting or non-conducting material is enclosed by a plating material.
  • FIGS. 16( a ) to ( d ) are schematic cross-sectional views disclosing method steps of a sixteenth embodiment comprising plating and in which a conducting or non-conducting material is enclosed by a plating material.
  • FIGS. 17( a ) to ( h ) are schematic cross-sectional views disclosing different embodiments of a master electrode.
  • FIG. 18 is a schematic flow scheme of the method steps of a conventional lithographic and electroplating process.
  • FIG. 19 is a schematic flow scheme of the method steps of the inventive method.
  • FIG. 20 ( a ) to ( b ) are schematic cross-sectional views disclosing an electrode having no predeposited material and en electrode having predeposited material, respectively.
  • the method steps comprises one or several of the following six steps, namely:
  • a substrate is prepared by applying a seed layer on top of said supplied substrate.
  • a barrier/capping and/or adhesion layer is deposited on the substrate prior to applying the seed layer or arranged below the seed layer before being applied on the substrate.
  • Said seed layer comprises at least one, normally relatively thin layer of conducing material onto which material, such as predeposited anode material in the master electrode, can be plated with the ECPR plating process.
  • the seed layer comprises at least one, normally relatively thick layer of conducing material in which structures can be etched with the ECPR etching process.
  • the seed layer forms one of the electrodes of the electrochemical cell, the seed layer must be applied at least where a cell is to be formed. Moreover, the seed layer must be able to be electrically contacted from the outside of the substrate or through conducting parts of the substrate, which is connected with the seed layer, or via the master electrode. Thus, the seed layer can be arranged covering only the required surfaces. However, the seed layer can be applied over the entire surface of the substrate to be acted upon.
  • the seed layer can be comprised of one or several layers of any of the materials Ru, Os, Hf, Re, Cr, Au, Ag, Cu, Sn, Ti, Ni, Al, alloys of these material, Si, other metals such as used for barrier/capping and/or adhesion layers mentioned below, conducting polymers such as polyaniline, solder materials such as SnPb, SnAg, SnAgCu, SnCu, alloys such as monel or permalloy and/or combinations thereof.
  • the seed layer can be applied by chemical-vapor-deposition (CVD), metallorganic-chemical-vapor-deposition (MOCVD), physical-vapor-deposition (PVD), atomic layer deposition (ALD), sputtering, electroless plating, electroplating, electro-grafting, immersion deposition and/or by other processes including applying layers of conducting material.
  • CVD chemical-vapor-deposition
  • MOCVD metalorganic-chemical-vapor-deposition
  • PVD physical-vapor-deposition
  • ALD atomic layer deposition
  • sputtering electroless plating
  • electroplating electro-grafting
  • immersion deposition immersion deposition and/or by other processes including applying layers of conducting material.
  • electroplating may be used to form a layer having a relatively uniform upper surface independent on any recesses in the substrate surface.
  • a uniform upper surface can be achieved by using additives such as suppressors, levelers, accelerators and/or wetting agents, for instance PEG (poly-ethylene glycol) and chloride ions, SPS (bis-(3-sulfopropyl)-disulfide) and/or sodium-lauryl-sulphate used for copper plating, that increase the electrodeposition speed in the recess and/or by using pulse plating, for instance pulse-reverse-plating which also evens out height differences in the deposited layer.
  • a uniform upper surface can be achieved independent on any recess in the substrate, specifically if the thickness of the seed layer is significantly larger than the depth of the recesses.
  • the seed layer of the substrate can be cleaned and activated before usage in the ECPR process.
  • the cleaning method can include the use of organic solvents e.g. acetone or alcohols; and/or inorganic solvents e.g. nitric acid, sulfuric acid, phosphoric acid, hydrochloric acid, acetic acid, hydrofluoric acid, strong oxidizing agents, e.g. peroxides, persulfates, ferric-chloride, and/or de-ionized water.
  • Cleaning can also be performed by applying oxygen plasma, argon plasma and/or hydrogen plasma or by mechanically removing impurities. Activation of the seed layer surface can be performed with solutions removing oxides, e.g.
  • sulfuric acid nitric acid, hydrochloric acid, hydrofluoric acid, phosphoric acid and etchants, e.g. sodium-persulfate, ammonium-persulfate, hydrogen-peroxide, ferric-chloride and/or other solutions comprising oxidizing agents.
  • etchants e.g. sodium-persulfate, ammonium-persulfate, hydrogen-peroxide, ferric-chloride and/or other solutions comprising oxidizing agents.
  • Said barrier/capping layer can be comprised of at least one layer of at least one material or a combination of materials that: prevents said conducting material from corrosion; prevents said conducting material from diffusing into interfacing materials; prevents electro-migration and/or prevents other phenomena having negative effect on the electrical properties of the manufactured substrate.
  • the barrier/capping layer can be comprised of Ti, TiN, TiW, Cr, Ni, NiB, NiP, NiCo NiBW, NiM-P, Pd, Pt, Au, Ag, W, Ru, Ta, TaN, Re, Os, Hf, Rh, Wo, Co, CoReP, CoP, CoWP, CoWB, CoWBP, alloys thereof and/or combinations thereof.
  • Said adhesion layer can be comprised of material or a combination of materials that increase the adhesion of the conducting seed layer material or barrier/capping material to the dielectric layer.
  • the adhesion layer can be comprised of Cr, Ti, TiW, AP-3000 (Dow Chemicals), AP-100 (Silicon Resources), AP-200 (Silicon Resources) and/or AP-300 (Silicon Resources).
  • the adhesion layer can in some embodiments also function as a catalytic layer facilitating and/or improving the deposition of the seed layer.
  • the barrier/capping and/or adhesion layers can be applied by using deposition methods such as electrodeposition, MOCVD, CVD, PVD, ALD, sputtering, electroless deposition, immersion deposition, electrografting and/or other deposition methods suitable for the barrier/capping and/or adhesion materials.
  • deposition methods such as electrodeposition, MOCVD, CVD, PVD, ALD, sputtering, electroless deposition, immersion deposition, electrografting and/or other deposition methods suitable for the barrier/capping and/or adhesion materials.
  • the barrier/capping layer and/or adhesion layer can, in some embodiments, be applied with a mask-less selective deposition process such as electroless deposition and/or chemical grafting, whereby deposition is obtained only on surfaces active in relation to said deposition processes, for instance on a structure layer and not on a dielectric layer.
  • a mask-less selective deposition process such as electroless deposition and/or chemical grafting, whereby deposition is obtained only on surfaces active in relation to said deposition processes, for instance on a structure layer and not on a dielectric layer.
  • the seed layer also functions as a barrier/capping layer, for instance when applying a Ru layer.
  • a barrier/capping layer can be used as a seed layer.
  • said barrier/capping layer needs to be activated in order to function as a seed layer.
  • Such surface activation can be Sn, or Pd activation, for instance by treating the surface with a PdCl 2 and/or SnCl 2 solution.
  • a solution for Pd activation can be PdCl 2 in diluted HCl.
  • HF is added to the activation solution, for instance when activating a TiN barrier/capping layer.
  • a master electrode comprising an electrically conducting electrode layer, of at least one inert material, such as platinum, and an insulating pattern layer, is put in close physical contact with the conducting top layer, such as the seed layer, on the substrate in the presence of an electrolyte, forming electrochemical cells, filled with electrolyte, defined by the cavities of the insulating structures on the master.
  • Putting the master in close contact with the top layer on the substrate includes aligning the master electrode insulating pattern to the patterned layer on the substrate.
  • This step can include the use of alignment marks on the front side or backside of the master electrode that can be aligned to the corresponding alignment marks on the substrate. The alignment procedure can be performed before or after applying the electrolyte.
  • Predeposited anode material may previously be arranged onto said conducting electrode layer in the cavities of the insulating pattern layer prior to putting the master in contact with a substrate.
  • Predeposited material in the master electrode cavities can be cleaned and activated in advance, in the same manner as described for the substrate seed layer in the first step “(a)”, before putting the master into contact with the substrate.
  • Said electrolyte comprises a solution of cations and anions appropriate for electrochemical etching and/or plating, such as conventional electroplating baths.
  • a copper sulphate bath can be used, such as an acidic copper sulphate bath.
  • additives can be used, such as suppressors, levellers and/or accelerators, for instance PEG and chloride ions and/or SPS.
  • a Watt's bath can be used.
  • Appropriate electrolyte systems for different materials of ECPR etched or plated structures are described in: Lawrence J. Durney, et al, Electroplating Engineering Handbook, 4th ed., (1984).
  • a third step (c) structures of conducting material are formed using ECPR etching or plating by applying a voltage, using an external power source, to the master electrode and to the seed layer on the substrate for creating an electrochemical process simultaneously inside each of the electrochemical cells defined by the cavities of the master electrode and the top layer on the substrate.
  • the voltage is applied in such a manner that the seed layer on the substrate is anode and the conducting electrode layer in the master electrode is cathode, the seed layer material is dissolved and at the same time material is deposited inside the cavities of the master electrode.
  • the grooves created by dissolving the seed layer separate the remaining structures of the seed layer.
  • the structures formed from the remaining seed layer is a negative image of the cavities of the insulating pattern layer of the master electrode; and these structures are referred to as “ECPR etched structures” below in this description.
  • the predeposited anode material inside the cavities of the master electrode is dissolved and at the same time material is deposited on the conducting layer on the substrate in the cavities that are filled with electrolyte.
  • the deposited material on the conducting layer on the substrate forms structures that are a positive image of the cavities of the insulating pattern layer of the master electrode; and these structures are referred to as “ECPR plated structures” below in this description.
  • Said ECPR etched or ECPR plated structures can be comprised of conducting materials, such as metals or alloys, for instance Au, Ag, Ni, Cu, Sn, Pb and/or SnAg, SnAgCu, AgCu and/or combinations thereof, for example Cu.
  • conducting materials such as metals or alloys, for instance Au, Ag, Ni, Cu, Sn, Pb and/or SnAg, SnAgCu, AgCu and/or combinations thereof, for example Cu.
  • said anode material is predeposited in the cavities of the master electrode by using ECPR etching of a material, which is anode, and depositing said material onto the conducting electrode, which is cathode, in the cavities of the insulating pattern layer of the master electrode.
  • said anode material is predeposited by regular electroplating, electroless plating, immersion plating, CVD, MOCVD, (charged) powder-coating, chemical grafting and/or electrografting said material selectively onto the conducting electrode layer in the cavities of the insulating pattern layer of the master electrode.
  • the voltage can be applied in a manner that improves the uniformity and/or properties of the etched and/or plated structures.
  • the applied voltage can be a DC voltage, a pulsed voltage, a square pulsed voltage, a pulse reverse voltage and/or a combination thereof.
  • the uniformity of the etched and/or plated structures can be increased by choosing an optimized combination of applied voltage waveform, amplitude and frequency.
  • the etch depth or plating height can be controlled by monitoring the time and the current passing through the master electrode. If the total electrode area is known, the current density can be predicted from the current passing through the electrode area. The current density corresponds to an etching or plating rate and hence the etching depth or plating height can be predicted from the etching or plating rate and time.
  • the etching or plating process is stopped by disconnecting the applied voltage before reaching the underlying surface of the dissolving anode material.
  • the plating process this means that the process is stopped when a layer of predeposited anode material still remains, such as 5% to 50%, covering the conducting electrode layer. Otherwise, uneven current distribution may occur in the respective electrochemical cells.
  • the desired height of the plated structures is significantly less than the thickness of the predeposited anode material. This implies that several layers of structures can be plated onto one or several substrates before having to predeposit new anode material. In some examples the height of the predeposited material can be at least twice as thick as the height of the plated structures.
  • multiple layers of ECPR plated structures are applied directly onto each other.
  • a fourth step (d) after the ECPR etched or plated structures are formed the master is separated from the substrate in a manner that minimizes damages on the master or on the ECPR etched or plated structures on the substrate.
  • the method can be performed by holding the substrate in a fixed position and moving the master electrode in a direction perpendicular to the substrate surface or by holding the master electrode in a fixed position and moving the substrate in a direction perpendicular to the master electrode surface.
  • the separation can be performed in a less parallel manner in order to ease the separation.
  • a fifth step (e) after ECPR plating the seed layer on the substrate is removed so that the deposited structures are not connected to each other by the seed layer.
  • the seed layer removing step can include applying wet etching chemicals suitable for globally etching the materials that the seed layer is comprised of.
  • An anisotropic etching method can be used in order to avoid or reduce the etching of the sidewalls and/or undercutting of the ECPR plated structures.
  • the seed layer can be removed with dry-etching, for instance ion-sputtering, reactive-ion-etching (RIE), plasma-assisted-etching, laser-ablation, ion-milling. Dry-etching may remove the material by evaporation and removal in gaseous form.
  • the seed layer can be removed by a combination of dry-etching and wet-etching methods. For instance, a dry-etching method can sometimes leave residues or bi-products from etching the seed layer. These residues or bi-products can in some embodiments be removed by wet-etching methods.
  • said seed layer removing step can include electrochemical etching methods by applying a voltage making the seed layer anode and thereby dissolving (etching) at least some portions of said seed layer.
  • Said electrochemical etching methods can in some embodiments include ECPR etching of at least some portions of the seed layer.
  • a protective coating is applied uniformly all over said ECPR etched or plated structures; said protective coating is treated with an anisotropic etch, said etch having the property of etching with a higher rate in a vertical direction than in lateral direction such as said dry-etching methods, thereby uncovering the top of said structures and/or the seed layer between the structures while leaving a protective layer on the side walls of said structures.
  • the seed layer can be removed using said etching methods without etching the side walls and/or creating corner rounding of the ECPR etched or plated structures.
  • Said protective coating can comprise materials, and can be applied with methods, such as used for an etch-mask layer described below.
  • Said protective coating on the sidewalls of said structures can be removed after finishing the seed layer etching.
  • a barrier/capping layer and/or adhesion layer have been applied on the substrate prior to applying the seed layer, these layers can be removed in the areas between the ECPR etched or plated structures using the same methods as mentioned above for the seed layer.
  • the seed layer, barrier/capping layer and/or adhesion layer are comprised of materials that can be selectively etched in relation to the material of the ECPR plated structures.
  • said seed layer, barrier/capping layer and/or adhesion layer can be treated with methods converting said layers into insulating material.
  • Such methods can for instance include: electrochemical anodization, such as anodizing a Ti layer to TiO 2 ; thermal and/or plasma based treatment in an environment including gases or precursors, such as nitrogen and/or oxygen, that converts said layers into insulating layers; and/or chemical treatment for instance by strong oxidizing agents, such as peroxides and/or hydroxides.
  • electrochemical anodization such as anodizing a Ti layer to TiO 2
  • thermal and/or plasma based treatment in an environment including gases or precursors, such as nitrogen and/or oxygen, that converts said layers into insulating layers
  • chemical treatment for instance by strong oxidizing agents, such as peroxides and/or hydroxides.
  • said layers being converted into insulating layers do not necessarily have to be removed.
  • remaining material deposited inside the cavities of the master electrode can be removed using the same methods as for removing the seed layer on the substrate.
  • the remaining material can in some embodiments also be removed by regular plating and/or ECPR plating onto a cathode and/or dummy substrate, respectively. In some embodiments this is done prior to using the master electrode in another ECPR etching step or prior to predepositing new material inside the cavities of the master used for the ECPR plating step.
  • plating only a portion of the predeposited material may be used in a single procedure and another portion of the predeposited material may be used in the next procedure, for a number of procedures.
  • the material deposited on the cathode, i.e. the master electrode may not need to be removed between each procedure, but may be removed between each second, third, etc., procedure.
  • a dielectric layer is applied onto the top layer of the substrate.
  • a barrier/capping layer and/or adhesion layer are applied onto the top layer of the substrate prior to applying said dielectric layer in order to improve the adhesion properties and/or prevent contamination, migration (electromigration) and/or diffusion of material; said barrier/capping layer and/or adhesion layer may be comprised of materials mentioned above and can be applied with methods described above.
  • said barrier/capping and/or adhesion layer can comprise materials such as for an etch-stop layer described below.
  • Said dielectric layer can comprise one or several layers of materials with low dielectric constants.
  • the dielectric layer can be applied by spin-coating, spray-coating, powder-coating, dip-coating, roller-coating, sputtering, PVD, CVD, Plasma-Enhanced-Chemical-Vapor-Deposition (PECVD), electrodeposition, by other suitable deposition processes and/or by combinations thereof.
  • the dielectric layer can be applied so that it completely covers the ECPR etched or plated structures as well as fills up the cavities.
  • the layer is applied as uniformly as possible in order to avoid or minimize the use of a planarization process.
  • a process can be performed to uncover the top of at least some parts of said structures from the dielectric layer. In an embodiment this is done by planarizing the dielectric layer to the same level as the top of said structures. Said planarization can be done by polishing and/or etching methods.
  • the polishing methods can be mechanical and/or chemical.
  • chemical-mechanical-polishing (CMP) can be used.
  • CMP includes planarizing the dielectric material using a mechanical force from a rotating or translating polishing pad together with a chemical component from a polishing slurry that is applied on the polishing pad which is put in close contact with the dielectric material or directly onto the material.
  • the slurry chemistry is relevant for proper polishing.
  • It can consist of micro or nano sized silica or aluminum particles in a carrier solution.
  • a chemical reaction occurs at the dielectric surface, which makes the surface susceptible to mechanical abrasion by the particles suspended in the slurry.
  • the abraded particles are then swept away from the vicinity of the substrate surface and flushed from the system as fresh slurry is added and used slurry is removed from the system.
  • Another planarization method is to use a doctor blade.
  • a further planarization method is contact planarization (CP), which comprises applying a force or a pressure with a planar disc, which for instance is comprised of silicon, glass and/or quartz, onto a layer thereby reducing the unevenness of the layer surface.
  • CP contact planarization
  • a planarizing material layer is applied onto the dielectric layer prior to using said planarization methods.
  • the planarizing material layer results in a more planar surface, than of the underlying layer, when applied.
  • Said planarizing material layer can be applied with methods such as spin-coating, spray-coating, powder-coating, dip-coating, roller-coating, sputtering, PVD, CVD, PEVCD, electrodeposition and/or by combinations thereof.
  • the dielectric material and/or said planarization material layer is not cured prior to using said planarization methods which means that the material is in a more or less soft or flowable condition so that the material moves and planarize under the influence of the pressure.
  • said planar disc can be optically transparent, and UV-light and/or heat radiation can pass there through and be applied in order to cure said planarization material layer and/or dielectric layer.
  • the dielectric and/or planarizing material layer is brought into contact with said planar disc without applying a pressure.
  • the dielectric and/or planarizing material layer can be heated (for example above the glass temperature T g ) followed by applying a mechanical force by the planar disc onto the dielectric and/or planarizing material layer during sufficient time for planarization to occur.
  • the heating may occur by having the disc at an elevated temperature or heating the disc.
  • the dielectric and/or planarizing material layer can be cooled (for example below T g ) and the planar disc can be removed from the planarized surface.
  • planarization using said etching methods include dry-etching methods such as ion-sputtering, reactive-ion-etching (RIE), plasma-assisted-etching, laser-ablation, ion-milling and/or combinations thereof.
  • Said etching methods may give a uniform etching rate over the entire surface that is planarized.
  • Planarization can in some embodiments be preformed by combining different planarization methods. In some cases it can be suitable first to use CMP and/or CP to planarize the top surface and then use said etching methods to further planarize or further remove said planarizing material layer and/or dielectric layer until it uncovers the top of the ECPR etched or ECPR plated structures.
  • the etching may be global or only affect the dielectric material. For instance, the planarization speed can be significantly higher on the dielectric material than on the ECPR etched or plated structures. This minimizes the amount of abraded material from the ECPR etched or plated structures during said planarization step.
  • the structure material or metal may include an etch-stop layer or coating for preventing etching thereof. The etching can be continued until all structure portions are uncovered. The etching can be further continued in order to ensure that all structure portions are safely uncovered, such as less than about 20% extra, for example less than about 10%, for instance less than about 1%.
  • end-point detection can be used to determine when said etching or planarization method is completed.
  • the end-point detection method can comprise the use of a sensor that detects when the material of the ECPR etched or plated structures is being abraded and/or etched by said planarization methods.
  • the detection can be based on interferometry or spectral analysis of the etching plasma that detects molecules or atoms of the ECPR etched or ECPR plated structures, which are abraded/etched by said etching or planarization methods.
  • Other end detection methods may be used such as laser measurement of the height of the layer.
  • Yet further end-point detection methods can include a sensor for analysis of the color of the planarized material, such as by using a camera, for example an LCD-camera.
  • the tops of at least some parts of said structures are uncovered from the dielectric layer, which covers at least some parts of the structures, by patterning said dielectric layer with for example a lithographic process.
  • Said lithographic process can be photolithography, laser lithography, E-beam lithography, nanoimprinting or other lithographic processes suitable for the dielectric material.
  • etch-mask at least some parts of the top of said structures as delimited by an etch-mask, are uncovered by dry-etching the dielectric layer with methods such as ion-sputtering, reactive-ion-etching (RIE), plasma-assisted-etching, laser-ablation, ion-milling.
  • RIE reactive-ion-etching
  • the patterned material used as an etch-mask for the dry-etching process can be a photoresist and/or another polymer material that can be patterned by said lithographic processes.
  • the etch-mask material for dry-etching the dielectric layer can also comprise materials such as SiN, SiO 2 , SiC, tetraethyl orthosilicate (TEOS), SiON, SiOC, SiCN:H, (non-porous) fluorine doped silicon glass (FSG), (non-porous) organic doped silicon glass (OSG), a low-k dielectric barrier/etch stop film such as BLOkTM (Applied Materials), Pt, Ti, TiW, TiN, Al, Cr, Au, Ni, Cu, Ag, other metals, other hard materials and/or combinations thereof.
  • TEOS tetraethyl orthosilicate
  • FSG fluorine doped silicon glass
  • OSG organic doped silicon glass
  • BLOkTM Applied Materials
  • the etch-mask material can in turn be etched using a patterned photoresist and/or another resist, which is patterned with said lithographic processes, as a mask.
  • the etch-mask can comprise at least one layer of ECPR etched or plated structures.
  • said etch-mask is removed after the etching step.
  • removing the etch-mask is not required, for instance in order to improve mechanical properties of the multilayer structure.
  • said dielectric layer can be applied with a thickness corresponding to multiple structure layers and patterned in several layers prior to applying at least one structure layer.
  • said dielectric layer can be applied and patterned repeatedly, thereby creating a patterned dielectric layer with a thickness corresponding to multiple structure layers, prior to applying at least one structure layer.
  • the method for uncovering at least some parts of the ECPR etched or plated structures from the dielectric material can include a combination of said planarization methods and said patterning methods.
  • the dielectric materials can be comprised of materials having dielectric constants less than 4.0. Such materials are generally referred to as low-k materials.
  • the low-k materials can comprise carbon-doped dielectrics, such as OSG, FSG, organic polymers, and the like.
  • ultra-low-k dielectric materials can be used with a k-value ranging from less than 2.5.
  • the dielectric material can be comprised of organic compounds, such as polymers, as well as insulating in-organic compounds such as oxides and/or nitrides.
  • Used polymer materials can for instance be: polyimide, siloxane modified polyimide, BCB, SU-8, polytetrafluoroethylene (PTFE), silicones, elastomeric polymers, E-beam resists (such as ZEP (Sumitomo)), photoresists, thinfilm resists, thickfilm resists, polycyclic olefins, polynorborene, polyethene, polycarbonate, PMMA, BARC materials, Lift-Off-Layer (LOL) materials, PDMS, polyurethane, epoxy polymers, fluoro elastomers, acrylate polymers, (natural) rubber, silicones, lacquers, nitrile rubber, EPDM, neoprene, PFTE, parylene, fluoromethylene cyanate ester, inorganic-organic hybrid polymers, (fluorinated and/or hydrogenated) amorphous carbon, by other polymers and/or by combinations thereof.
  • PTFE polyt
  • Used in-organic compounds can for instance be organic doped silicon glass (OSG), fluorine doped silicon glass (FSG), PFTE/silicon compound, tetraethyl orthosilicate (TEOS), SiN, SiO 2 , SiON, SiOC, SiCN:H, SiOCH materials, SiCH materials, silicates, silica based materials, silsesquioxane (SSQ) based material, (nanoporous) methyl-silsesquioxane (MSQ), hydrogen-silsesquioxane (HSQ), TiO 2 , Al 2 O 3 , TiN and/or combinations thereof.
  • OSG organic doped silicon glass
  • FSG fluorine doped silicon glass
  • PFTE/silicon compound tetraethyl orthosilicate
  • SiN SiO 2
  • SiON SiOC
  • SiCN:H SiOCH materials
  • SiCH materials silicates
  • silica based materials silsesquioxane (
  • Said dielectric material can also comprise other available low-k dielectrics listed in the publication: K. Maex, M. R. Baklanov, D. Shamiryan, F. Iacopi, S. H. Brongersma, Z. S. Yanovitskaya, J. Appl. Phys. 93, 8793 (2003).
  • an etch-stop layer is deposited onto the top layer on the substrate prior to applying the dielectric layer.
  • the etch-stop material can be comprised of a material that is much less effected by said dry-etching processes than the dielectric material, and which can be used for selectively etch cavities in the dielectric layer down to the underlying etch-stop layer on top of underlying layer of the substrate or etch down the dielectric layer to slightly below the top of the structure layer.
  • the etch-stop material can be comprised of SiC, SiN, Pt and/or TiW films.
  • a low-k dielectric barrier/etch stop film, such as BLOkTM may be used.
  • Material used for said barrier/capping, adhesion and/or etch-mask layer may also be used for the etch-stop layer.
  • This silicon carbide film is deposited using trimethylsilane ((CH 3 ) 3 SiH) and has a lower dielectric constant (k ⁇ 5) than that of conventional SiC films (k>7) generated by SiH 4 and CH 4 , and that of plasma silicon nitride (k>7).
  • said etch-stop layer can also function as a barrier/capping layer and/or adhesion layer, which adhesion layer also may improve the adhesion between the lower dielectric layer and the upper dielectric layer.
  • a pore sealing operation can be done prior to applying any material layer onto the dielectric.
  • said dielectric material can be a sacrificial polymer material wherein the sacrificial polymer is decomposed into a gaseous phase when for instance treating the material with heat or radiation.
  • said dielectric material can be removed, by decomposing said material and allowing the byproducts to diffuse away, after the multiple structure layers are formed and thereby creating voids or air gaps in the areas that were occupied by the dielectric layer.
  • Said sacrificial polymer used can be a copolymer of butylnorbornene and triethoxysilyl norbornene, such as Unity Sacrificial PolymerTM (Promerus). Further more, by using mechanically stable and insulating barrier/capping and/or etch-mask layers that are not removed from the multiple structure layers, said multiple structure layers are prevented from collapsing.
  • forming multiple layers of conducting and/or dielectric materials includes creating at least one layer with ECPR etching and/or plating and creating at least another layer with known masking and deposition techniques such as lithography followed by electrodeposition, electroless deposition, wet etching, dry etching or other methods for creating a patterned layer of a conducting material.
  • FIGS. 1( a ) to ( h ) illustrate the steps for producing a substrate comprising multiple layers of ECPR etched structures and multiple layers of planarized dielectric material.
  • FIG. 1( a ) illustrates a substrate 2 onto which a seed layer 1 has been applied with the method in said step “(a)”.
  • FIG. 1( b ) illustrates how the master electrode 4 is aligned to and put in contact with the seed layer 1 on the substrate 2 in the presence of an electrolyte 3 with the method in said step “(b)”.
  • FIG. 1( c ) illustrates how ECPR etching proceeds with the method in said step “(c)”.
  • ECPR etched structures 8 which is a replica (negative image) of the insulating pattern layer 5 of the master electrode 4 , are formed in the seed layer on the substrate 2 .
  • the etched material 7 is deposited on the conducting electrode layer 6 in the cavities of the master electrode.
  • the ECPR etching process is stopped when the etching has removed the entire thickness of the seed layer 1 .
  • the etching can in an embodiment be stopped before or prior to etching the entire thickness of the seed layer.
  • FIG. 1( d ) illustrates the substrate with ECPR etched structures 8 after separating the master electrode 4 from the substrate 2 with the method in said step “(d)”. Possible residues or particles or portions of the seed layer have been removed in the etched grooves. Moreover, the material 7 deposited inside the cavities of the master electrode has been removed, such as according to the method in said step “(e)”.
  • FIG. 1( e ) illustrates how a dielectric material 9 has been applied with the method in said step “(f)” and covers the ECPR etched structures 8 .
  • FIG. 1( f ) illustrates how the dielectric material 9 has been planarized with the method in step “(f)”, uncovering the top of the ECPR etched structures 8 .
  • FIG. 1( g ) illustrates how a second seed layer has been applied with the method in said step “(a)”, how ECPR etched structures 8 has been formed by etching grooves in the seed layer with the method in “(b)” to “(e)” and how a second layer of dielectric material 9 has been applied and planarized, with the method in said step “(f)”, uncovering the top of the ECPR etched structures.
  • FIG. 1( h ) illustrates how multiple layers of ECPR etched structures 8 and planarized dielectric material 9 have been formed on the substrate 2 by repeating said steps “(a)” to “(f)”.
  • polishing is used in the planarization steps of FIGS. 1( f ) and 1 ( h ), the polishing is performed on both the hard structural material 8 , such as of metal, as well as on the soft dielectric material 9 .
  • This can result in dishing and erosion as explained above.
  • the dishing and erosion problems are directly related to the amount of structure material that is planarized.
  • FIGS. 2( a ) to 2 ( p ) illustrate the steps for producing a substrate comprising multiple layers of ECPR plated structures and multiple layers of planarized dielectric material.
  • FIG. 2( a ) illustrates a substrate 2 onto which a seed layer 1 has been applied with the method described in said step “(a)”.
  • FIG. 2( b ) illustrates how the master electrode 4 is aligned to and put in contact with the seed layer 1 on the substrate 2 in the presence of an electrolyte 3 with the method in said step “(b)”.
  • FIG. 2( c ) illustrates ECPR plating with the method in said step “(c)”.
  • An anode material 10 which is previously predeposited onto the conducting electrode layer 6 in the cavities formed in the insulating pattern layer 5 of the master electrode 4 , is dissolved and transported in the electrolyte 3 at the same time as ECPR plated structures 11 are formed onto the seed layer 1 on the substrate 2 creating a pattern which is a replica (positive image) of the cavities of the master electrode.
  • FIG. 2( d ) illustrates the substrate 2 with ECPR plated structures 11 after separating the master electrode 4 from the substrate 2 with the method in said step “(d)” and after removing the seed layer in the cavities between the ECPR plated structures with the method described in said step “(e)”. All or substantially all of the anode material, which had been predeposited in the cavities of the master, has been transferred to the substrate forming the ECPR plated structures. Remaining residues of predeposited material in the master can be removed according to the methods described in said step “(e)”.
  • FIG. 2( e ) illustrates an alternative to FIG. 2( d ) showing the substrate with ECPR plated structures 11 after separating the master 4 from the substrate 2 with the method in said step “(d)” and after removing the seed layer in the cavities between the ECPR plated structures with the method described in said step “(e)”. Only a portion of the anode material 10 , which had been predeposited in the cavities of the master, has been transferred to the substrate forming the ECPR plated structures. The remaining predeposited anode material can be used for one or several subsequent ECPR plating steps or it can be removed from the cavities by using the methods described in said step “(e)”. In some embodiments, the remaining anode material does not need to be removed before predepositing new anode material for using in a subsequent ECPR plating step.
  • FIG. 2( f ) illustrates how a dielectric material 9 has been applied with the method in said step “(f)” and covering the ECPR plated structures 11 on a substrate 2 .
  • FIG. 2( g ) illustrates how the dielectric material 9 has been planarized with the method in said step “(f)”, uncovering the top of the ECPR plated structures 11 on the substrate 2 .
  • the polishing will be performed on structures having different hardness, such as the hard structure layer, such as of metal and the soft material layer of dielectric material. This can result in dishing and erosion of the soft material and crack formation on the structure layer.
  • the dishing and erosion problems are directly related to the amount of structure material that is planarized. By carefully controlling the thickness of the structure layer, by using a master electrode with predeposited anode material, dishing, erosion and overall planarity problems can be significantly reduced or even eliminated.
  • FIG. 2( h ) illustrates how a second seed layer 1 has been applied with the method in said step “(a)” and how a second layer of ECPR plated structures 11 is formed by plating a pattern, which is a replica of the cavities of the master electrode, onto the seed layer 1 with the methods in said steps “(b)” to “(e)”.
  • FIG. 2( i ) illustrates how the seed layer in the cavities between the ECPR plated structures is removed with the method described in said step “(e)”.
  • FIG. 2( j ) illustrates how a dielectric material 9 has been applied with the method in said step “(f)” and covering the ECPR plated structures 11 on substrate 2 .
  • FIG. 2( k ) illustrates how the dielectric material 9 has been planarized with the method in said step “(f)”, uncovering the top of the ECPR plated structures 11 on the substrate 2 .
  • FIG. 2( l ) illustrates how a third seed layer 1 has been applied with the method in said step “(a)” and how ECPR plated structures 11 has been formed by plating a pattern, which is a replica of the cavities of the master electrode, onto the seed layer 1 with the methods in said steps “(b)” to “(e)”.
  • FIG. 2( m ) illustrates how a fourth layer of ECPR plated structures 11 is formed onto at least some parts of the previously plated pattern without having removed the previously applied seed layer 1 .
  • the master electrode 4 is aligned to and put in contact with the underlying pattern with the methods in said step “(b)” in a way that the cavities of the insulating layer 5 , which are enclosing the electrolyte 3 , are placed only in the areas which are to be plated upon.
  • the predeposited anode material 10 is dissolved from the conducting electrode layer 6 in the cavities of the master and ECPR plated structures 11 are formed by the method described in said step “(c)”. This step can only be performed if at least some parts of the fourth structure layer are completely inside the structure layer of the previous layer, and results in a saving of method steps.
  • FIG. 2( n ) illustrates a substrate 2 onto which a fourth layer of ECPR plated structures 11 have been deposited directly onto at least some parts of the second ECPR plated pattern without removing the seed layer 1 which had been applied prior to forming the third layer of ECPR plated structures.
  • FIG. 2( o ) illustrates how the seed layer has been removed with the method in said step “(e)” and how a further layer of dielectric material 9 has been applied and covering the ECPR plated structures 11 on substrate 2 .
  • FIG. 2( p ) illustrates how the dielectric material 9 has been planarized using the method in step “(f)” uncovering the top of the ECPR plated structures 11 .
  • the polishing will be performed on two layers having different hardness, such as the hard structure layer of metal and the soft material layer of dielectric material. This can result in dishing and erosion of the soft material and crack formation on the structure layer.
  • the dishing and erosion problems are directly related to the amount of structure material that is planarized.
  • FIGS. 3( a ) to 3 ( k ) illustrate the steps for producing a substrate comprising multiple layers of ECPR etched structures and multiple layers of lithography patterned dielectric material.
  • several procedure steps are saved because the dielectric material is formed with a thickness corresponding to two layers at the same time.
  • two structure layers are formed in a single process, thus saving further time, by applying a seed layer of a thickness corresponding to two layers.
  • FIG. 3( a ) illustrates a substrate 2 on which a seed layer 1 is arranged with the method in said step “(a)”.
  • FIG. 3( b ) illustrates a master electrode 4 that is aligned and put into contact with a seed layer 1 on a substrate 2 using the methods in said step “(b)” and where an electrolyte 3 is enclosed in the cavities of the insulating layer 5 of the master.
  • FIG. 3( c ) illustrates how ECPR etched structures are formed in the seed layer 1 on a substrate 2 by using the methods described in said step “(c)”.
  • the etched material 7 is transferred in the electrolyte 3 and deposited onto the conducting electrode layer 6 in the cavities of the insulating layer 5 in the master electrode 4 .
  • FIG. 3( d ) illustrates a substrate 2 with ECPR etched structures 8 after separating the master 4 from the substrate with the method in said step “(d)” and after removing possible residues or particles of the seed layer 1 in the etched grooves. Also the material deposited inside the cavities of the master electrode has been removed according to the method in said step “(e)”.
  • FIG. 3( e ) illustrates how a dielectric material 9 has been applied to a substrate 2 with the method in step “(f)” and is covering the ECPR etched structures 8 .
  • the material is applied in a thickness corresponding to two layers.
  • a dielectric layer such as spin-coating or spray-coating
  • a planarization material layer can be applied as described in step “(f)”.
  • small valleys may still be formed opposite the cavities in the structure layer 8 below. Such small valleys do not mean any problem in this process.
  • the dielectric material layer is planarized with for example contact planarization.
  • polishing methods can be used, since a single material is affected, namely the material of the dielectric layer.
  • contact planarization and/or polishing methods can be combined with said etch-back methods to achieve desired planarization.
  • FIG. 3( f ) illustrates how the dielectric material 9 is patterned by lithographic methods in said step “(f)”, uncovering the top of at least some parts of the ECPR etched structures 8 previously formed on the substrate 2 .
  • FIG. 3( g ) illustrates a second seed layer 1 that is applied using the methods in said step “(a)” onto the lithography patterned dielectric material 9 which previously is applied to the substrate 2 .
  • the second seed layer is applied with a thickness sufficient for two layers.
  • the cavities of the dielectric material below cause the formation of grooves on top of the applied seed layer corresponding to the pattern, as shown in the figure. Such grooves do not cause any problem for the present process.
  • electroplating methods including the used of additives, such as mentioned above, and/or pulse plating can be used to apply the relatively thick seed layer with a uniform upper surface independent on any recesses in the underlying layer. Using any application method, a uniform upper surface can be achieved independent on any recess in the substrate if the thickness of the seed layer is significantly larger than the depth of the recess.
  • FIG. 3( h ) illustrates how the grooves of the seed layer 1 is removed, if desired, with the planarization methods such as for a dielectric material which is described in said step “(f)”. Since the planarization works on a single material, in this case the hard material of the seed layer, any polishing method can be used. As mentioned above, this planarization can in some cases be left out.
  • FIG. 3( i ) illustrates how the master electrode 4 is aligned and put in contact with the second seed layer 1 using the methods in said step “(b)”. Electrolyte 3 is enclosed in the cavities of insulating pattern layer 5 . The figure also illustrates how structures are formed by ECPR etching according to the method in said step “(c)”, whereby the etched material 7 is being deposited on the conducting electrode layer 6 in the cavities of the master electrode.
  • FIG. 3( j ) illustrates how a second layer of ECPR etched structures 8 is formed after separating of the master electrode from the substrate 2 using the method in said step “(d)” and after removing possible residues of seed layer in the grooves of the ECPR etched structures using the method in said step “(e)”.
  • FIG. 3( k ) illustrates a second dielectric material 9 that is applied with a thickness of two layers and patterned with lithography on the second layer of ECPR etched structures 8 using the methods in said step “(f)”.
  • FIG. 3( l ) illustrates how a third seed layer 1 is applied, with a thickness of two layers, with the method in “(a)”, how ECPR etched structures 8 is formed by repeating the methods in said steps “(b)” to “(e)” and how a dielectric material 9 is applied and further patterned with lithography using the method in said step “(f)”. These processes are repeated until the entire structure is built.
  • FIGS. 4( a ) to 4 ( m ) illustrate the steps for producing a substrate comprising multiple layers of ECPR plated structures and multiple layers of lithography patterned dielectric material.
  • FIG. 4( a ) illustrates a substrate 2 onto which a relatively thin seed layer 1 is applied with the method described in said step “(a)”.
  • FIG. 4( b ) illustrates how the master electrode 4 is aligned and put in contact with the seed layer 1 on the substrate 2 in the presence of an electrolyte 3 , which is enclosed in the cavities of the insulating pattern layer 5 , with the method in said step “(b)”.
  • FIG. 4( c ) illustrates how ECPR plating proceeds with the method in said step “(c)”.
  • An anode material 10 which is previously predeposited onto the conducting electrode layer 6 in the cavities exerted by the insulating pattern 5 of the master electrode 4 , is dissolved and transported in the electrolyte 3 at the same time as ECPR plated structures 11 are formed onto the seed layer 1 on the substrate 2 creating a pattern which is a replica (positive image) of the cavities of the master electrode.
  • FIG. 4( d ) illustrates the substrate 2 with ECPR plated structures 11 after separating the master electrode 4 from the substrate 2 with the method in said step “(d)”.
  • the seed layer in the cavities between the plated structures is removed with the method described in said step “(e)”.
  • All or substantially all of the anode material, which is predeposited in the cavities of the master is transferred to the substrate forming the ECPR plated structures. Remaining residues of predeposited material in the master is removed according to the methods described in said step “(e)”.
  • FIG. 4( e ) illustrates an alternative to FIG. 4( d ) showing the substrate with ECPR plated structures 11 after separating the master electrode 4 from the substrate 2 with the method in said step “(d)” and after removing the seed layer in the cavities between the plated structures with the method described in said step “(e)”.
  • Only a portion of the anode material 10 which is predeposited in the cavities of the master, is transferred to the substrate forming the ECPR plated structures.
  • the remaining predeposited anode material can be used for one or several subsequent ECPR plating steps or can be removed from the cavities by using the methods described in said step “(e)”. In some embodiments, the remaining anode material does not have to be removed before predepositing new anode material for using in a subsequent ECPR plating step.
  • FIG. 4( f ) illustrates how a dielectric material 9 has been applied with the method in said step “(f)” and covering the ECPR plated structures 11 on a substrate 2 and having a height corresponding to two layers.
  • the dielectric material layer can be planarized if required.
  • FIG. 4( g ) illustrates how the dielectric material 9 is patterned by said lithography and/or etching methods in step “(f)”, uncovering the top of at least some parts of the ECPR plated structures 11 previously formed on the substrate 2 .
  • FIG. 4( h ) illustrates a relatively thin seed layer 1 that is applied using the method in said step “(a)” onto the dielectric material 9 .
  • FIG. 4( i ) illustrates a master electrode 4 that is aligned and put in contact with the seed layer 1 using the methods in said step “(b)”.
  • a second layer of ECPR plated structure 11 is formed inside the cavities of the insulating pattern layer 5 as well as in the cavities of patterned dielectric material 9 by dissolving the predeposited anode material 10 which is transported in the electrolyte 3 and deposited on the seed layer.
  • a third layer is formed by deposition.
  • the third layer can include with small recesses opposite the cavities in the second dielectric layer, as shown. Such recesses normally mean no problem in the process.
  • Recesses can also be minimized by the use of pulse-plating, such as pulse-reverse-plating, and/or by including additives in the electrolyte such as mentioned above. If necessary, the recesses can be removed by a planarization operation, which can be a polishing operation since only hard material is encountered, namely the deposited material, such as a metal.
  • FIG. 4( j ) illustrates a third layer of ECPR plated structures 8 being finalized after separation of the master electrode using the method in said step “(d)”.
  • the seed layer is removed in the areas between the ECPR plated structures using the method in said step “(e)”.
  • the second layer of ECPR plated structures fill up the cavities of the lithography patterned dielectric material 9 and connect to the first layer of underlying structures and forms at the same time a third structure layer.
  • FIG. 4( k ) illustrates a second layer of dielectric material 9 that is applied with a thickness of two layers and patterned with lithography and/or etching on a second layer of ECPR etched structures 8 using the methods in said step “(f)”.
  • FIG. 4( l ) illustrates how a fourth and fifth layer of ECPR plated structures 11 are formed by repeating the methods in step “(a)” to “(e)”. At lest some portion of the ECPR plated structures connect to at least some parts of the underlying structures through the cavities of the lithography patterned dielectric material 9 .
  • FIG. 4( m ) illustrates how a further layer of dielectric material 9 with a thickness of two layers is applied and patterned on the third layer of ECPR plated structures 11 using the method in said step “(f)”.
  • the process is repeated until the desired number of layers is built.
  • FIGS. 5( a ) to 5 ( l ) illustrate the steps for producing a substrate comprising multiple layers of ECPR plated structures including barrier/capping layers and multiple layers of lithography patterned dielectric material.
  • ECPR plating can be used for creating metallic interconnects in semiconductor device.
  • a substrate 2 is patterned with a pre-metal dielectric 12 , which is arranged covering possible semiconductors or transistors formed in the substrate. The cavities or the pattern are filled for creating connection plugs 13 of a suitable material, for instance tungsten.
  • a first barrier/capping layer 14 is applied onto the connection plugs 13 and the pre-metal dielectric layer 12 .
  • the barrier/capping layer can be of the same materials and can be applied with the same methods as described for the barrier/capping layers in said step “(f)”.
  • a first layer of dielectric material 9 is applied with methods in said step “(f)”.
  • the dielectric material may comprise a suitable low-k or ultra low-k material, also described in said step “(f)”. The result of performing the mentioned steps is shown in FIG. 5( a ).
  • FIG. 5( b ) illustrates an etch-mask 15 that is applied and patterned on top of the dielectric material 9 .
  • said etch-mask is removed after the etching step.
  • removing the etch-mask is not required, for instance in order to improve mechanical properties of the multilayer structure.
  • FIG. 5( c ) illustrates how the dielectric material 9 and the barrier/capping layer 14 are patterned by the lithography and/or etching methods in said step “(f)” thereby uncovering the top of the connection plugs 13 forming cavities down to the connection plug 13 .
  • FIG. 5( d ) illustrates how a barrier/capping layer 14 and a seed layer 1 is applied onto, and into the cavities of, the patterned dielectric material 9 using the method in said step “(a)”.
  • the barrier/capping layer can also functions as a seed layer, e.g. when using a Ru layer.
  • FIG. 5( e ) illustrates how a master electrode 4 is aligned to the patterned dielectric material 9 and put in contact with the seed layer 1 and enclosing electrolyte 3 in the cavities of the insulating pattern layer 5 using the method in step “(b)”.
  • the predeposited anode material 10 is dissolved at the conducting electrode layer 6 and ECPR plated structures are deposited on the seed layer 1 in the cavities that are filled with electrolyte 3 , as described in the method in said step “(c)”.
  • FIG. 5( f ) illustrates how two layers of ECPR plated structures 11 are formed in one step where the first is filling the cavities of the dielectric material 9 and the second is forming lines on top of some parts of the dielectric material 9 .
  • the via can first be filled by ECPR plating using the methods in said steps “(b)” to “(d)” and then ECPR plated structures 11 are deposited on top on the via layer by repeating the methods in said steps “(b)” to “(d)” and without removing the seed layer in between, possibly by using a second master electrode with a different pattern.
  • FIG. 5( g ) illustrates how the seed layer and the barrier/capping layer selectively are removed in the areas between the ECPR plated structures 11 using the method in said step “(e)”.
  • An anisotropic etching method can be used in order to avoid or reduce the etching of the sidewalls and/or undercutting of the ECPR plated structures 11 .
  • the seed layer and/or the capping layer can be of a material that can be selectively etched in relation to the material of the ECPR plated structures 11 .
  • said seed layer and/or barrier/capping layer can be treated with methods, such as anodization methods mentioned above, converting said materials into insulating materials. In this case, removing said layers may not be required.
  • FIG. 5( h ) illustrates how a barrier/capping coating 16 selectively is applied on the ECPR plated structures.
  • a second layer of dielectric material 9 is applied with a thickness of two layers and patterned with lithography, using the method in said step “(f)”.
  • the deposition of this barrier/capping coating can be done with a method that selectively deposits the material only onto the ECPR plated conductive structures as described in the method in said step “(f)” and does not deposit material on the non-conductive dielectric material 9 .
  • the deposition process can for instance be an electroless deposition process mentioned below and the material can for instance be CoWP, CoWB or CoWBP.
  • the barrier/capping coating is removed, using said etching methods, in the bottom of the cavities of the applied dielectric layer 9 in order to achieve a better contact to a subsequent structure layer.
  • FIG. 5( i ) illustrates how a barrier/capping layer 14 and a seed layer 1 is applied on top of and into the cavities of the patterned dielectric material 9 , using the method in said step “(a)”.
  • FIG. 5( j ) illustrates how the cavities of the dielectric material 9 is filled and how another wire layer of ECPR plated structures 11 is simultaneously formed on top of the dielectric material by repeating the methods in said steps “(b)” to “(d)”.
  • the seed layer and the barrier/capping layer are selectively removed in the areas between the ECPR plated structures 11 using the method in said step “(e)”.
  • a barrier/capping coating 16 is selectively applied onto the ECPR plated structures and a dielectric material is applied and patterned, using the method in said step “(f)”.
  • FIG. 5( k ) illustrates the result after applying a barrier/capping layer 14 and a seed layer 1 using the method in said step “(a)”; forming ECPR plated structures that fill up the cavities of the patterned dielectric material 9 and forming a wire layer of ECPR plated structures 11 on top of the dielectric material by repeating the methods in said steps “(b)” to “(d)”; and removing the barrier/capping layer and seed layer from the areas between the ECPR plated structures using the method in said step “(e)”.
  • FIG. 5( l ) illustrates how another layer of barrier/capping coating 16 is applied onto the ECPR plated structures 11 and how a dielectric material 9 is applied and patterned and/or planarized to uncover the top of the plated structures using the method in said step “(f)”.
  • a passivation layer 17 is applied on top of the ECPR plated structures and dielectric material 9 .
  • the passivation layer can be one or several barrier/capping layers and/or dielectric material layers.
  • FIGS. 6( a ) to 6 ( n ) illustrate the steps for producing a substrate comprising multiple layers of ECPR plated structures including barrier/capping layers and multiple layers of planarized dielectric material.
  • FIG. 6( a ) illustrates a substrate 2 with a patterned pre-metal dielectric layer 12 and connection plugs 13 , onto which a barrier/capping layer 14 and a seed layer 1 has been applied using the method in said step “(a)”.
  • the substrate is similar to the substrate shown in FIG. 5( a ).
  • FIG. 6( b ) illustrates how a master electrode 4 is aligned to the top layer on the substrate and put in contact with the seed layer 1 and enclosing electrolyte 3 in the cavities of the insulating pattern layer 5 using the method in said step “(b)”.
  • the predeposited anode material 10 is dissolved at the conducting electrode layer 6 and ECPR plated structures are deposited on the seed layer 1 in the cavities that are filled with electrolyte 3 , as described in the method in said step “(c)”.
  • FIG. 6( c ) illustrates how ECPR plated structures 11 is formed as a replica (positive image) of the cavities of the master electrode that is separated from the substrate using the method in said step “(d)”.
  • FIG. 6( d ) illustrates how the seed layer 1 and the barrier/capping layer 14 are removed between the ECPR plated structures 11 .
  • An anisotropic etching method can be used in order to avoid or reduce the etching of the sidewalls and/or undercutting of the ECPR plated structures 11 .
  • the seed layer and/or the barrier/capping layer can be of a material that can be selectively etched in respect to the material of the ECPR plated structures 11 .
  • FIG. 6( e ) illustrates how a barrier/capping coating 16 selectively is applied and is covering the ECPR plated structures 11 .
  • the barrier/capping coating 16 can also form an etch-stop coating as described below.
  • FIG. 6( f ) illustrates how a dielectric material 9 is applied and planarized.
  • the planarization is performed by a polishing action until the dielectric layer is slightly above the structure below as shown in FIG. 6( f ).
  • This planarization is performed on a single material, namely the soft material of the dielectric layer.
  • FIG. 6( g ) illustrates a final removal of dielectric material until the top of the structure below is uncovered.
  • the final removal can be performed by etching with a method that removes the material with a uniform rate. If the coating 16 has etch-stop properties, the etching only affects the dielectric material. The material is removed until the structure material 8 below is uncovered. The removal can continue for some time to form a safety margin, for example remove 5 to 10% extra material of the dielectric material, calculated from the start of the etch process. If necessary, the barrier/capping coating 16 can be selectively removed from the top of the exposed structure, especially if the coating 16 is an etch-stop coating.
  • FIG. 6( h ) illustrates how a second layer of ECPR plated structures 11 is formed using the methods in said steps “(b)” to “(d)”; and how the seed layer 1 and the barrier/capping layer 14 is removed between the second ECPR plated structures using the method in said step “(e)”; and how a barrier/capping coating 16 selectively is applied and is covering the ECPR plated structures; and how a second layer of dielectric material 9 is applied and planarized using the method in said step “(f)” uncovering the top of the ECPR plated structures as described above.
  • FIG. 6( i ) illustrates how a barrier/capping layer 14 and a seed layer 1 are applied using the method in said step “(a)”; and how a subsequent layer of ECPR plated structures 11 is formed onto the seed layer using the methods in said steps “(b)” to “(d)”.
  • FIG. 6( j ) illustrates how a subsequent layer of ECPR plated structures is formed, using the methods in said steps “(a)” to “(d)”, directly onto at least some parts of the previous plated structures without removing the previously applied barrier/capping layer 14 and seed layer 1 .
  • the figure illustrates how the master electrode 4 is aligned and put in contact with the previously formed ECPR plated structures using the method in said step “(b)”.
  • the predeposited anode material 10 is dissolved and transported in the electrolyte 3 inside the cavities of the insulating pattern layer 5 and a subsequent layer of ECPR plated structures is formed, onto at least some parts of the previous layer of ECPR plated structures.
  • FIG. 6( k ) illustrates how a subsequent layer of ECPR plated structures 11 is formed, with the method in said steps “(a)” to “(d)”, onto at least some parts of the preceding layer of ECPR plated structures without removing the preceding barrier/capping layer 14 and seed layer 1 .
  • FIG. 6( l ) illustrates how the seed layer 1 and the barrier/capping layer 14 are removed selectively between the ECPR plated structures using the method in said step “(e)”; how a barrier/capping coating selectively is applied to and is covering both the previous and the subsequent layer the ECPR plated structures 11 and how another layer of dielectric material 9 is applied and planarized to uncover the top of the previous layer of ECPR plated structures, using the method in said step “(f)”.
  • FIG. 6( m ) illustrates how a barrier/capping layer 14 and a seed layer 1 is applied using the method in said step “(a)”; a subsequent layer of ECPR plated structures 11 is formed onto the seed layer 1 using the methods in said steps “(b)” to “(d)”; and how the barrier/capping layer 14 and seed layer 1 are removed selectively between the ECPR plated structures using the method in said step “(e)”.
  • FIG. 6( n ) illustrates how a barrier/capping coating 16 selectively is applied to and is covering the ECPR plated structures 11 and how another layer of dielectric material 9 is applied and planarized using the method in said step “(f)”. Finally, a passivation layer 17 is applied to cover the dielectric material and the top of the ECPR plated structures, which are covered with a barrier/capping coating.
  • forming multiple metallic interconnect layers and dielectric layers in a semiconductor device includes creating at least one layer of ECPR plated structures and dielectric material, as illustrated in FIG. 5 and FIG. 6 , using either etching or plating or a combination thereof, and creating at least another layer of conducting structures and dielectric material using known lithographical and plating techniques such as the dual damascene or single damascene process.
  • Some embodiments such as when forming metallic interconnects for integrated circuits (IC), includes fabricating said interconnects by forming multiple ECPR plated structure layers, for instance comprising Cu, and arranging a dielectric material, such as a low-k material, between said structures.
  • a dielectric material such as a low-k material
  • the dielectrics layers are firstly etched and subsequently interconnects are electroplated filling the cavities etched.
  • dielectric materials with lower dielectric constant is required.
  • etching and post-etch-cleaning may result in various problems such as too high line width variations and k-value increase.
  • the method of the present process can eliminate or reduce the number of etching steps of said layers of dielectric material, for instance ultra low-k dielectric layers. Said elimination or reduction of number of etching steps results in less line width variations and less k-value increase which enables the use of ultra low-k materials in an IC device and hence a lower RC-delay as well as less RC-delay variations can be achieved.
  • ECPR plating can be used to fill vias or other grooves in a substrate and/or in a patterned material onto a substrate.
  • FIG. 7( a ) illustrates a via-substrate comprising a substrate 2 , a patterned dielectric material 9 and a seed layer 1 .
  • a master electrode is aligned and put in contact with the seed layer, using the methods in said step “(b)”, in such a way that the walls of the insulating pattern layer 5 which define the cavities of the master electrode 4 are placed outside of the lateral extent of the vias in the dielectric material 9 , the cavities of the master electrode having a larger width than the vias.
  • the predeposited anode material 10 is transferred in the electrolyte 3 by ECPR plating using the method in said step “(c)”.
  • FIG. 7( b ) illustrates how the cavities of the dielectric material 9 are filled with ECPR plated structures 11 .
  • the material deposited on top of the seed layer beside the via can include a groove as shown in FIG. 7( b ).
  • the groove is in some cases of no or less importance.
  • Such chemicals can include additive systems such as described above.
  • the grooves can be reduced by using pulse plating methods such as pulse reverse plating.
  • FIGS. 8( a ) to 8 ( b ) illustrate the steps for filling the vias of a substrate with a patterned dielectric material when aligning the cavities of the master electrode edge to edge with the via-holes, the cavities of the master electrode having the same width as the via-holes.
  • FIG. 8( a ) illustrates how the master electrode is aligned and put in contact with the seed layer, using the methods in said step “(b)”, in such way that the walls of the insulating pattern layer 5 which define the cavities of the master electrode 4 are placed “edge to edge” of the walls of the vias in the dielectric material 9 .
  • the predeposited anode material 10 is transferred in the electrolyte 3 by ECPR plating using the method in said step “(c)”.
  • FIG. 8( b ) illustrates how the cavities of the dielectric material 9 are filled with ECPR plated structures 11 .
  • FIGS. 9( a ) to 9 ( c ) illustrate the steps for filling the vias of a substrate with a patterned dielectric material when aligning the cavities of the master electrode within the lateral extent of the via-holes, the cavities of the master electrode having a smaller width than the via-holes.
  • FIG. 9( a ) illustrates how the master electrode is aligned and put in contact with the seed layer, using the method in said step “(b)”, in such way that the walls of the insulating pattern layer 5 which define the cavities of the master electrode 4 are placed within the lateral extent of the vias in the dielectric material 9 .
  • the predeposited anode material 10 is transferred in the electrolyte 3 by ECPR plating using the method in said step “(c)”, as shown in FIG. 9( a ).
  • FIG. 9( b ) illustrates how the cavities of the dielectric material 9 are filled with ECPR plated structures 11 .
  • FIG. 9( c ) illustrates how the ECPR plated structures 11 are formed above the dielectric material layer as a replica (positive image) of the cavities of insulating pattern layer on the master electrode.
  • FIGS. 10( a ) to 10 ( c ) illustrate the steps for forming a filled through-hole-substrate by filling a via-hole-substrate and planarizing the backside.
  • FIG. 10( a ) illustrates how a master electrode 4 is aligned and put in contact with a seed layer 1 on a substrate 2 patterned with via-hole cavities.
  • the walls of the cavities of the insulating pattern layer 5 can be placed within or outside the lateral extent of, or edge to edge with the walls of the cavities of the substrate.
  • predeposited anode material 10 is dissolved at the conducting electrode layer 6 and ECPR plated structures are formed onto the seed layer 1 in the cavities that comprise the electrolyte 3 .
  • FIG. 10( b ) illustrates how the cavities of the substrate 2 are filled with ECPR plated structures 11 .
  • FIG. 10( c ) illustrates how the seed layer on the front side is removed, the backside of the substrate 2 has been planarized and how the bottom of the ECPR plated structures 11 is uncovered by etching, planarization and/or grinding from the backside.
  • FIGS. 11( a ) to 11 ( c ) illustrate the steps for forming a filled through-hole-substrate by filling a through-hole-substrate with a seed layer on the backside.
  • FIG. 11( a ) illustrates how a master electrode 4 is aligned and put in contact with the front side of a substrate 2 patterned with through-hole cavities and a seed layer 1 on the backside.
  • the walls of the cavities of the insulating pattern layer 5 can be placed within (as illustrated in this figure), or outside the lateral extent of, or edge to edge with the walls of the cavities of the substrate.
  • predeposited anode material 10 is dissolved at the conducting electrode layer 6 and ECPR plated structures are formed onto the seed layer 1 in the cavities that comprise the electrolyte 3 .
  • FIG. 11( b ) illustrates how the cavities of the substrate 2 are filled with ECPR plated structures 11 .
  • FIG. 11( c ) illustrates how the seed layer on the backside is removed and how the bottom of the ECPR plated structures 11 is uncovered.
  • FIGS. 12( a ) to 12 ( b ) illustrate the steps for forming a filled through-hole-substrate by filling a through-hole-substrate onto which a seed layer has been applied.
  • FIG. 12( a ) illustrates how a master electrode 4 has been aligned and put in contact with a seed layer 1 on a substrate 2 patterned with via-through-hole cavities whereby the seed layer 1 extends on the front-side and on the walls of the via-through-holes.
  • the walls of the cavities of the insulating pattern layer 5 can be placed within (as illustrated in this figure), or outside the lateral extent of, or edge to edge with the walls of the cavities of the substrate.
  • FIG. 12( b ) illustrates how the cavities of the substrate 2 are filled with ECPR plated structures 11 and how the seed layer is removed on the front side.
  • FIGS. 13( a ) to 13 ( c ) illustrate the steps for forming a filled through-hole-substrate including filling a via-hole-substrate that is coated with a dielectric material and including patterning the substrate backside.
  • FIG. 13( a ) illustrates how a master electrode 4 has been aligned and put in contact with a seed layer 1 on a substrate 2 patterned with via-hole cavities, which in turn have been patterned by a dielectric material 9 which covers the substrate front-side and the vertical walls of the vias.
  • the walls of the cavities of the insulating pattern layer 5 can be placed within (as illustrated in this figure), or outside the lateral extent of, or edge to edge with the walls of the cavities of the substrate.
  • predeposited anode material 10 is dissolved at the conducting electrode layer 6 and ECPR plated structures are formed onto the seed layer 1 in the cavities that comprise the electrolyte 3 .
  • FIG. 13( b ) illustrates how the cavities of the substrate 2 , which are coated with a patterned dielectric material 9 , are partly filled with ECPR plated structures 11 .
  • FIG. 13( c ) illustrates how the seed layer on the front side is removed and how the backside of the substrate 2 is patterned to uncover the bottom of the ECPR plated structures 11 and the dielectric material 9 .
  • FIGS. 14( a ) to 14 ( c ) illustrate the steps for forming a filled and front side patterned through-hole-substrate.
  • FIG. 14( a ) illustrates how a master electrode 4 is aligned and put in contact with a seed layer 1 on a substrate 2 patterned with via-hole cavities, which in turn have been patterned by a dielectric material 9 .
  • the walls of the cavities of the insulating pattern layer 5 can be placed within or outside (as illustrated in this figure) the lateral extent of, or edge to edge with the walls of the cavities of the substrate. Some parts of the cavities of the insulating pattern layer 5 can be located in areas, separate from the substrate cavities, where ECPR plated structures also are to be formed.
  • predeposited anode material 10 is dissolved at the conducting electrode layer 6 and ECPR plated structures are formed onto the seed layer 1 in the cavities that comprise the electrolyte 3 .
  • FIG. 14( b ) illustrates how the cavities of the substrate 2 , which are coated with a patterned dielectric material 9 , are filled and how ECPR plated structures 11 also are formed on some parts of the seed layer 1 .
  • FIG. 14( c ) illustrates how the seed layer on the front side is removed in the areas between the ECPR plated structures 11 and how the backside of the substrate 2 is patterned to uncover the bottom of the ECPR plated structures.
  • FIGS. 15( a ) to 15 ( c ) illustrate the steps for coating a patterned substrate, which is covered with a seed layer, with ECPR plated structures.
  • FIG. 15( a ) illustrates how a master electrode 4 has been aligned and put in contact with a seed layer 1 on a substrate 2 patterned with structures.
  • the structures exerting the pattern on the substrate can for instance be a conducing pattern 18 , a substrate pattern and/or a dielectric material pattern 9 .
  • the master electrode can be placed in a way that the cavities of the insulating pattern layer 5 enclose at least some parts of the substrate structures. Some parts of the cavities of the insulating pattern layer 5 can be located in areas, separate from the substrate structures, where ECPR plated structures also are to be formed.
  • a voltage is applied, predeposited anode material 10 is dissolved at the conducting electrode layer 6 and ECPR plated structures are formed onto the seed layer 1 in the cavities that comprise the electrolyte 3 .
  • FIG. 15( b ) illustrates how the substrate structures that were enclosed in the cavities of insulating pattern layer of the master electrode are coated with ECPR plated structures 11 . Also, other areas corresponding to the cavities of the insulating pattern layer of the master electrode that do not enclose the substrate structures, are patterned with ECPR plated structures.
  • FIGS. 16( a ) to 16 ( d ) illustrate the steps for creating multiple coating layers on a substrate patterned with conducting material.
  • FIG. 16( a ) illustrates how a master electrode 4 is aligned and put in contact with a seed layer onto which conducting material structures are formed 18 .
  • the master electrode can be placed in a way that the cavities of the insulating pattern layer 5 enclose at least some parts of the conducting material structures 18 .
  • predeposited anode material 10 is dissolved at the conducting electrode layer 6 and ECPR plated structures are formed onto the seed layer and the conducting material structures 18 in the cavities that comprise the electrolyte 3 .
  • FIG. 16( b ) illustrates how the conducting material structures 18 that are enclosed in the cavities of the master electrode are coated with ECPR plated structures 11 .
  • FIG. 16( c ) illustrates how a second coating of ECPR plated structures 11 is applied to the previously coated material 19 covering the conducting material structures 18 .
  • FIG. 16( d ) illustrates how the seed layer selectively is removed in the areas between the coated structures.
  • This method can be repeated one or several times whereby one or several layers of ECPR plated structures 11 can be coated onto the previously coated material 19 on the conducing material 18 structures.
  • the different layers of ECPR plated structures can be of the same or several different materials.
  • the conducting material 18 can be Cu
  • the first coated material 19 can be Ni
  • the second coating of ECPR plated structures 11 can be Au.
  • the conducing material 18 can be Cu
  • the first coated material 19 can be Sn
  • the second coating of ECPR plated structures 11 can be Ag.
  • the ECPR plated structures that coat the substrate pattern comprises a barrier/capping material, adhesion material, etch-mask material and/or etch-stop material.
  • FIGS. 17( a ) to 17 ( h ) are sectional views of different exemplary combinations of designs and materials of a master electrode.
  • FIG. 17( a ) illustrates a sectional view of a master electrode comprising a flexible conducting foil 20 and an insulating pattern layer 5 .
  • FIG. 17( b ) illustrates a sectional view of a master electrode comprising a conducting electrode layer 6 and an insulating pattern layer 5 .
  • FIG. 17( c ) illustrates a sectional view of a master electrode comprising a mechanical support layer 22 , a conducting electrode layer 6 and an insulating pattern layer 5 .
  • FIG. 17( d ) illustrates a sectional view if a master electrode comprising a mechanical support layer 22 , a conducting electrode layer 6 , an insulating pattern layer 5 and a flexible elastomer layer 21 .
  • FIG. 17( e ) illustrates a sectional view of a master electrode comprising a flexible conducting foil 20 , an insulating pattern layer 5 and a flexible elastomer layer 21 .
  • FIG. 17( f ) illustrates a sectional view of a master electrode comprising a conducting electrode layer 6 an insulating pattern layer 5 and a flexible elastomer layer 21 .
  • FIG. 17( g ) illustrates a sectional view of a master electrode comprising a mechanical support layer 22 , a conducting elastomer layer 23 , a conducting electrode layer 6 and an insulating pattern layer 5 .
  • FIG. 17( h ) illustrates a sectional view of a master electrode comprising a mechanical support layer 22 , a conducting electrode layer 6 , an insulating pattern layer 5 and intermediate metal layer 24 and a flexible elastomer layer 21 .
  • the master electrode comprises at least one insulating pattern layer and at least one conducting electrode layer (normally inert in the ECPR process) and possibly a predeposited anode material in the cavities of the master electrode.
  • the insulting pattern of the master layer is a polymer, e.g. a photoresist, an oxide, e.g. SiO 2 , a nitride, e.g. SiN, or combinations thereof.
  • the electrolyte comprises suitable substances for dissolving and depositing the conducting material in which the structures are formed during the ECPR process.
  • the electrolyte comprises an aqueous solution of Cu 2+ , SO 4 2 ⁇ , H + and/or Cl ⁇ and additives such as levelers, accelerators, brighteners, suppressors and wetting agents.
  • additives can be poly-ethylene-glycol (PEG), chloride ions, MPSA, SPS and/or sodium-lauryl-sulfate.
  • FIG. 18 illustrates the schematic eight step process of conventional lithography and electroplating.
  • FIG. 19 illustrates the schematic three step process of producing a plating pattern with the ECPR method.
  • an etching pattern is created with an electrochemical process by using the conducting electrode layer of the master electrode as cathode whereby material is dissolved from the substrate, transferred in the electrolyte and deposited on the cathode thereby creating ECPR etched structures on the substrate corresponding to the pattern of insulating pattern layer on the master electrode. Since the material that is being dissolved from the substrate, which is anode, also is deposited at the conducting electrode layer, which is cathode, the amount of dissolved anode material in the electrolyte remains close to constant during the electrochemical process. If the deposition rate of the dissolved material is zero, the concentration of dissolved anode material ions in the electrolyte increases quickly, this slows down the electrochemical reaction until it eventually stops.
  • a too high ion concentration can also result in precipitation of salts. In this case, only small amounts could be dissolved from the substrate and only thin layers could be patterned. Instead, by making sure that the dissolution reaction has an appropriate deposition reaction, substrates with thicker layers can be etched.
  • the dissolution and deposition reaction in the electrochemical process is determined by the thermodynamic and kinetic reaction at a given applied potential in a specific system of anode, cathode and electrolyte. By choosing the appropriate anode material, cathode material and electrolyte, the desired dissolution and deposition reaction can be achieved since they are thermodynamically and kinetically favorable in the chosen system.
  • anode, cathode and electrolyte system is Ni as anode material, Au as a cathode material and a Watt's bath used as electrolyte.
  • the deposition reaction does not have to be corresponding to the dissolution reaction exactly. As long as the deposition rate of the dissolved material is larger than zero, the buildup of ion concentration of anode material in the electrolyte will be slow which means that it will take longer time before the reaction stops and hence thicker layers on the substrate can be etched. For instance, the deposition rate of the dissolved ions can be 90-100% of the dissolution rate.
  • the ion concentration of dissolved anode will increase slowly, but in some aspects a desired etched thickness can be achieved before the concentration becomes too high.
  • the dissolution rate can be lower than the deposition speed, which eventually leads to depletion of ion concentration in the electrolyte.
  • the dissolution reaction is not too low compared to the deposition reaction (e.g. >90% of the deposition rate)
  • a desired thickness can still be etched from the substrate before depletion of anode material ions in the electrolyte.
  • an inappropriate system is Ag as anode material, Al as cathode material and an alkaline silver cyanide bath as an electrolyte.
  • the deposition rate of silver ions is zero, which will lead to a fast buildup of silver ions in the electrolyte.
  • a plating pattern is created by an electrochemical process by using the conducting electrode layer of the master electrode as anode and having predeposited anode material on the anode inside the cavities defined by the master electrode whereby said anode material is dissolved, transferred in the electrolyte and deposited on the substrate, being cathode, thereby creating ECPR plated structures on the substrate corresponding to the cavities of the insulating pattern layer on the master electrode.
  • Another problem with prior art processes, which do not have predeposited material is that the dissolved material that is undercutting the insulating pattern layer leads to that the anode area increases differently in large contra small cavities in the insulating pattern layer.
  • the area increase due to undercutting is smaller than in small cavities, as illustrated in FIG. 20( a ).
  • Increasing the anode area leads to a higher current density (i.e. plating rate) at the cathode.
  • the structures plated in the small cavities of the insulating pattern layer will be deposited with a higher plating rate than the structures in the large cavities leading to an uneven thickness distribution that depends on the pattern.
  • this problem is solved by having a predeposited material, since no area increase will occur and thereby the current density (plating rate) will be the same in all cavities, non-depending on the size of the patterns.
  • the dissolution of predeposited material prevents the depletion of the concentration of ions in the electrolyte that are deposited on the cathode.
  • a depletion of ions in the electrolyte would gradually slow down the deposition process until it eventually stops and only thin layers of plated structures would be achievable.
  • the ion concentration remains stable and thicker layers of plated structures can be achieved.
  • an appropriate choice of electrochemical system is: having Cu as predeposited material (anode), Cu as seed layer (cathode) and an acidic copper sulfate bath as an electrolyte.
  • the deposition reaction does not have to be corresponding to the dissolution reaction exactly.
  • the dissolution rate of the predeposited material is larger than zero, the depletion of ion concentration in the electrolyte will be slower which means that it will take longer time before the reaction stops and hence thicker layers can be plated.
  • the dissolution rate can be 90-100% of the deposition rate.
  • the ion concentration of material being deposited will decrease slowly, but in some aspects a desired plated thickness can be achieved before the concentration becomes too low.
  • the method may include applying a barrier/capping coating 16 onto the top layer on the substrate 2 prior to applying a dielectric material 9 .
  • This may be done with a mask-less method, as mentioned in said step “(f)”, selectively coating the ECPR plated structures 11 .
  • it can be suitable not to remove the barrier/capping layer 14 after removing the seed layer 1 and prior to applying the barrier/capping coating 16 . In this way, top layer on the substrate 2 , for instance a dielectric material layer, is protected by the barrier/capping layer 14 in the following step of applying the barrier/capping coating 16 .
  • the barrier/capping layer 14 can be of a material onto which no barrier/capping coating 16 is deposited during the mask-less method used for applying the coating onto the ECPR plated structures 11 .
  • the barrier/capping layer 14 between the structures can be removed using said removing methods for the layer described in said step “(e)”.
  • the barrier/capping material may comprise a material that can be etched with a dry-etch method described in said step “(e)”.
  • the barrier/capping coating 16 may comprise a material that is not affected by the removing method used for the barrier/capping layer 14 or at least less affected than the material used for the barrier/capping layer 14 .
  • a conducting or semiconducting layer is used instead of said dielectric layer.
  • a sacrificial layer may be used instead of said dielectric layer, said sacrificial layer being removed after forming said multiple structure layers.
  • the same layer may comprise structural material, sacrificial material and dielectric material.
  • each individual layer can be of any dimension as required by the construction. However, normally, each layer is of a uniform height over the entire surface of the substrate, i.e. the layer has a substantially constant thickness.
US12/085,176 2005-11-18 2006-11-20 Method of Forming a Multilayer Structure Abandoned US20090218233A1 (en)

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US12/085,176 Abandoned US20090218233A1 (en) 2005-11-18 2006-11-20 Method of Forming a Multilayer Structure
US12/412,322 Abandoned US20090183992A1 (en) 2005-11-18 2009-03-26 Method of forming a multilayer structure
US12/412,319 Abandoned US20090205967A1 (en) 2005-11-18 2009-03-26 Method of forming a multilayer structure
US12/470,452 Abandoned US20090229855A1 (en) 2005-11-18 2009-05-21 electrode and method of forming the master electrode
US12/470,448 Abandoned US20090229854A1 (en) 2005-11-18 2009-05-21 Electrode and method of forming the electrode
US12/470,444 Abandoned US20090229857A1 (en) 2005-11-18 2009-05-21 Electrode and method of forming the electrode
US13/429,733 Active US8617362B2 (en) 2005-11-18 2012-03-26 Electrode and method of forming the master electrode
US13/435,771 Abandoned US20120279866A1 (en) 2005-11-18 2012-03-30 Method of forming a multilayer structure
US13/456,142 Abandoned US20120267241A1 (en) 2005-11-18 2012-04-25 Master electrode and method of forming it
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US12/470,452 Abandoned US20090229855A1 (en) 2005-11-18 2009-05-21 electrode and method of forming the master electrode
US12/470,448 Abandoned US20090229854A1 (en) 2005-11-18 2009-05-21 Electrode and method of forming the electrode
US12/470,444 Abandoned US20090229857A1 (en) 2005-11-18 2009-05-21 Electrode and method of forming the electrode
US13/429,733 Active US8617362B2 (en) 2005-11-18 2012-03-26 Electrode and method of forming the master electrode
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