TWI685932B - 用於干擾屏蔽的引線接合線 - Google Patents

用於干擾屏蔽的引線接合線 Download PDF

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TWI685932B
TWI685932B TW105132857A TW105132857A TWI685932B TW I685932 B TWI685932 B TW I685932B TW 105132857 A TW105132857 A TW 105132857A TW 105132857 A TW105132857 A TW 105132857A TW I685932 B TWI685932 B TW I685932B
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substrate
microelectronic device
wire bonding
wire
coupled
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TW105132857A
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TW201714263A (zh
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阿比歐拉 奧佐拉
孫卓文
惠爾 佐尼
阿修克Ｓ 普拉布
威爾瑪 蘇比杜
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美商英帆薩斯公司
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Abstract

大致有關於一具有免於干擾的保護的微電子封裝之設備係被揭示。在本發明之一設備中，一基板係具有一上表面以及一與該上表面相對的下表面，並且具有一接地面。一第一微電子裝置係耦接至該基板的該上表面。引線接合線係耦接至該接地面以用於傳導該干擾至其，並且從該基板的該上表面延伸離開。該些引線接合線的一第一部分係被設置以提供一用於該第一微電子裝置的相關該干擾的屏蔽區域。該些引線接合線的一第二部分並未被設置以提供該屏蔽區域。一第二微電子裝置係耦接至該基板，並且位在該屏蔽區域之外。一導電的表面係在該些引線接合線的該第一部分之上，以用於覆蓋該屏蔽區域。

Description

用於干擾屏蔽的引線接合線
以下的說明係大致有關用於垂直的互連及/或干擾屏蔽的引線接合線。
微電子組件一般包含一或多個IC，例如是一或多個經封裝的晶粒("晶片")或是一或多個晶粒。此種IC中的一或多個可被安裝在一電路平台之上，例如一像是晶圓層級封裝("WLP")的晶圓、印刷板("PB")、一印刷線路板("PWB")、一印刷電路板("PCB")、一印刷線路組件("PWA")、一印刷電路組件("PCA")、一封裝基板、一中介體、或是一晶片載體。此外，一IC可被安裝在另一IC之上。一中介體可以是一被動式IC或是一主動式IC，其中後者係包含一或多個例如是電晶體的主動裝置，而前者並不包含任何主動裝置，但是可包含一或多個例如是電容器、電感器、及/或電阻器的被動裝置。再者，一中介體可被形成像是一PWB，亦即不具有任何的電路元件，例如是不具有任何被動或主動裝置。此外，一中介體可包含至少一穿過基板的貫孔(via)。
一IC例如可包含導電的元件，例如是路徑、線路、軌跡、貫孔、接點、像是接觸墊及焊墊的墊、插塞、節點、或是端子，其可被使用於與一電路平台電互連。這些配置可以使得被用來提供IC的功能的電連 接變得容易。一IC可以藉由接合來耦接至一電路平台，例如是接合此種電路平台的線路或端子至一IC的焊墊或是接腳或柱的露出的末端或類似者；或是一IC可以藉由焊接來耦接至一電路平台。此外，一重分佈層("RDL")可以是一IC的部分，以例如使得一覆晶的配置、晶粒堆疊、或是焊墊的更便利或可接達的位置變得容易。
某些被動或主動微電子裝置可以與電磁干擾("EMI")及/或射頻干擾("RFI")加以屏蔽開。然而，習知的屏蔽可能是製造上複雜的、對於某些行動應用而言是過重的、且/或對於某些低輪廓的應用而言是過大的。再者，某些屏蔽可能並不適合用於大致被稱為三維的("3D")IC或是"3D IC"的一堆疊的晶粒或是堆疊的封裝。
於是，提供一對於習知的干擾屏蔽的改良之干擾屏蔽將會是所期望而且是有用的。
一種設備係大致有關於一具有免於干擾的保護之微電子封裝。在此種設備中，一基板係具有一上表面以及一與該上表面相對的下表面，並且具有一接地面。一第一微電子裝置係耦接至該基板的該上表面。引線接合線係耦接至該接地面以用於傳導該干擾至其，並且從該基板的該上表面延伸離開。該些引線接合線的一第一部分係被設置以提供一用於該第一微電子裝置的相關該干擾的屏蔽區域。該些引線接合線的一第二部分並未被設置以提供該屏蔽區域。一第二微電子裝置係耦接至該基板，並且位在該屏蔽區域之外。一導電的表面係在該些引線接合線的該第一部分之上，以用於覆蓋該屏蔽區域。
一種設備係大致有關於另一具有免於干擾的保護之微電子封裝。在此種設備中，一基板係具有一上表面以及一與該上表面相對的下表面，並且具有一接地面。一微電子裝置係耦接至該基板的該上表面。引線接合線係被接合到該基板的該上表面，並且從該基板的該上表面延伸離開。該些引線接合線的一第一部分係具有一第一高度，並且接近該第一微電子裝置而且在該第一微電子裝置的周圍來加以設置，以用於提供一用於該第一微電子裝置的相關該干擾的屏蔽區域。該些引線接合線的該第一部分係耦接至該接地面以用於傳導該干擾至其。該些引線接合線的一第二部分係具有一小於該第一高度的第二高度，並且接近該第一微電子裝置而且在該第一微電子裝置的周圍來加以設置。該些引線接合線的該第二部分係包含用於電耦接該微電子裝置與該基板的信號線。一導電的表面係在該些引線接合線之上，以用於覆蓋該屏蔽區域。該些引線接合線的該第一部分的上方的末端係機械式地耦接至該導電的表面。
一種設備係大致有關於又一具有免於干擾的保護之微電子封裝。在此種設備中，一基板係具有一上表面以及一與該上表面相對的下表面，並且具有一接地面。一第一微電子裝置係耦接至該基板的該上表面。引線接合線的下方的末端係耦接至該接地面以用於傳導該干擾至其。該些引線接合線的一第一部分係被設置以提供一用於該第一微電子裝置的相關該干擾的屏蔽區域。該些引線接合線的一第二部分並未被設置以提供該屏蔽區域。一第二微電子裝置係耦接至該基板，並且位在該屏蔽區域之外。一導電的表面係使得該些引線接合線的該第一部分耦接至其。該導電的表面係覆蓋該屏蔽區域並且界定該屏蔽區域，其中該些引線接合線的該第一 部分係從該導電的表面延伸離開。
10‧‧‧系統級封裝(SiP)
11‧‧‧主動微電子裝置
12‧‧‧被動微電子裝置
13‧‧‧晶粒
15‧‧‧引線接合
17‧‧‧覆晶的互連(微凸塊互連)
19‧‧‧封裝基板
19L‧‧‧下方的封裝基板
19U‧‧‧上方的封裝基板
20‧‧‧EMI屏蔽
21、22‧‧‧引線接合
23‧‧‧頂端導電板
24‧‧‧底部導電板
100‧‧‧系統級封裝(SiP)
100L‧‧‧下方的SiP
100U‧‧‧上方的SiP
130‧‧‧導電的表面
131‧‧‧引線接合線
131i‧‧‧內部的引線接合線
131L‧‧‧下方的引線接合線
131o‧‧‧外部的引線接合線
131s‧‧‧信號引線接合線
131U‧‧‧上方的引線接合線
132‧‧‧上表面
133‧‧‧屏蔽區域
136‧‧‧BVA配置
137‧‧‧孔洞
140‧‧‧接地面
140L‧‧‧下方的接地面
140U‧‧‧上方的接地面
141‧‧‧球體接合
142‧‧‧貫孔
143‧‧‧介電保護材料
144‧‧‧間隙
145、145U‧‧‧微電子裝置
145L‧‧‧下方的微電子裝置
146‧‧‧上表面
148‧‧‧尖端
149‧‧‧下表面
150‧‧‧導電的覆蓋
153‧‧‧法拉第籠
160‧‧‧接地面
161‧‧‧互連
162‧‧‧貫孔
165‧‧‧微電子裝置
168‧‧‧上表面
169‧‧‧上方的基板
170‧‧‧焊墊
171‧‧‧墊至墊的間距
180‧‧‧互連
190‧‧‧堆疊式封裝的(PoP)裝置
191‧‧‧互連
192L‧‧‧下方的法拉第籠
192U‧‧‧上方的法拉第籠
200‧‧‧垂直整合的微電子封裝
201‧‧‧上表面
202‧‧‧上表面
203‧‧‧側壁
204‧‧‧互連共晶體
231‧‧‧引線接合線
252‧‧‧最下面的表面
261、262、263、264‧‧‧長度
271‧‧‧微電子裝置
274‧‧‧互連共晶體
所附的圖式係展示根據範例的設備或方法的一或多個特點之範例實施例。然而，所附的圖式不應該被視為限制申請專利範圍的範疇，而只是用於解說及理解而已。
圖1A是描繪一不具有電磁干擾("EMI")屏蔽的範例的習知系統級封裝("SiP")的側視方塊圖。
圖1B是描繪另一不具有EMI屏蔽的範例的習知的SiP的側視方塊圖。
圖2是描繪具有一習知的EMI屏蔽的一範例的部分之角落的俯視立體圖。
圖3A及3B是描繪個別的具有EMI屏蔽的範例的SiP的俯視方塊圖。
圖4是描繪一具有EMI屏蔽的範例的SiP的側視橫截面方塊圖。
圖5是描繪一範例的SiP的側視橫截面方塊圖，其係具有一導電的覆蓋並且具有在該導電的覆蓋之下的一EMI屏蔽區域中的信號引線接合線。
圖6是描繪一具有利用一上方的基板的EMI屏蔽的範例的SiP的側視橫截面方塊圖。
圖7是描繪在一法拉第籠(Faraday cage)的一上方的導電的表面的加入之前的一SiP的一範例的部分的俯視方塊圖。
圖8是描繪在一法拉第籠的一上方的導電的表面的加入之前的另一SiP的一範例的部分的俯視方塊圖。
圖9A是描繪一具有EMI屏蔽的堆疊式封裝("PoP")裝置的一範例的部分的側視橫截面方塊圖。
圖9B是描繪另一具有EMI屏蔽的PoP裝置的一範例的部分的側視橫截面方塊圖。
圖10是描繪另一具有EMI屏蔽的SiP的一範例的部分的側視橫截面方塊圖。
圖11A是描繪一不具有引線接合線EMI屏蔽的SiP的一範例的部分的側視橫截面方塊圖。
圖11B是描繪另一不具有引線接合線EMI屏蔽的SiP的一範例的部分的側視橫截面方塊圖。
圖12A至12D是描繪個別的不具有引線接合線EMI屏蔽的SiP的範例的部分之個別的側視橫截面方塊圖。
圖13A至13D是描繪個別的不具有引線接合線EMI屏蔽而具有垂直整合的微電子封裝的SiP的範例的部分之個別的側視橫截面方塊圖。
在以下的說明中，許多特定的細節係被闡述，以提供在此所述的特定例子之更徹底的說明。然而，對於熟習此項技術者應該明顯的是，一或多個其它例子或是這些例子的變化可以在無所有以下給出的特定細節下加以實施。在其它實例中，眾所週知的特點並未詳細地敘述，以防模糊在此的例子的說明。為了便於說明，相同的元件符號係在不同的圖中被使用以參照到相同的項目；然而，在替代的例子中，該些項目可以是不同的。
範例的設備及/或方法係在此加以描述。應瞭解的是，該字詞"範例的"係在此被使用以表示"當作為一個例子、實例、或是例證"。任何在此敘述為"範例"的例子或特點並不一定被解釋為相對其它例子或特點為 較佳或是有利的。
干擾可能是電磁干擾("EMI")及/或射頻干擾("RFI")。干擾屏蔽的以下的說明可被使用於這些類型的干擾的任一種或是兩者。然而，為了舉例且非限制性之清楚的目的起見，大致只有針對EMI的屏蔽係在以下用額外的細節來加以描述。
圖1A是描繪一不具有EMI屏蔽之範例的習知系統級封裝("SiP")10的側視方塊圖。在SiP 10中，可以有耦接至一封裝基板19的一或多個主動微電子裝置11、被動微電子裝置12、及/或IC晶粒13。在此例子中，可以是一被動式或主動式的晶粒的IC晶粒13可能會遭受到EMI。IC晶粒13可以利用引線接合15而被引線接合至封裝基板19，該些引線接合15是用於載有輸入/輸出及其它信號、一電源電壓以及接地參考。
封裝基板19可以是由稱為積層或積層基板的薄層所形成的。積層可以是有機或無機的。用於"剛性"封裝基板的材料例子係包含一例如是FR4或FR5的環氧樹脂基的積層、一例如是雙馬來醯亞胺-三嗪("BT")樹脂基的積層、一陶瓷基板(例如，一低溫共燒陶瓷(LTCC))、一玻璃基板、或是其它形式的剛性封裝基板。再者，一封裝基板19在此可以是一PCB或是其它電路板。為了清楚的目的起見，其它有關習知的SiP 10的已知的細節並未被敘述。
圖1B是描繪另一不具有EMI屏蔽之範例的習知的SiP 10的側視方塊圖。除了例如是微凸塊的覆晶的("FC")互連17被使用，而不是引線接合15之外，圖1B的SiP 10係與圖1A的SiP 10相同的。即使微凸塊互連17係說明性地被描繪，但是其它類型的晶粒表面安裝的互連亦可被使 用。再者，儘管未說明性地描繪在圖1B中，但是微凸塊互連17可以在引線接合15之外另外被使用。
圖2是描繪一習知的EMI屏蔽20的一範例的部分的角落的俯視立體圖。在習知的EMI屏蔽20中，一頂端導電板23可被設置在一底部導電板24之上，其中此種底部導電板24係具有一大於此種頂端導電板23的表面積。
導電板23及24分別可以耦接至一具有引線接合21及22的列之封裝基板19。因此，頂端板23的兩個側邊可以與對應的列的引線接合21來加以引線接合，並且底部板24的兩個側邊同樣地可以與對應的列的引線接合22來加以引線接合。非導電的間隙壁(未顯示)可被用來隔離引線接合21與底部導電板24。一待被EMI屏蔽的微電子裝置(未顯示)可被夾設在頂端及底部導電板23及24之間。此類型的具有引線接合的EMI屏蔽對於許多應用而言可能是過於龐大的。再者，在相關提供側邊EMI屏蔽的引線接合之相對的側邊上可能會有間隙。
干擾屏蔽
圖3A及3B是描繪個別的具有EMI屏蔽之範例的SiP 100的俯視方塊圖。SiP 100的每一個都可包含一封裝基板19，其係具有耦接至其之一上表面132的一或多個主動微電子裝置11、一或多個被動微電子裝置12、以及引線接合線131，其中此種引線接合線131的上方的末端可以耦接至一上表面132。上表面132可以是一導電的表面。引線接合線131可包含等於或小於約0.0508毫米(2密耳)的導線直徑。
引線接合線131的一部分可被設置以界定一屏蔽區域133。 以此種方式，引線接合線131的一BVA配置136的列與行可被用來包圍或者是圍繞一屏蔽區域133。此種引線接合線131的至少一子集合之圍繞一屏蔽區域133的上方的末端可被用來支撐導電的表面130，因而此種導電的表面130可以是在此種屏蔽區域133之上，以用於其之覆蓋。
導電的表面130可以是一導電的剛性或撓性的表面。在一實施方式中，導電的表面130可以是撓性的，例如是在一撓性的片的一表面上之一撓性的導電的塗層。在另一實施方式中，一剛性板可以提供一導電的表面。一剛性板可以是由一種導電材料所做成的。然而，一導電的塗層可被噴塗或是擦塗在一剛性板或是撓性的片上。在圖3B的例子中，如同在以下以額外的細節敘述的，導電的表面130可以具有孔洞137，以用於容許引線接合線131中的界定一屏蔽區域133的至少某些個的上方的部分能夠延伸穿過上表面130。
圖4是描繪一具有EMI屏蔽之範例的SiP 100的側視橫截面方塊圖。SiP 100可包含一封裝基板19，其係具有耦接至其之一上表面132的一或多個主動微電子裝置11、一或多個被動微電子裝置12、以及引線接合線131，其中此種引線接合線131的上方的末端可以耦接至一導電的表面130。即使一SiP 100係被描述，但是其它類型的具有免於EMI的保護的微電子封裝亦可被使用。
封裝基板19係具有一上表面132以及一與該上表面相對的下表面149。封裝基板19可以具有位在表面132及149之間的一接地面140以及互連接至此種接地面以用於導電的貫孔142。
引線接合線131可以利用貫孔142來耦接至接地面140。某 些引線接合線131可以利用用於導電的球體接合141來機械式地耦接至上表面132；然而，在其它實施方式中，其它類型的接合亦可被使用。再者，並非所有的引線接合線131都需要耦接至接地面140。某些引線接合線131可被使用於在SiP 100之內載有供應電壓或信號。某些引線接合線131可被使用於耦接至在SiP 100之內的其它裝置。然而，以下的說明的大部分大致上是有關於和一法拉第籠153相關的引線接合線131。以此種方式，引線接合線131可以耦接至一或多個接地面，以用於傳導干擾至其。
一主動或被動的微電子裝置145可以耦接至封裝基板19的上表面132。微電子裝置145可包含一主動的積體電路晶粒及/或一被動構件。一被動構件可以是一電容器、一電感器、或是一電阻器、或是其之任意組合。
微電子裝置145可以利用如先前所述的球體或凸塊互連及/或引線接合線來耦接至封裝基板19。再者，微電子裝置145可以利用一黏著劑或是一底膠填充層(未顯示)來耦接至上表面132。
微電子裝置145可被設置在例如是利用一密封劑或是一模製材料的一介電保護材料143中，以用於至少覆蓋微電子裝置145的一上表面以及側壁。引線接合線131可被設置在微電子裝置145的側壁的周圍。
導電的表面130可以是位在介電保護材料143的一頂端或上表面146之上、或是耦接至其。然而，在另一實施方式中，如同在以下以額外的細節敘述的，介電保護材料143的一頂表面可以是位在一高於引線接合線131的尖端148的高度處。導電的表面130可被設置在和法拉第籠153相關的引線接合線131之上。此種引線接合線131的上方的末端或尖端 148可以機械式地耦接至導電的表面130。此耦接可以是利用一熱壓接合或是其它形式的機械式耦接。
法拉第籠153可以是接地面140的一部分例如利用貫孔142來互連接至支撐一導電的表面130的引線接合線131的一組合。在另一實施方式中，在導電的表面130與引線接合線131的某些個的尖端148之間可以有一間隙144。以此種方式，導電的表面130的一底部，例如是一導電板的一底部例如可以附接至、或是安置在介電保護材料143的一頂表面之上，因而介電保護材料143的高度可以是大於引線接合線131的高度。
因此，一導電的表面130可被設置在引線接合線131的一部分之上，其中其之上方的末端或尖端148係和導電的表面130間隔開。然而，一種具有一間隙144的配置可能會提供一較不有效的法拉第籠153，因而為了例如且非限制性的清楚的目的起見，應假設是沒有間隙的。
耦接至接地面140而從封裝基板19的上表面132向上突出或延伸離開的引線接合線131可加以排列。以此種方式，即使引線接合線131的一種Bond Via ArrayTM或是BVATM配置136的單一列與行在一實施方式中可以存在，但是一種BVATM配置136的多個列及/或多個行的引線接合線131可以沿著一屏蔽區域133的一或多個側邊而存在。
為了重述要點，引線接合線131中的某些例如是在界定一屏蔽區域133的BVA配置136中的引線接合線131可被設置，以提供此種避免EMI或相關EMI的屏蔽區域133給微電子裝置145。引線接合線131的其它位在屏蔽區域133之外的部分可能並未被使用於EMI屏蔽。再者，一或多個其它主動或被動微電子裝置11及/或12可以耦接至基板19，並且是 位在屏蔽區域133之外，因而不是此種屏蔽區域的部分、或是用於此種屏蔽區域的位置。
圖5是描繪一範例的SiP 100的側視橫截面方塊圖，其係具有一導電的覆蓋150，並且在導電的覆蓋150之下的一EMI屏蔽區域中具有信號引線接合線131s。圖5的SiP 100是與圖4的SiP 100相同的，但是具有以下的差異。
在此例子中，引線接合線131的一部分係具有一高度大於引線接合線131的另一部分的一高度。兩組的引線接合線131都可以接近微電子裝置145而且在微電子裝置145的周圍來加以設置。然而，引線接合線131的較高的部分可以是用於提供一相關EMI的屏蔽區域133給微電子裝置145。然而，引線接合線131的其它較矮的部分("引線接合線131s")可以是耦接微電子裝置145至封裝基板19的導體的信號線。此種較矮的引線接合線131s可以是在一法拉第籠153之內。較高的引線接合線131的高度可被限制為低輪廓的封裝應用。
導電的覆蓋150可以耦接至封裝基板19的上表面132。導電的覆蓋150可以覆蓋SiP 100的耦接至上表面132的構件，其係包含微電子裝置145、微電子裝置11、12以及引線接合線131。並非BVA配置136的部分之引線接合線131可以將導電的覆蓋150以及接地面140互連。此耦接可被使用以降低內部的雜訊。然而，法拉第籠153可以是位在覆蓋150之下，以用於內部的EMI屏蔽。選配的是，導電的表面130可被省略，而有利於利用導電的覆蓋作為法拉第籠153的一上方的導電的表面，而不論在尖端148與導電的覆蓋150的一底面之間具有或是不具有一間隙144。
某些在BVA配置136之內的引線接合線131可以是信號線，亦即引線接合線131s。引線接合線131s可以不耦接至接地面140，而是可以耦接至封裝基板19的線路(未顯示)。引線接合線131s的尖端可以在介電保護材料143的使用之前，先被接合或是焊接至微電子裝置145。在另一實施方式中，相關微電子裝置145的介電保護材料143可被省略。
引線接合線131s可被接合到被動微電子裝置12或是主動微電子裝置11中的一或多個的上表面。這些引線接合線131s可以是用於在SiP 100之內的互連。
圖6是描繪一範例的SiP 100的側視橫截面方塊圖，其係具有利用一上方的基板169的EMI屏蔽。圖6的SiP 100係與圖5的SiP 100相同的，但是並不具有導電的覆蓋150，而且具有以下的差異。
除了貫孔162之外，上方的基板169可包含一接地面160。引線接合線131的尖端或是上方的末端148可以沿著上方的基板169的一底表面，利用互連161(例如是利用微球體或微凸塊)來互連接至貫孔162，例如以用於耦接至接地面160。互連161可被設置在介電保護材料143的一上表面168上。接地面160可以提供法拉第籠153的一上方的導電的表面130。
另一不論是主動或被動的微電子裝置165可以耦接至上方的基板169的一頂表面。微電子裝置165可以利用引線接合線15來耦接至基板169的貫孔或線路。然而，微球體或是微凸塊可以在另一實施方式中被使用。微電子裝置165可以耦接在法拉第籠153之外。
圖7是描繪在一法拉第籠153的一上方的導電的表面130的加入之前的一SiP 100的一範例的部分的俯視方塊圖。焊墊170可以接近微 電子裝置145而且在微電子裝置145的周圍來加以設置，以用於將引線接合線131分別耦接至其，以用於提供法拉第籠153的屏蔽區域133。屏蔽區域133可被界定在一BVA配置136之內。
焊墊170可以在介電保護材料143的側邊周圍和彼此間隔開。在介電保護材料143中的微電子裝置145可以是位在屏蔽區域133的一中央部分中。焊墊170的一墊至墊的間距171可以是等於或小於約250微米。焊墊170的間距171可以針對於和例如是EMI及/或RFI的干擾相關的頻率來加以選擇，以將微電子裝置145與EMI及/或RFI屏蔽開。再者，微電子裝置145可能是一干擾的輻射體，並且因而此種屏蔽可以是用以保護SiP 100的其它構件免於由微電子裝置145所產生的干擾。
即使單一列與行的焊墊170係說明性地被描繪，但是在另一實施方式中可以有超過一或兩個列及/或行。再者，焊墊170的列及/或行可以相關彼此來交錯的，以提供較稠密的屏蔽。引線接合線131可以有效地被用來提供一低通濾波器的法拉第籠，以用於降低相關微電子裝置145的操作的EMI。以此種方式，儘管並非必要的，但焊墊170的設置以及因此的引線接合線131的設置可以是一致的。引線接合線131可以針對於被調適以屏蔽往微電子裝置145、或是來自微電子裝置145的一特定範圍的頻率之密度來加以置放及/或調整。
圖8是描繪在一法拉第籠153的一上方的導電的表面130的加入之前的另一SiP 100的一範例的部分的俯視方塊圖。在此例子中，引線接合線131的一BVA配置136的兩個列以及兩個行係被用來界定一屏蔽區域133。在此例子中，在列與行之間的間隔是交錯的，以提供一較稠密的引 線接合線131的樣式。
在此例子中，BVA配置136的引線接合線131中的某些個係用於載有信號，亦即引線接合線131s。以此種方式，互連180可被形成以用於從微電子裝置145延伸到介電保護材料143之外，以用於與信號引線接合線131s的互連。
圖9A是描繪一具有EMI屏蔽的堆疊式封裝的("PoP")裝置190的一範例的部分的側視橫截面方塊圖。PoP裝置190可包含一上方的SiP 100U，其係堆疊在一下方的SiP 100L的頂端上。PoP裝置190例如可包含一或多個在一屏蔽區域之外的其它微電子裝置以及其它的細節，例如是先前參考圖3A至8所述者。於是，為了清楚且非限制性的目的起見，先前針對於SiP 100所敘述的細節並未在以下加以敘述。
一下方的SiP 100L的一下方的封裝基板19L可包含一下方的接地面140L，其係使得下方的引線接合線131L從下方的封裝基板19L的一上表面向上地延伸。此種下方的引線接合線131L及接地面140L可以例如是利用如先前所述的貫孔及球體接合來互連接至彼此，以用於形成一法拉第籠153的一下方的部分。下方的引線接合線131L的尖端148可以沿著上方的封裝基板19U的一下方側，利用互連191而被接合或耦接至針對其之墊及貫孔。
選配的是，上方的封裝基板19U可包含一上方的接地面140U，以用於形成一法拉第籠153來作為兩個法拉第籠的一堆疊，亦即一上方的法拉第籠192U以及一下方的法拉第籠192L。法拉第籠192U及192L的每一個都可包含分別耦接至封裝基板19U及19L的上表面之個別的封裝 的微電子裝置145U及145L。
上方的基板19U的上方的接地面140U可以是位在一下方的微電子裝置145L之上，因而下方的引線接合線131L的尖端或上方的末端148可以沿著上方的封裝基板19U的一底表面，利用互連191來互連接至墊或接點以用於電耦接至上方的接地面140U。上方的引線接合線131U以及選配的接地面140U可以例如利用如先前所述的貫孔以及球體接合來互連接至彼此，以用於形成一法拉第籠153的一上方部分。上方的引線接合線131U的尖端148可被接合或是耦接至導電的表面130，以用於完成此種上方的法拉第籠192U。
在另一實施方式中，上方的基板封裝19U的貫孔可以在不連接至一上方的接地面140U之下，互連下方的引線接合線131L以及上方的引線接合線131U，以形成一用於兩個微電子裝置145U、145L的"兩個樓層的"或是兩層的法拉第籠153。即使只有兩層係說明性地被描繪，但是超過兩層亦可被使用在其它的實施方式中。
圖9B是描繪另一具有EMI屏蔽的PoP裝置190的一範例的部分的側視橫截面方塊圖。PoP裝置190例如可包含一或多個在一屏蔽區域之外的其它的微電子裝置以及其它細節，例如是先前參考圖3A至9A所述者。於是，為了清楚且非限制性的目的起見，先前針對於SiP 100所敘述的細節並未在以下加以敘述。
除了以下的差異之外，圖9B的PoP裝置190可以是與圖9A的PoP裝置190相同的。圖9B的PoP裝置190可包含信號引線接合線131s。信號引線接合線131s可以是位在法拉第籠153之內，其係包含在法拉第籠 192U之內。
在此配置中的信號引線接合線131s可以從一下方的微電子裝置145L的一上表面向上地延伸。從下方的微電子裝置145L的一上表面延伸之引線接合線131s的尖端或上方的末端148可以例如是利用互連191而互連接至上方的封裝基板19U的一下面側。貫孔及/或線路(未顯示)可以利用信號引線接合線131s來電耦接上方及下方的微電子裝置145。再者，下方的基板封裝19L可包含用於與下方的微電子裝置145互連的貫孔及/或線路(未顯示)。
圖10是描繪另一具有EMI屏蔽的SiP 100的一範例的部分的側視橫截面方塊圖。SiP 100例如可包含一或多個在一屏蔽區域之外的其它的微電子裝置以及其它細節，例如是先前參考圖3A至9B所述者。於是，為了清楚且非限制性的目的起見，先前針對於SiP 100所敘述的細節並未在以下加以敘述。
在此例子中，引線接合線131以及一例如是IC晶粒的微電子裝置145係被一介電保護材料143所保護。微電子裝置145可以在沉積或是注入介電保護材料143之前，利用微凸塊互連17來互連至封裝基板19的一上表面。同樣地，在沉積或是注入介電保護材料143之前，引線接合線131可以被球體接合到封裝基板19的一上表面。
選配的是，信號引線接合線131s可以在沉積或是注入介電保護材料143之前，被球體接合到微電子裝置145的一上表面201。信號引線接合線131s因此可以是在一法拉第籠153的一屏蔽區域133之內。
引線接合線131的尖端或上方的末端148以及選配的信號引 線接合線131s可以延伸在介電保護材料143的一上表面202之上。焊料球體或是其它的互連共晶體204可加以沉積到尖端148之上，以用於例如是在此的別處所描述的後續的互連。
不具有干擾屏蔽的垂直的整合
圖11A是描繪一不具有引線接合線EMI屏蔽的SiP 100的一範例的部分的側視橫截面方塊圖。圖11B是描繪一可包含或者可以不包含EMI屏蔽的SiP 100的一範例的部分的側視橫截面方塊圖。同時參考圖11A及11B，分別說明性地描繪在那些圖中的SiP 100係進一步加以敘述。SiP 100的每一個都可以包含一或多個其它微電子裝置以及其它細節，例如是先前所敘述者。於是，為了清楚且非限制性的目的起見，先前針對於SiP 100所敘述的細節並未在以下加以敘述。
SiP 100的每一個係包含一垂直整合的微電子封裝200。微電子封裝200的每一個係包含一基板19，其係具有一上表面132以及一與該上表面相對的下表面149。封裝基板19可以具有位在表面132及149之間的一接地面140、以及互連接至此種接地面以用於導電的貫孔142，然而此並不是一項要件。
一微電子裝置145可以耦接至基板19的上表面132，其中微電子裝置是一主動或是被動微電子裝置。以此種方式，在一SiP 100中，可以有被動或是主動微電子裝置中的任一種或是兩者的一或多個耦接至上表面132。該些主動或被動裝置可被實施在一半導體晶片上、或是可被實施為離散的構件，例如是獨立的電容器、電阻器、電感器、天線、感測器、等等。若被實施在一種半導體材料中、或是在一種半導體材料上，則該構件 可以用一面向上或是面向下的配置來加以連接，並且亦可以具有一或多個耦接該構件的相對的側邊之穿過半導體的貫孔(TSV)。根據此實施方式，此種主動或是被動微電子裝置的上表面在過去對於垂直的整合而言可能已經變成是未使用的，現在則包含接合被附接至此種微電子裝置的此種上表面的引線接合線，以用於連接至其它的被動或是主動構件。
更具體而言，引線接合線131可以耦接至基板19的上表面132並且從該上表面132延伸離開，並且引線接合線231可以耦接至微電子裝置145的一上表面201並且從該上表面201延伸離開。引線接合線131及231分別可以利用用於導電的球體接合141來機械式地耦接至上表面132及201。然而，在其它實施方式中，其它類型的接合亦可被使用。引線接合線231係在長度上比引線接合線131短的。
參考圖11A，引線接合線131可以具有一整體完成後的長度261，並且引線接合線231可以具有一整體完成後的長度262。然而，引線接合線131及231的完成後的高度可以是大致相同的，以用於使得上方的末端148延伸在模製層143的一上表面202之上。
上方的末端148可以為了大致是共面的而為毗連的。焊料球體或是其它的互連共晶體204可以在上表面202上，而分別加以沉積在上方的末端148之上，以用於與在一主動或被動微電子裝置11或12的一正面的底面上的墊(未顯示)形成互連。
根據一實施方式，微電子裝置145可以耦接至封裝基板19的上表面132。微電子裝置145可包含導電線路，並且可以只包含被動構件。若被實施為一被動構件，則微電子裝置145可以代表一電容器、一電感器、 或是一電阻器、或是其之任意組合。若被實施為一主動構件，則微電子裝置145可以代表例如是一具有電晶體的晶粒，但是額外或替代地可以在該主動構件上、或是在該主動構件中包含其它的主動或被動裝置。
如同先前所述的，微電子裝置145可以利用球體或凸塊互連及/或引線接合線來耦接至封裝基板19。再者，微電子裝置145可以利用一黏著劑或是一底膠填充層(未顯示)來耦接至上表面132。
在所展示的實施方式中，微電子裝置145以及微電子裝置11或12係使得朝向是面向下的，亦即朝向基板19的上表面132之面朝下的朝向。然而，在另一實施方式中，微電子裝置11或12可以額外或是替代地在從基板19的一上表面132面向上的一正面的側面上具有電路。
一微電子裝置11或12可以被耦接在模製層143的最上面的表面202之上。在一實施方式中，一微電子裝置11或12可以利用共晶體204或是其它機械式互連來耦接至引線接合線131及231之上方的末端148。微電子裝置11或12可以是位在微電子裝置145之上，並且可以完全地重疊微電子裝置145、至少部分地重疊此種微電子裝置145、或是可以完全不重疊微電子裝置145。
模製層143可以具有一最上面的表面202以及一與該最上面的表面相對的最下面的表面252。模製層143可被設置以用於圍繞引線接合線131及231兩者的長度261及262的部分。上方的末端148例如可以像是藉由用於一注入模製的一模製輔助膜的使用而不被模製層143所覆蓋。在另一實施方式中，模製層143可以暫時完全覆蓋長度261及262，接著是一回蝕以露出上方的末端148。
在一垂直整合的微電子封裝200的一實施方式中，微電子裝置145可被設置在模製層143中。以此種方式，在一實施方式中，微電子裝置145可以完全位在模製層143的最上面的表面202與最下面的表面252之間。引線接合線131可被設置在微電子裝置145的側壁203的周圍，儘管在此範例實施方式中並非是用於干擾的屏蔽。
引線接合線131可以耦接至接地面140，以用於從封裝基板19的上表面132向上地突出或延伸，並且可加以排列。以此種方式，儘管引線接合線131及/或231的一BVATM配置的單一列與行在一實施方式中可以存在，但是多個列及/或多個行的此種引線接合線亦可以是在一BVATM配置中。
在垂直整合的微電子封裝200的一實施方式中，被實施為一被動微電子裝置的微電子裝置12可被使用。然而，在垂直整合的微電子封裝200的另一實施方式中，微電子裝置11可被實施為一主動微電子裝置。
參考圖11B，內部的引線接合線131i可以具有一整體完成後的長度263，並且引線接合線231可以具有一整體完成後的長度264。如同先前參考圖11A所述的，外部的引線接合線131o可以具有一整體完成後的高度261。引線接合線131i及231在形成之後的完成後的高度可以是大致相同的，以用於使得上方的末端148大致與彼此為高低相同的。
引線接合線131i及231的上方的末端148可以是為了大致是共面的而為毗連的。焊料球體或是其它的互連共晶體274分別可以將一主動或被動微電子裝置271的一下表面耦接至引線接合線131i及231的上方的末端148，以用於與在一主動或被動微電子裝置271的一正面的底面上的 墊(未顯示)形成互連。在微電子裝置271處於適當的地方下，一模製材料可被注入以形成模製材料層143，並且因此微電子裝置271的一下表面可以接觸到模製層143的模製材料。為了模製，一模製輔助膜可被用來容許外部的引線接合線131o的尖端148、以及微電子裝置271的墊或是其它互連(未顯示)，能夠延伸在模製層143的上表面202之上。在另一實施方式中，模製層143可以暫時完全地覆蓋長度261，接著是一回蝕以露出其之上方的末端148。
微電子裝置271可以耦接至微電子裝置145而且位在微電子裝置145之上，並且可以至少部分地重疊微電子裝置145。以此種方式，微電子裝置271可以橫向地延伸在微電子裝置271的一周邊之外，以用於內部的引線接合線131i在基板19的上表面132與微電子裝置271的一面對此種上表面132的下表面之間的互連。引線接合線131i以及引線接合線131o可被設置在微電子裝置145的側壁203的周圍，儘管在此範例實施方式中並非用於干擾的屏蔽。
同樣地，一被動微電子裝置145可以耦接至封裝基板19的上表面132。微電子裝置145可包含導電線路，並且可以只包含被動構件。一被動構件可以是一電容器、一電感器、或是一電阻器、或是其之任意組合。如先前所述，微電子裝置145可以利用球體或是凸塊互連及/或引線接合線來耦接至封裝基板19。再者，微電子裝置145可以利用一黏著劑或是一底膠填充層(未顯示)來耦接至上表面132。若該微電子裝置是一離散的被動構件，則該導線231可被形成在一例如是焊料墊的焊料部分上、或是在一銅、鎳、金、或合金墊上。
模製層143可以具有一最上面的表面202以及一與該最上面的表面相對的最下面的表面252。模製層143可被設置以用於圍繞引線接合線131o的長度261的部分，並且用於圍繞引線接合線131i及231兩者的長度263及264。
在垂直整合的微電子封裝200的一實施方式中，微電子裝置145可被設置在模製層143中，並且完全位在模製層143的最上面的表面202與最下面的表面252之間。微電子裝置271可被設置在模製層143中，並且至少部分地位在模製層143的最上面的表面202與最下面的表面252之間。微電子裝置11或12可以被耦接在模製層143的最上面的表面202之上。
對於一被動微電子裝置271而言，微電子裝置271可包含導電線路，並且可以只包含被動構件。微電子裝置271可包含一RDL。一被動構件可以是一電容器、一電感器、或是一電阻器、或是其之任意組合。在此實施方式中，微電子裝置145及271、以及微電子裝置11或12係具有面向下的朝向，亦即朝向基板19的上表面132之面朝下的朝向。然而，在另一實施方式中，微電子裝置11或12及/或微電子裝置271可以具有從基板19的一上表面132面向上的一正面的側面。
在垂直整合的微電子封裝200的一實施方式中，一被動微電子裝置的微電子裝置12可被使用。然而，在垂直整合的微電子封裝200的另一實施方式中，一主動微電子裝置的微電子裝置11可被使用。一微電子裝置11或12可以耦接在模製層143的最上面的表面202之上，以用於與微電子裝置271的互連。在一實施方式中，一微電子裝置11或12可以利用用於導電的共晶體204或是其它的機械式互連來耦接至微電子裝置271的一上 表面。
微電子裝置11或12可以是位在微電子裝置271之上，並且至少部分地重疊此種微電子裝置271。以此種方式，一微電子裝置11或12可以耦接在模製層143的最上面的表面202之上，以用於與外部的引線接合線131o的上方的末端148的互連、以及與微電子裝置271的一上表面的互連。
引線接合線131i及131o可以耦接至接地面140，以用於從封裝基板19的上表面132向上地突出或延伸，並且可加以排列。以此種方式，即使引線接合線131i、131o及/或231的一BVATM配置的單一列與行在一實施方式中可以存在，但是多個列及/或多個行的此種引線接合線可以是在一BVATM配置中。
圖12A是描繪另一不具有引線接合線EMI屏蔽之SiP 100的一範例的部分的側視橫截面方塊圖。除了以下的細節之外，圖12A的SiP 100可以是與在圖11A中的相同。在一垂直整合的微電子封裝200的此實施方式中，微電子裝置12係懸臂伸出，以用於橫向地延伸超過一引線接合線131並且在其之上。以此種方式，引線接合線131的上方的末端148可以利用共晶體204來互連至一微電子裝置11或12的一下表面。
圖12B是描繪另一不具有引線接合線EMI屏蔽之SiP 100的一範例的部分的側視橫截面方塊圖。除了以下的細節之外，圖12B的SiP 100可以是與在圖11B中的相同。在一垂直整合的微電子封裝200的此實施方式中，微電子裝置12並未懸臂伸出以用於橫向地延伸超過一引線接合線131o並且在其之上。以此種方式，一微電子裝置11或12以及微電子裝置 271對於其分別的下表面以及上表面可以具有大致相等的表面積。
圖12C是描繪另一不具有引線接合線EMI屏蔽之SiP 100的一範例的部分的側視橫截面方塊圖。除了以下的細節之外，圖12C的SiP 100可以是與在圖12A中的相同。在一垂直整合的微電子封裝200的此實施方式中，微電子裝置12係懸臂伸出以用於在微電子裝置145的一右側以及一左側上橫向地延伸超過引線接合線131並且在其之上。以此種方式，引線接合線131的上方的末端148可以利用共晶體204來互連至一微電子裝置11或12的一下表面。於是，應該體認到的是，被設置在一微電子裝置的周圍並且互連接至一微電子裝置11或12的引線接合線131可被使用於扇出。
圖12D是描繪另一不具有引線接合線EMI屏蔽之SiP 100的一範例的部分的側視橫截面方塊圖。除了以下的細節之外，圖12D的SiP 100可以是與在圖12B中的相同。在一垂直整合的微電子封裝200的此實施方式中，微電子裝置12係並未懸臂伸出以用於橫向地延伸超過一引線接合線131o並且在其之上。以此種方式，一微電子裝置11或12以及微電子裝置271對於其分別的下表面以及上表面可以具有大致相等的表面積。以此種方式，引線接合線131i的上方的末端148可以利用共晶體274來互連至一微電子裝置271的一下表面。於是，應該體認到的是，被設置在一微電子裝置145的周圍並且互連接至一微電子裝置271的引線接合線131i可被使用於扇出。
圖13A是描繪一不具有EMI屏蔽而具有一垂直整合的微電子封裝200之範例的SiP 100的側視橫截面方塊圖。在此實施方式中，一垂直整合的微電子封裝200可以是一耦接至基板19的獨立的封裝，即如同在 圖12D中的一SiP 100。由於SiP 100的構件先前已經例如是參考圖4來加以敘述，因而此種說明並未予以重複。
在此實施方式中，共晶體274係被形成在模製層143的一上表面202上。共晶體274係將引線接合線131i及231的上方的末端148互連至微電子裝置271的一下表面，該些引線接合線除了其之下方及上方的末端之外，可被封入在模製層143中。在此例子中，微電子裝置271的一下表面並未接觸模製層143的一上表面202。
再者，在此範例實施方式中，除了此種信號引線接合線131s的下表面之外，信號引線接合線131s可被封入在模製層143的模製材料中。信號引線接合線131s可以是短於內部的引線接合線131i，並且可以是如先前所述的用於與一微電子裝置145的互連。以此種方式，微電子裝置271可以耦接至例如是引線接合線131i之被耦接到上表面132的引線接合線131的一較高的部分的上方的末端148。微電子裝置271可以進一步耦接至引線接合線231的上方的末端148。例如是先前所敘述的，引線接合線131的另一耦接至上表面132的部分(例如是信號引線接合線131s)可以使得其之上方的末端148耦接至微電子裝置145的一上表面。
選配的是，引線接合線331可以耦接至直接被耦接到一基板19的上表面132的主動微電子裝置11及/或被動微電子裝置12的一或多個上表面。
有關圖13A的SiP 100的其它細節先前已經加以敘述，並且因此為了清楚且非限制性的目的起見而未予以重複。
圖13B是描繪一不具有EMI屏蔽而具有一垂直整合的微電 子封裝200之範例的SiP 100的側視橫截面方塊圖。在此實施方式中，如同在圖13A中的一SiP 100，一垂直整合的微電子封裝200可以是一耦接至基板19之獨立的封裝。由於SiP 100的構件先前已經例如參考圖4來加以敘述，因而此種說明並不予以重複。
除了以下的差異之外，圖13B的SiP 100係類似於圖13A的SiP 100。在圖13B的SiP 100中，垂直整合的微電子封裝200係省略微電子裝置271。因此，例如是先前敘述的，一微電子裝置11及/或12可以利用共晶體204來直接耦接至模製層143的一上表面202。
圖13C是描繪一不具有EMI屏蔽而具有一垂直整合的微電子封裝200的範例的SiP 100的側視橫截面方塊圖。在此實施方式中，如同在圖13A中的一SiP 100，一垂直整合的微電子封裝200可以是一耦接至基板19的獨立的封裝。由於SiP 100的構件先前已經例如參考圖4來加以敘述，因而此種說明並不予以重複。
除了以下的差異之外，圖13C的SiP 100係類似於圖13A的SiP 100。在圖13C的SiP 100中，垂直整合的微電子封裝200係具有某些如先前所述的被封入在模製層143的模製材料中的引線接合線131i，並且具有某些並未被封入在模製層143的模製材料中的引線接合線131i。
圖13D是描繪一不具有EMI屏蔽而具有一垂直整合的微電子封裝200之範例的SiP 100的側視橫截面方塊圖。在此實施方式中，如同在圖13B中的一SiP 100，一垂直整合的微電子封裝200可以是一耦接至基板19的獨立的封裝。由於SiP 100的構件先前已經例如參考圖4來加以敘述，因而此種說明並不予以重複。
除了以下的差異之外，圖13D的SiP 100係類似於圖13B的SiP 100。在圖13D的SiP 100中，垂直整合的微電子封裝200並不具有被封入在模製層143的模製材料中的引線接合線131。
這些是用於一SiP 100的一垂直整合的微電子封裝200的各種實施方式中的一些實施方式。然而，這些或其它的實施方式亦可以根據在此的說明來加以提供。
以此種方式，儘管前述內容係描述根據本發明的一或多個特點的範例實施例，但是根據本發明的該一或多個特點的其它及進一步的實施例可以在不脫離本發明的範疇下而被設計出，該範疇係藉由以下的申請專利範圍以及其等同物來加以決定。申請專利範圍所列的步驟並不意指該些步驟的任何順序。商標則是其個別的擁有者之財產權。
11‧‧‧主動微電子裝置
12‧‧‧被動微電子裝置
19‧‧‧封裝基板
100‧‧‧系統級封裝(SiP)
130‧‧‧導電的表面
131‧‧‧引線接合線
132‧‧‧上表面
136‧‧‧BVA配置
140‧‧‧接地面
141‧‧‧球體接合
142‧‧‧貫孔
143‧‧‧介電保護材料
144‧‧‧間隙
145‧‧‧微電子裝置
146‧‧‧上表面
148‧‧‧尖端
149‧‧‧下表面
153‧‧‧法拉第籠

Claims (20)

  1. 一種用於一具有免於干擾的保護的微電子封裝之設備，其係包括：一基板，其係具有一上表面以及一與該上表面相對的下表面，並且具有一接地面；一第一微電子裝置，其係耦接至該基板的該上表面；引線接合線，其係耦接至該接地面以用於傳導該干擾至其，並且從該基板的該上表面延伸離開；該些引線接合線的一第一部分係被設置以提供一用於該第一微電子裝置的相關該干擾的屏蔽區域；該些引線接合線的一第二部分並未被設置以提供該屏蔽區域；一第二微電子裝置，其係耦接至該基板，並且位在該屏蔽區域之外；以及一導電的表面，其係在該些引線接合線的該第一部分之上，以用於覆蓋該屏蔽區域。
  2. 根據申請專利範圍第1項之設備，其中該導電的表面係被設置在該些引線接合線的該第一部分之上，其中其之上方的末端係機械式地耦接至該導電的表面。
  3. 根據申請專利範圍第2項之設備，其中該第一微電子裝置係包含一積體電路晶粒。
  4. 根據申請專利範圍第2項之設備，其中該第一微電子裝置係包含一被動構件。
  5. 根據申請專利範圍第4項之設備，其中該被動構件係從由一電容器、 一電感器、以及一電阻器所構成的一群組被選出。
  6. 根據申請專利範圍第1項之設備，其中該接地面、該導電的表面、以及該些引線接合線的該第一部分的一互連的組合係提供一法拉第籠。
  7. 根據申請專利範圍第1項之設備，其進一步包括一耦接至該基板的該上表面之導電的覆蓋，該導電的覆蓋係覆蓋該第一微電子裝置、該第二微電子裝置、該導電的表面、以及該些引線接合線。
  8. 根據申請專利範圍第1項之設備，其進一步包括：接近該第一微電子裝置而且在該第一微電子裝置的周圍而被設置在該基板的該上表面上的焊墊，以用於將該些引線接合線的該第一部分耦接至其以用於該屏蔽區域；以及該些焊墊係具有一等於或小於約250微米的墊至墊的間距。
  9. 根據申請專利範圍第1項之設備，其中該基板以及該接地面分別是一第一基板以及一第一接地面，該設備進一步包括：一第二基板，其係具有一第二接地面；該些引線接合線的該第一部分的上方的末端係耦接至該第二基板的一底表面，以用於耦接至該第二接地面；以及一第三微電子裝置，其係耦接至該第二基板的一頂表面。
  10. 一種用於一具有免於干擾的保護的微電子封裝之設備，其係包括：一基板，其係具有一上表面以及一與該上表面相對的下表面，並且具有一接地面；一微電子裝置，其係耦接至該基板的該上表面；引線接合線，其係被接合到該基板的該上表面，並且從該基板的該上 表面延伸離開；該些引線接合線的一第一部分係具有一第一高度，並且接近而且在該微電子裝置的周圍而被設置以用於提供一相關該干擾的屏蔽區域給該微電子裝置，該些引線接合線的該第一部分係耦接至該接地面以用於傳導該干擾至其；該些引線接合線的一第二部分係具有一小於該第一高度的第二高度，並且接近而且在該微電子裝置的周圍而被設置，該些引線接合線的該第二部分係包含用於電耦接該微電子裝置與該基板的信號線；一導電的表面，其係在該些引線接合線之上以用於覆蓋該屏蔽區域；以及該些引線接合線的該第一部分的上方的末端係機械式地耦接至該導電的表面。
  11. 根據申請專利範圍第10項之設備，其中該微電子裝置是一第一微電子裝置，該設備進一步包括一第二微電子裝置，其係耦接至該基板並且位在該屏蔽區域之外。
  12. 根據申請專利範圍第10項之設備，其進一步包括：接近而且在該微電子裝置的周圍而被設置在該基板的該上表面上的焊墊，以用於耦接該些引線接合線至其；以及該些焊墊係具有一等於或小於約250微米的墊至墊的間距。
  13. 根據申請專利範圍第10項之設備，其中該基板、該接地面以及該微電子裝置分別是一第一基板、一第一接地面以及一第一微電子裝置，該設備進一步包括： 一第二基板，其係位在該第一微電子裝置之上並且具有一第二接地面以作為該導電的表面，該第二基板是位在該些引線接合線的上方的末端之上；以及一第二微電子裝置，其係耦接至該第二基板的一頂表面。
  14. 根據申請專利範圍第10項之設備，其中該接地面、該導電的表面、以及該些引線接合線的該第一部分的一互連的組合係提供一法拉第籠。
  15. 一種用於一具有免於干擾的保護的微電子封裝之設備，其係包括：一基板，其係具有一上表面以及一與該上表面相對的下表面，並且具有一接地面；一第一微電子裝置，其係耦接至該基板的該上表面；引線接合線的下方的末端，其係耦接至該接地面以用於傳導該干擾至其；該些引線接合線的一第一部分係被設置以提供一用於該第一微電子裝置的相關該干擾的屏蔽區域；該些引線接合線的一第二部分並未被設置以提供該屏蔽區域；一第二微電子裝置，其係耦接至該基板並且位在該屏蔽區域之外；以及一導電的表面，其係使得該些引線接合線的該第一部分耦接至其，該導電的表面係覆蓋該屏蔽區域並且界定該屏蔽區域，其中該些引線接合線的該第一部分係從該導電的表面延伸離開。
  16. 根據申請專利範圍第15項之設備，其進一步包括：接近該第一微電子裝置而且在該第一微電子裝置的周圍而被設置在該 基板的該上表面上的焊墊，以用於耦接該些引線接合線的該些下方的末端至其，以用於提供相關該干擾的該屏蔽區域給該微電子裝置；以及該焊墊係具有一等於或小於約250微米的墊至墊的間距。
  17. 根據申請專利範圍第15項之設備，其中該接地面、該導電的表面、以及該些引線接合線的該第一部分的一互連的組合係提供一法拉第籠。
  18. 根據申請專利範圍第15項之設備，其中該基板以及該接地面分別是一第一基板以及一第一接地面，該設備進一步包括：一第二基板，其係具有一第二接地面；該些引線接合線的該第一部分的球體接合，其係耦接至該第二基板的一底表面，以用於耦接至該第二接地面以作為該導電的表面；以及一第三微電子裝置，其係耦接至該第二基板的一頂表面。
  19. 根據申請專利範圍第15項之設備，其中該第一微電子裝置係包含一積體電路晶粒。
  20. 根據申請專利範圍第15項之設備，其中該第一微電子裝置係包含一被動構件。
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