KR910010508A - 반도체 장치 - Google Patents

반도체 장치 Download PDF

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Publication number
KR910010508A
KR910010508A KR1019890016570A KR890016570A KR910010508A KR 910010508 A KR910010508 A KR 910010508A KR 1019890016570 A KR1019890016570 A KR 1019890016570A KR 890016570 A KR890016570 A KR 890016570A KR 910010508 A KR910010508 A KR 910010508A
Authority
KR
South Korea
Prior art keywords
semiconductor devices
circuit pattern
circuit
circuit blocks
same
Prior art date
Application number
KR1019890016570A
Other languages
English (en)
Other versions
KR0149163B1 (ko
Inventor
슈소 후지이
기요후미 사쿠라이
미츠루 시미즈
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
다케다이 마사다카
도시바 마이크로 일렉트로닉스 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바, 다케다이 마사다카, 도시바 마이크로 일렉트로닉스 가부시키가이샤 filed Critical 아오이 죠이치
Publication of KR910010508A publication Critical patent/KR910010508A/ko
Application granted granted Critical
Publication of KR0149163B1 publication Critical patent/KR0149163B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)

Abstract

내용 없음

Description

반도체 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제5도는 본 발명의 제1실시예에 따른 반도체메모리장치의 평면구조를 나타낸 도면,
제6도는 제5도에 나타낸 메모리어레이 및 그 주변회로를 나타낸 도면,
제7도는 제5도에 나타낸 Ⅰ-Ⅰ선에 따른 단면구조를 나타낸 도면.

Claims (1)

  1. 상호 동일한 구조를 갖고서 규칙적으로 배치된 복수의 회로블럭으로 구성된 회로패턴(10)과, 이 회로패턴(10)에 인접해서 설치된 단부회로블럭의 배치조건을 여타 회로블럭과 실질적으로 동일하게 설정하는 더미회로패턴(DML)을 구비해서 구성된 것을 특징으로 하는 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890016570A 1988-11-15 1989-11-15 반도체장치 KR0149163B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63-288438 1988-11-15
JP63288438A JPH0828467B2 (ja) 1988-11-15 1988-11-15 半導体装置

Publications (2)

Publication Number Publication Date
KR910010508A true KR910010508A (ko) 1991-06-29
KR0149163B1 KR0149163B1 (ko) 1998-10-01

Family

ID=17730213

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890016570A KR0149163B1 (ko) 1988-11-15 1989-11-15 반도체장치

Country Status (5)

Country Link
US (1) US5066997A (ko)
EP (1) EP0369427B1 (ko)
JP (1) JPH0828467B2 (ko)
KR (1) KR0149163B1 (ko)
DE (1) DE68921421T2 (ko)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0461161A (ja) * 1990-06-22 1992-02-27 Mitsubishi Electric Corp 半導体メモリ装置のメモリパターンレイアウト
WO1992002044A1 (en) * 1990-07-18 1992-02-06 Seiko Epson Corporation Semiconductor device
DE69128819T2 (de) * 1990-08-13 1998-05-14 Nec Corp Halbleiterspeicheranordnung
US5441915A (en) * 1992-09-01 1995-08-15 Taiwan Semiconductor Manufacturing Company Ltd. Process of fabrication planarized metallurgy structure for a semiconductor device
KR0121992B1 (ko) * 1993-03-03 1997-11-12 모리시다 요이치 반도체장치 및 그 제조방법
JPH08306773A (ja) * 1995-04-28 1996-11-22 Sharp Corp 半導体装置
US5635421A (en) * 1995-06-15 1997-06-03 Taiwan Semiconductor Manufacturing Company Method of making a precision capacitor array
US5856241A (en) * 1995-07-26 1999-01-05 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
JP3311244B2 (ja) * 1996-07-15 2002-08-05 株式会社東芝 基本セルライブラリ及びその形成方法
US5790417A (en) * 1996-09-25 1998-08-04 Taiwan Semiconductor Manufacturing Company Ltd. Method of automatic dummy layout generation
JPH11111938A (ja) 1997-09-30 1999-04-23 Nec Corp 半導体装置
JP3097627B2 (ja) * 1997-11-05 2000-10-10 日本電気株式会社 半導体記憶装置
US6166415A (en) * 1998-11-02 2000-12-26 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with improved noise resistivity
DE10051719C2 (de) * 2000-10-18 2003-10-02 Infineon Technologies Ag Verfahren zur Herstellung von Schaltkreisstrukturen auf einem Halbleitersubstrat mit Hilfe eines Lithographieprozesses und Anordnung mit funktionalen Schaltkreisstrukturen und Dummy-Schaltkreisstrukturen
JP2002158278A (ja) * 2000-11-20 2002-05-31 Hitachi Ltd 半導体装置およびその製造方法ならびに設計方法
KR100346841B1 (ko) 2000-11-23 2002-08-03 삼성전자 주식회사 저항 소자를 구비하는 반도체 집적 회로 및 그의 제조 방법
JP2002373896A (ja) * 2001-06-15 2002-12-26 Mitsubishi Electric Corp 半導体装置
JP4177568B2 (ja) * 2001-07-10 2008-11-05 株式会社東芝 半導体デバイス
US6750139B2 (en) * 2001-12-12 2004-06-15 Aurora Systems, Inc. Dummy metal pattern method and apparatus
KR20040057789A (ko) * 2002-12-26 2004-07-02 주식회사 하이닉스반도체 반도체장치
JP4599048B2 (ja) * 2003-10-02 2010-12-15 川崎マイクロエレクトロニクス株式会社 半導体集積回路のレイアウト構造、半導体集積回路のレイアウト方法、およびフォトマスク
JP4965445B2 (ja) * 2005-07-27 2012-07-04 スパンション エルエルシー 半導体装置およびその製造方法
JP2007129026A (ja) * 2005-11-02 2007-05-24 Nec Electronics Corp 半導体装置および配線パターン形成方法、マスク配線データ発生方法
JP2010232669A (ja) * 2010-05-25 2010-10-14 Renesas Electronics Corp 半導体装置及び半導体製造方法
US9245603B2 (en) * 2013-10-21 2016-01-26 Macronix International Co., Ltd. Integrated circuit and operating method for the same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5279787A (en) * 1975-12-26 1977-07-05 Toshiba Corp Integrated circuit device
JPS5536977A (en) * 1978-09-07 1980-03-14 Fujitsu Ltd Production of semiconductor device
JPS58111183A (ja) * 1981-12-25 1983-07-02 Hitachi Ltd ダイナミツクｒａｍ集積回路装置
JPH0658947B2 (ja) * 1984-02-24 1994-08-03 株式会社日立製作所 半導体メモリ装置の製法
JPH0666442B2 (ja) * 1985-03-08 1994-08-24 三菱電機株式会社 半導体メモリ装置
US4916514A (en) * 1988-05-31 1990-04-10 Unisys Corporation Integrated circuit employing dummy conductors for planarity
JPH021928A (ja) * 1988-06-10 1990-01-08 Toshiba Corp 半導体集積回路

Also Published As

Publication number Publication date
EP0369427A3 (en) 1992-03-25
DE68921421T2 (de) 1995-08-03
KR0149163B1 (ko) 1998-10-01
EP0369427B1 (en) 1995-03-01
US5066997A (en) 1991-11-19
JPH02133958A (ja) 1990-05-23
EP0369427A2 (en) 1990-05-23
JPH0828467B2 (ja) 1996-03-21
DE68921421D1 (de) 1995-04-06

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