KR910008730A - 반도체 기억장치 - Google Patents
반도체 기억장치 Download PDFInfo
- Publication number
- KR910008730A KR910008730A KR1019900016100A KR900016100A KR910008730A KR 910008730 A KR910008730 A KR 910008730A KR 1019900016100 A KR1019900016100 A KR 1019900016100A KR 900016100 A KR900016100 A KR 900016100A KR 910008730 A KR910008730 A KR 910008730A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor memory
- bits
- terminals
- memory device
- circuit blocks
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/065—Differential amplifiers of latching type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Databases & Information Systems (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 이 발명의 한 실시예에 의한 DRAM의 전체의 구성을 표시하는 블록도.
제2도는 제1도의 DRAM의 주요부를 상세히 표시하는 회로도.
Claims (1)
- 복수 비트로 이루어지는 데이타를 기억하는 반도체 기억장치에 있어서 상기 복수 비트의 데이타를 입력 또는 출력 하기 위한 복수의 단자, 상기 복수의 단자에 대응하여 설치된 복수의 기능회로 블록, 및 상기 복수의 기능회로 블록중 어느 것인가를 고정적으로 비활성 상태에 설정하기 위한 설정 수단을 구비한 반도체 기억장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1264149A JPH0778994B2 (ja) | 1989-10-11 | 1989-10-11 | 半導体記憶装置 |
JP1-264149 | 1989-10-11 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR910008730A true KR910008730A (ko) | 1991-05-31 |
KR970000331B1 KR970000331B1 (ko) | 1997-01-08 |
Family
ID=17399145
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019900016100A KR970000331B1 (ko) | 1989-10-11 | 1990-10-11 | 반도체 기억장치 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5875132A (ko) |
JP (1) | JPH0778994B2 (ko) |
KR (1) | KR970000331B1 (ko) |
DE (1) | DE4020895C2 (ko) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6260103B1 (en) * | 1998-01-05 | 2001-07-10 | Intel Corporation | Read-while-write memory including fewer verify sense amplifiers than read sense amplifiers |
KR100306965B1 (ko) * | 1998-08-07 | 2001-11-30 | 윤종용 | 동기형반도체메모리장치의데이터전송회로 |
US6141286A (en) * | 1998-08-21 | 2000-10-31 | Micron Technology, Inc. | Embedded DRAM architecture with local data drivers and programmable number of data read and data write lines |
US6320811B1 (en) * | 1998-12-10 | 2001-11-20 | Cypress Semiconductor Corp. | Multiport memory scheme |
JP4597470B2 (ja) * | 2002-07-25 | 2010-12-15 | 富士通セミコンダクター株式会社 | 半導体メモリ |
US7280428B2 (en) | 2004-09-30 | 2007-10-09 | Rambus Inc. | Multi-column addressing mode memory system including an integrated circuit memory device |
US8595459B2 (en) * | 2004-11-29 | 2013-11-26 | Rambus Inc. | Micro-threaded memory |
US7660183B2 (en) * | 2005-08-01 | 2010-02-09 | Rambus Inc. | Low power memory device |
US7906982B1 (en) | 2006-02-28 | 2011-03-15 | Cypress Semiconductor Corporation | Interface apparatus and methods of testing integrated circuits using the same |
US20070260841A1 (en) | 2006-05-02 | 2007-11-08 | Hampel Craig E | Memory module with reduced access granularity |
US9268719B2 (en) | 2011-08-05 | 2016-02-23 | Rambus Inc. | Memory signal buffers and modules supporting variable access granularity |
US9759772B2 (en) | 2011-10-28 | 2017-09-12 | Teradyne, Inc. | Programmable test instrument |
US10776233B2 (en) | 2011-10-28 | 2020-09-15 | Teradyne, Inc. | Programmable test instrument |
US10453544B2 (en) | 2014-12-10 | 2019-10-22 | Nxp Usa, Inc. | Memory array with read only cells having multiple states and method of programming thereof |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5427785A (en) * | 1977-08-04 | 1979-03-02 | Nec Corp | Integrated circuit |
JPS56124929A (en) * | 1980-03-06 | 1981-09-30 | Toshiba Corp | Integrated circuit device |
FR2528613B1 (fr) * | 1982-06-09 | 1991-09-20 | Hitachi Ltd | Memoire a semi-conducteurs |
DE3276399D1 (en) * | 1982-09-22 | 1987-06-25 | Itt Ind Gmbh Deutsche | Electrically programmable memory matrix |
JPS62112292A (ja) * | 1985-11-11 | 1987-05-23 | Nec Corp | メモリ回路 |
JPS62120700A (ja) * | 1985-11-20 | 1987-06-01 | Fujitsu Ltd | 半導体記憶装置 |
JPS62188090A (ja) * | 1986-02-13 | 1987-08-17 | Mitsubishi Electric Corp | 電圧検出回路 |
JPS6326892A (ja) * | 1986-07-18 | 1988-02-04 | Nec Corp | メモリ装置 |
JPS6337894A (ja) * | 1986-07-30 | 1988-02-18 | Mitsubishi Electric Corp | ランダムアクセスメモリ |
JPS6349812A (ja) * | 1986-08-19 | 1988-03-02 | Fujitsu Ltd | メモリ制御方式 |
JP2569538B2 (ja) * | 1987-03-17 | 1997-01-08 | ソニー株式会社 | メモリ装置 |
US4891795A (en) * | 1987-05-21 | 1990-01-02 | Texas Instruments Incorporated | Dual-port memory having pipelined serial output |
US4894770A (en) * | 1987-06-01 | 1990-01-16 | Massachusetts Institute Of Technology | Set associative memory |
JPS6451512A (en) * | 1987-08-22 | 1989-02-27 | Fuji Photo Film Co Ltd | Power saving type memory device |
JP2645417B2 (ja) * | 1987-09-19 | 1997-08-25 | 富士通株式会社 | 不揮発性メモリ装置 |
-
1989
- 1989-10-11 JP JP1264149A patent/JPH0778994B2/ja not_active Expired - Fee Related
-
1990
- 1990-06-29 US US07/545,786 patent/US5875132A/en not_active Expired - Fee Related
- 1990-06-29 DE DE4020895A patent/DE4020895C2/de not_active Expired - Fee Related
- 1990-10-11 KR KR1019900016100A patent/KR970000331B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US5875132A (en) | 1999-02-23 |
DE4020895C2 (de) | 1994-01-20 |
DE4020895A1 (de) | 1991-04-25 |
JPH0778994B2 (ja) | 1995-08-23 |
KR970000331B1 (ko) | 1997-01-08 |
JPH03125393A (ja) | 1991-05-28 |
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