JPS5536977A - Production of semiconductor device - Google Patents

Production of semiconductor device

Info

Publication number
JPS5536977A
JPS5536977A JP11016478A JP11016478A JPS5536977A JP S5536977 A JPS5536977 A JP S5536977A JP 11016478 A JP11016478 A JP 11016478A JP 11016478 A JP11016478 A JP 11016478A JP S5536977 A JPS5536977 A JP S5536977A
Authority
JP
Japan
Prior art keywords
electrode
pattern
dummy patterns
etching
fingers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11016478A
Other languages
Japanese (ja)
Inventor
Hidetake Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11016478A priority Critical patent/JPS5536977A/en
Publication of JPS5536977A publication Critical patent/JPS5536977A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)
  • Weting (AREA)

Abstract

PURPOSE:When comb shape fine metal pattern is formed, to get rid of ununiform etching by providing dummy patterns on further outer side of extreme outside electrode and imposing function of becoming thin by over etching to the dummy patterns. CONSTITUTION:An Al thin layer for electrode is deposited and photoresist pattern is provided thereon and etched to form comb shape electrode. Namely, resist pattern consisting of group of fingers 21-2n and group of fingers 31-3n and root connecting these groups is formed. At this time, dummy patterns 41, 43 are disposed on further outer side of both sides and also a dummy pattern 42 is disposed between the two groups. By etching in such manner, becoming thin of the finger by overetching is taken by dummy patterns and the size of electrode pattern is kept as designed.
JP11016478A 1978-09-07 1978-09-07 Production of semiconductor device Pending JPS5536977A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11016478A JPS5536977A (en) 1978-09-07 1978-09-07 Production of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11016478A JPS5536977A (en) 1978-09-07 1978-09-07 Production of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5536977A true JPS5536977A (en) 1980-03-14

Family

ID=14528662

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11016478A Pending JPS5536977A (en) 1978-09-07 1978-09-07 Production of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5536977A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5935473A (en) * 1982-08-23 1984-02-27 Nec Corp Semiconductor device
EP0219100A2 (en) * 1985-10-16 1987-04-22 Kabushiki Kaisha Toshiba Method of forming a fine pattern
JPH02133958A (en) * 1988-11-15 1990-05-23 Toshiba Corp Semiconductor device
JPH02177558A (en) * 1988-12-28 1990-07-10 Nec Corp Semiconductor integrated circuit device
FR2681958A1 (en) * 1991-10-01 1993-04-02 France Telecom Device which includes a pattern configured by photogravure, especially an electrical circuit
JPH0669214A (en) * 1991-03-01 1994-03-11 Nec Corp Semiconductor device
JP2014008608A (en) * 2012-06-27 2014-01-20 Canon Inc Method of processing silicon wafer
JP2014067773A (en) * 2012-09-25 2014-04-17 Canon Inc Silicon substrate etching method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5330311A (en) * 1976-09-01 1978-03-22 Fujitsu Ltd Production of magnetic head of floating type

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5330311A (en) * 1976-09-01 1978-03-22 Fujitsu Ltd Production of magnetic head of floating type

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5935473A (en) * 1982-08-23 1984-02-27 Nec Corp Semiconductor device
EP0219100A2 (en) * 1985-10-16 1987-04-22 Kabushiki Kaisha Toshiba Method of forming a fine pattern
JPH02133958A (en) * 1988-11-15 1990-05-23 Toshiba Corp Semiconductor device
JPH02177558A (en) * 1988-12-28 1990-07-10 Nec Corp Semiconductor integrated circuit device
JPH0669214A (en) * 1991-03-01 1994-03-11 Nec Corp Semiconductor device
FR2681958A1 (en) * 1991-10-01 1993-04-02 France Telecom Device which includes a pattern configured by photogravure, especially an electrical circuit
JP2014008608A (en) * 2012-06-27 2014-01-20 Canon Inc Method of processing silicon wafer
JP2014067773A (en) * 2012-09-25 2014-04-17 Canon Inc Silicon substrate etching method

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