KR860007735A - 반도체장치 및 그 제조방법과 그 제조방법에 사용하는 리이드 프레임 - Google Patents

반도체장치 및 그 제조방법과 그 제조방법에 사용하는 리이드 프레임 Download PDF

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Publication number
KR860007735A
KR860007735A KR1019860001007A KR860001007A KR860007735A KR 860007735 A KR860007735 A KR 860007735A KR 1019860001007 A KR1019860001007 A KR 1019860001007A KR 860001007 A KR860001007 A KR 860001007A KR 860007735 A KR860007735 A KR 860007735A
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South Korea
Prior art keywords
ferret
semiconductor device
lead
tab
insulating sheet
Prior art date
Application number
KR1019860001007A
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English (en)
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KR940010546B1 (ko
Inventor
다기유기 오기다가
다가유기 오기다가
히로시 다지
히로시 오자기
간지 오오즈가
미지아기 후루기와
야스유기 야마자기
Original Assignee
가부시기가이샤 히다찌세이사꾸쇼
미쓰다 가쓰시게
히다찌초 Lsi 엔지니어링 가부시기가이샤
가부시기 가이샤 히다찌 세이사꾸쇼
오오노 미노루
히다찌초 Lsi 엔지니어링 가부시기 가이샤
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Application filed by 가부시기가이샤 히다찌세이사꾸쇼, 미쓰다 가쓰시게, 히다찌초 Lsi 엔지니어링 가부시기가이샤, 가부시기 가이샤 히다찌 세이사꾸쇼, 오오노 미노루, 히다찌초 Lsi 엔지니어링 가부시기 가이샤 filed Critical 가부시기가이샤 히다찌세이사꾸쇼
Publication of KR860007735A publication Critical patent/KR860007735A/ko
Priority to KR1019940021371A priority Critical patent/KR940011379B1/ko
Application granted granted Critical
Publication of KR940010546B1 publication Critical patent/KR940010546B1/ko

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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/906—Dram with capacitor electrodes used for accessing, e.g. bit line is capacitor plate

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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Abstract

내용 없음

Description

반도체장치 및 그 제조방법과 그 제조방법에 사용하는 리이드 프레임
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 의한 실시예 1인 반도체 장치를 도시한 제2도에 있어서의 Ⅰ-Ⅰ선 단면도.
제2도는 본 실시예 1의 반도체장치의 페렛과 리이드와의 관계를 도시한 평면도.
제3도는 본 실시예 1의 반도체 장치에 적용되는 리이드 프레임을 도금 공정에 있어서의 상태로 도시한 부분 평면도.

Claims (24)

  1. 수지봉지형 반도체 장치로서 페렛의 뒷면, 즉, 비회로 형성주면 혹은, 그 근방에 리이드가 뻗어서 된 반도체 장치.
  2. 탭이 페렛보다 작게 형성되어 있는 것을 특징으로 하는 특허청구의 범위 제1항 기재의 반도체 장치.
  3. 탭이 생략되어 있는 것을 특징으로 하는 특허청구의 범위 제1항 기재의 반도체 장치.
  4. 페렛이 적어도 1줄이상의 리이드와 탭에 접촉재료로 된 접착제로서 취부되어 있는 것을 특징으로 하는 특허청구의 범위 제1항 기재의 반도체 장치.
  5. 페렛이 절연사이트에 접착되고, 그 절연시이트가 리이드와 탭에 접착되어 있는 것을 특징으로 하는 특허청구의 범위 제1항 기재의 반도체 장치.
  6. 페렛이 리이드에 절연재료로된 접착제로 취부되어 있는 것을 특징으로 하는 특허청구의 범위 제1항 기재의 반도체 장치.
  7. 페렛이 절연시이트에 취부되어 있고, 그 절연시이트에 리이드의 적어도 1줄 이상이 접착되어 있는 것을 특징으로 하는 특허청구의 범위 제1항 기재의 반도체 장치.
  8. 리이드에 있어서의 본딩 와이어 접촉 영역 근방의 리이드 영역에 오목부 또는 볼록부가 형성되어 있는 것을 특징으로 하는 특허청구의 범위 제1항 기재의 반도체 장치.
  9. 수지봉지형 반도체 장치로서 페렛의 표면 즉, 회로형성면 혹은 그 근방에 리이드가 뻗어서 된 반도체 장치.
  10. 탭이 페렛보다 작게 형성되어 있는 것을 특징으로 하는 특허청구의 범위 제9항 기재의 반도체 장치.
  11. 탭이 생략되어 있는 것을 특징으로 하는 특허청구의 범위 제9항 기재의 반도체 장치.
  12. 페렛이 리이드와 탭에 접착제로 취부되어 있는 것을 특징으로 하는 특허청구의 범위 제9항 기재의 반도체 장치.
  13. 페렛이 절연시이트에 접속되고 그 절연시이트가 적어도 1줄 이상의 리이드와 탭에 접착되어 있는 것을 특징으로 하는 특허청구의 범위 제9항 기재의 반도체 장치.
  14. 페렛이리이드에 접착제로서 취부되어 있는 것을 특징으로 하는 특허청구의 범위 제9항 기재의 반도체 장치.
  15. 페렛이 절연시이트에 취부되어 있고, 그 절연시이트에 리이드의 적어도 1줄 이상이 접착되어 있는 것을 특징으로 하는 특허청구의 범위 제9항 기재의 반도체 장치.
  16. 리이드에 있어서의 본딩 와이어 접속영역 근방의 리이드 영역에 오목부 또는 볼록부가 형성되어 있는 것을 특징으로 하는 특허청구의 범위 제9항 기재의 반도체 장치.
  17. 리이드 프레임을 준비하고 리이드 프레임의 적어도 1줄 이상의 리이드에 절연 시이트를 접착제를 사용하여 고정한 후, 상기 절연 시이트에 페렛을 접착제를 사용해서 고정하는 공정과, 페렛에 있어서의 본딩 페드와 리이드를 와이어에 의해서 전기적으로 접속을 행하는 와이어 본딩 공정과, 페레 및 와이어 지에 의해 봉지하는 공정을 가진 반도체 장치의 제조 방법.
  18. 특허청구의 범위 제17항에 있어서, 페렛의 뒷면 즉, 비회로 형성 주면에 절연시이트가 접착제를 사용하여 고정하는 것을 특징으로 하는 반도체 장치의 제조 방법.
  19. 리이드 프레임을 준비하고, 리이드 프레임의 적어도 1줄 이상의 리이드에 페렛을 절연재료으로 된 접착제를 사용하여 고정하는 공정과, 페렛에 있어서의 본딩 페드와 리이드를 와이어에 의해서 전기적으로 접속을 행하는 와이어 본딩 공정과, 페렛 및 와이어를 수지에 의해 봉지하는 공정을 가진 반도체 장치의 제조 방법.
  20. 특허청구의 범위 제19항에 있어서, 페렛의 뒷면 즉, 비회로 형성 주면에 절연재료으로 된 접착제를 사용하여 고정하는 것을 특징으로 하는 반도체 장치의 제조방법.
  21. 수지 봉지형 반도체 장치의 제조에 사용되는 리이드 프레임으로서, 여러줄의 리이드 중 적어도 1줄이상의 리이드가 페렛이 배치되는 영역의 아래 또는 위로 뻗어 있는 것을 특징으로 하는 리이드 프레임.
  22. 특허청구의 범위 제21항에 있어서, 페렛이 취부하기 위한 탭이 마련되어 있는 것을 특징으로 하는 리이드 프레임.
  23. 특허청구의 범위 제21항에 있어서, 페렛이 취부하기 위한 탭이 마련되어 있지 않는 것을 특징으로 하는 리이드 프레임.
  24. 특허청구의 범위 제21항에 있어서, 페렛이 배치되는 영역의 아래 또는 위로 뻗어 있는 리이드에 있어서의 와이어 본딩 영역과 페렛배치 영역과의 사이의 리이드 부분에 오목부 또는 볼록부가 형성되어 있는 것을 특징으로 하는 리이드 프레임.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019860001007A 1985-03-25 1986-02-13 반도체장치 KR940010546B1 (ko)

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KR940010546B1 (ko) 1994-10-24
CN1043828A (zh) 1990-07-11
CN86101795A (zh) 1986-09-24
JPS61218139A (ja) 1986-09-27
JPH06105721B2 (ja) 1994-12-21
US5126821A (en) 1992-06-30
US4943843A (en) 1990-07-24
CN1147151A (zh) 1997-04-09

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