JP5102268B2 - 半導体メモリ素子のパワーアップ回路 - Google Patents
半導体メモリ素子のパワーアップ回路 Download PDFInfo
- Publication number
- JP5102268B2 JP5102268B2 JP2009239836A JP2009239836A JP5102268B2 JP 5102268 B2 JP5102268 B2 JP 5102268B2 JP 2009239836 A JP2009239836 A JP 2009239836A JP 2009239836 A JP2009239836 A JP 2009239836A JP 5102268 B2 JP5102268 B2 JP 5102268B2
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- JP
- Japan
- Prior art keywords
- power supply
- supply voltage
- level
- power
- sensing unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electronic Switches (AREA)
- Dram (AREA)
- Logic Circuits (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
210A、310A … 第1電源電圧感知部
210B、310B … 第2電源電圧感知部
220、320 … トリガ部
230、330 … バッファ部
Claims (3)
- 電源電圧のレベル変化に応じて線形的に変化する第1及び第2バイアス電圧を提供するための電源電圧レベルフォロワ部と、
前記第1バイアス電圧に応答して、前記電源電圧の下降時のパワーアップ信号の遷移レベルに対応する第1臨界レベルへの変化を感知するための第1電源電圧感知部と、
前記第2バイアス電圧に応答して、前記電源電圧の上昇時のパワーアップ信号の遷移レベルに対応し、前記第1臨界レベルより相対的に高い電圧レベルを有する第2臨界レベルへの変化を感知するための第2電源電圧感知部と、
前記電源電圧の下降時に前記第1電源電圧感知部から出力された第1感知信号に応答して、その出力信号を遷移させ、前記電源電圧の上昇時に前記第2電源電圧感知部から出力された第2感知信号に応答して、その出力信号を遷移させるためのトリガ部とを備えてなり、
前記電源電圧レベルフォロワ部は、電源電圧端と接地電圧端との間に設けられ電圧ディバイダを構成する3つ以上の負荷素子を備え、前記負荷素子間の第1ノードから第1バイアス電圧を出力するとともに、前記第1ノードとは異なる前記負荷素子間の第2ノードから前記第1バイアス電圧よりも低い第2バイアス電圧を出力し、
前記第1電源電圧感知部は、前記第1バイアス電圧をゲート入力とする第1トランジスタを備え、
前記第2電源電圧感知部は、前記第2バイアス電圧をゲート入力とする第2トランジスタを備える半導体メモリ素子のパワーアップ回路。 - 請求項1に記載の半導体メモリ素子のパワーアップ回路において、
前記第1電源電圧感知部は、
前記電源電圧端と第3ノードとの間に接続された負荷素子と、
前記第3ノードに接続されたインバータとを備え、
前記第1トランジスタは、前記接地電圧端と前記第3ノードとの間に接続されたNMOSトランジスタで具現され、
前記第2電源電圧感知部は、
前記電源電圧端と第4ノードとの間に接続された負荷素子と、
前記第4ノードに接続されたインバータとを備え、
前記第2トランジスタは、前記接地電圧端と前記第4ノードとの間に接続されたNMOSトランジスタで具現されることを特徴とする回路。 - 請求項2に記載の半導体メモリ素子のパワーアップ回路において、
前記負荷素子は、接地電圧をゲート入力とするPMOSトランジスタで具現することを特徴とする回路。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2003-099598 | 2003-12-30 | ||
KR1020030099598A KR100605574B1 (ko) | 2003-12-30 | 2003-12-30 | 반도체 메모리 소자의 파워업 회로 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004096633A Division JP2005196929A (ja) | 2003-12-30 | 2004-03-29 | 半導体メモリ素子のパワーアップ回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010080047A JP2010080047A (ja) | 2010-04-08 |
JP5102268B2 true JP5102268B2 (ja) | 2012-12-19 |
Family
ID=34698708
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004096633A Pending JP2005196929A (ja) | 2003-12-30 | 2004-03-29 | 半導体メモリ素子のパワーアップ回路 |
JP2009239836A Expired - Fee Related JP5102268B2 (ja) | 2003-12-30 | 2009-10-16 | 半導体メモリ素子のパワーアップ回路 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004096633A Pending JP2005196929A (ja) | 2003-12-30 | 2004-03-29 | 半導体メモリ素子のパワーアップ回路 |
Country Status (6)
Country | Link |
---|---|
US (1) | US6961270B2 (ja) |
JP (2) | JP2005196929A (ja) |
KR (1) | KR100605574B1 (ja) |
CN (1) | CN100419911C (ja) |
DE (1) | DE102004010353A1 (ja) |
TW (1) | TWI261265B (ja) |
Families Citing this family (14)
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KR100648857B1 (ko) * | 2005-03-31 | 2006-11-24 | 주식회사 하이닉스반도체 | 파워업 신호 발생 장치 및 그 생성 방법 |
KR100656463B1 (ko) | 2005-12-28 | 2006-12-11 | 주식회사 하이닉스반도체 | 파워-업 회로 및 이를 포함하는 반도체 메모리 장치 |
KR100746610B1 (ko) * | 2005-12-29 | 2007-08-08 | 주식회사 하이닉스반도체 | 파워-업 신호 발생 장치 |
KR100735678B1 (ko) | 2006-01-05 | 2007-07-04 | 삼성전자주식회사 | 초기화 신호 생성 회로 |
KR100806120B1 (ko) * | 2006-08-22 | 2008-02-22 | 삼성전자주식회사 | 내부 전원전압 발생회로 및 내부 전원전압 발생방법 |
KR100806127B1 (ko) | 2006-09-06 | 2008-02-22 | 삼성전자주식회사 | 피크 커런트를 감소시키는 파워 게이팅 회로 및 파워게이팅 방법 |
KR101418122B1 (ko) * | 2007-12-29 | 2014-07-11 | 엘지디스플레이 주식회사 | 인버터 |
KR100909636B1 (ko) * | 2008-03-18 | 2009-07-27 | 주식회사 하이닉스반도체 | 듀얼 파워 업 신호 발생 회로 |
JP5547451B2 (ja) * | 2009-10-13 | 2014-07-16 | ラピスセミコンダクタ株式会社 | パワーオンリセット回路 |
KR101145315B1 (ko) * | 2009-12-29 | 2012-05-16 | 에스케이하이닉스 주식회사 | 내부전압발생회로 |
KR101178560B1 (ko) | 2010-07-06 | 2012-09-03 | 에스케이하이닉스 주식회사 | 파워업 신호 생성회로 및 생성 방법 |
CN103871458B (zh) * | 2012-12-07 | 2018-05-01 | 三星电子株式会社 | 集成电路及其数据处理方法、解码器、存储器 |
KR102211056B1 (ko) | 2013-12-30 | 2021-02-02 | 에스케이하이닉스 주식회사 | 반도체 장치 |
US10224922B1 (en) * | 2018-04-04 | 2019-03-05 | Stmicroelectronics International N.V. | Biasing cascode transistor of an output buffer circuit for operation over a wide range of supply voltages |
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-
2003
- 2003-12-30 KR KR1020030099598A patent/KR100605574B1/ko active IP Right Grant
-
2004
- 2004-03-02 US US10/792,064 patent/US6961270B2/en not_active Expired - Lifetime
- 2004-03-03 DE DE102004010353A patent/DE102004010353A1/de not_active Withdrawn
- 2004-03-05 TW TW093105834A patent/TWI261265B/zh not_active IP Right Cessation
- 2004-03-29 JP JP2004096633A patent/JP2005196929A/ja active Pending
- 2004-05-28 CN CNB2004100424005A patent/CN100419911C/zh not_active Expired - Fee Related
-
2009
- 2009-10-16 JP JP2009239836A patent/JP5102268B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN1637943A (zh) | 2005-07-13 |
DE102004010353A1 (de) | 2005-07-28 |
US20050141287A1 (en) | 2005-06-30 |
US6961270B2 (en) | 2005-11-01 |
JP2005196929A (ja) | 2005-07-21 |
TWI261265B (en) | 2006-09-01 |
KR20050068332A (ko) | 2005-07-05 |
KR100605574B1 (ko) | 2006-07-28 |
TW200522083A (en) | 2005-07-01 |
JP2010080047A (ja) | 2010-04-08 |
CN100419911C (zh) | 2008-09-17 |
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