JP2008235728A - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2008235728A
JP2008235728A JP2007075858A JP2007075858A JP2008235728A JP 2008235728 A JP2008235728 A JP 2008235728A JP 2007075858 A JP2007075858 A JP 2007075858A JP 2007075858 A JP2007075858 A JP 2007075858A JP 2008235728 A JP2008235728 A JP 2008235728A
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Prior art keywords
layer
pad
wiring layer
semiconductor device
wiring
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Granted
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JP2007075858A
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JP2008235728A5 (ja
JP5192163B2 (ja
Inventor
Takeshi Igarashi
武司 五十嵐
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Sumitomo Electric Device Innovations Inc
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Sumitomo Electric Device Innovations Inc
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Priority to JP2007075858A priority Critical patent/JP5192163B2/ja
Priority to US12/054,087 priority patent/US8222736B2/en
Publication of JP2008235728A publication Critical patent/JP2008235728A/ja
Publication of JP2008235728A5 publication Critical patent/JP2008235728A5/ja
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Publication of JP5192163B2 publication Critical patent/JP5192163B2/ja
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Abstract

【課題】Ａｌパッド上にボンディングワイヤを形成することによるＡｌパッドとＡｕ配線層との反応を抑制すること。
【解決手段】本発明は、化合物半導体層１２上に設けられ、Ａｌを含み、かつボンディング領域２８を避けて設けられた配線接続部２６を有するパッド２０と、パッド２０の配線接続部２６に電気的に接続されたＡｕを含む配線層３４と、配線接続部２６と配線層３４との間に設けられたバリア層３２と、を具備する半導体装置である。
【選択図】図３

Description

本発明は、半導体装置に関し、特にＡｕを含む配線層とＡｌを含むボンディングパッドとを有する半導体装置に関する。
インバータ、コンバータやスイッチングレギュレータのスイッチに用いられる高電力用半導体装置には主にシリコン基板を用いた半導体装置が用いられている。この半導体装置においては、半導体チップに接続されるボンディングワイヤに大電流が流れるため、ボンディングワイヤは抵抗率の小さなＡｌ（アルミニウム）が用いられている。一方、シリコン基板を用いた半導体チップ上に形成される配線層は一般的にＡｌを用いている。よって、Ａｌを主に含むボンディングパッド（以下、Ａｌパッド）に、Ａｌを主に含むボンディングワイヤ（以下、Ａｌワイヤ）をボンディングすることとなる。
近年、ＧａＮ（窒化ガリウム）等のＩＩＩ−Ｖ族化合物半導体層を有する半導体装置を用いた高電力用半導体装置の開発が進められている。ＩＩＩ−Ｖ族化合物半導体層を用いた半導体チップにおいては、Ａｕ（金）を主に含む配線層（以下、Ａｕ配線層）が用いられる。これは、半導体層に接触するオーミック電極あるいはゲート電極等の電極としてＡｕを含む電極が用いられるためである。
ＡｌとＡｕは２００℃程度になると反応し金属間化合物を形成する。この化合物は抵抗率が高いため、ＡｌとＡｕとの接触箇所の電気抵抗が大きくなってしまう。この課題はパープルプレーグ（ＡｕＡｌ２の生成）として知られている。そこで、特許文献１のように、Ａｌを主に含む配線層（Ａｌ配線層）にＡｕを主に含むボンディングワイヤ（Ａｕワイヤ）を接続する際は、Ａｌ配線層上にバリア層を介しＡｕを主に含むパッド（Ａｕパッド）を形成し、Ａｕパッド上にＡｕワイヤを接続する。また、特許文献２及び３のように、Ａｌ配線層とＡｕ配線層との間にもバリア層を形成する。これにより、ＡｌとＡｕとの反応を抑制することができる。
特開昭５９−２１０６５６号公報 特開平１１−１６２９９６号公報 特開２００６−１７３３８６号公報
しかしながら、図１のように、化合物半導体の基板１０上に形成されたＡｕ層３４（Ａｕ配線層）にバリア層７２を介しＡｌパッド７０を形成し、Ａｌパッド７０にＡｌワイヤ４０を接続すると、後述するがＡｌとＡｕとの反応が生じてしまうことがわかった。
本発明は、上記課題に鑑みなされたものであり、Ａｌパッド上にボンディングワイヤを形成することによる、ＡｌパッドとＡｕ配線層との反応を抑制することを目的とする。
本発明は、化合物半導体層上に設けられ、Ａｌを含み、かつボンディング領域を避けて設けられた配線接続部を有するパッドと、前記パッドの前記配線接続部に電気的に接続されたＡｕを含む配線層と、前記配線接続部と前記配線層との間に設けられたバリア層と、を具備することを特徴とする半導体装置である。本発明によれば、パッドにボンディングワイヤが接続されるべきボンディング領域を避けて設けられた配線接続部において、配線層がバリア層を介しパッドに接続されている。これにより、ワイヤボンディングにより、パッドと配線層とが反応することを抑制できる。
上記構成において、前記半導体装置の使用上限温度は２００℃以上である構成とすることができる。この構成によれば、ＡｌとＡｕとが反応する温度である２００℃以上においても、ＡｌとＡｕとの反応を抑制することができる。
前記ボンディング領域に接続されるべきボンディングワイヤの太さは１００μｍφ以上である構成とすることができる。この構成によれば、ボンディングの際パッドに加わる圧力が大きい場合も、ＡｌとＡｕとの反応を抑制することができる。
上記構成において、前記配線層の端部において、前記配線層と前記パッドとの間に設けられた第１絶縁層を具備する構成とすることができる。この構成によれば、パッド上の配線層の端部において、ＡｌとＡｕとの反応を抑制することができる。
上記構成において、前記パッドの端部において、前記配線層と前記パッドとの間に設けられた第２絶縁層を具備する構成とすることができる。この構成によれば、パッドの端部におけるＡｕとＡｌが反応を抑制することができる。
上記構成において、前記パッドは第１層と該第１層上の第２層とからなり、前記配線層は前記第１層上に延在することにより前記パッドに接続され、前記ボンディング領域は前記第２層に設けられている構成とすることができる。この構成によれば、パッド端部のＡｌとＡｕとの反応を抑制し、かつボンディング領域に接続されるべきボンディングワイヤとパッドとの密着強度を保つことができる。
上記構成において、前記第２層は前記配線層上に第３絶縁層を介し延在する構成とすることができる。
上記構成において、前記バリア層は、ＴｉＮ、ＴｉＷＮ、ＷＮ、ＷＳｉＮ及びＴａＮのいずれかを含む構成とすることができる。
上記構成において、前記バリア層の厚さは１００ｎｍから２００ｎｍである構成とすることができる。
上記構成において、前記ボンディングワイヤはＡｌを含む構成とすることができる。この構成によれば、ボンディングワイヤとパッドとの間での金属間反応を抑制することができる。
本発明によれば、パッドにボンディングワイヤが接続されるべきボンディング領域を避けて設けられた配線接続部において、配線層がバリア層を介しパッドに接続されている。これにより、ワイヤボンディングにより、パッドと配線層とが反応することを抑制できる。
まず、図１に係る構造において、Ａｌパッド７０とＡｕ層３４とが反応する原因について調査した。その結果、Ａｌワイヤ４０をＡｌパッド７０にワイヤボンディングした際に、バリア層７２が破壊されることが原因であることがわかった。ワイヤボンディングする場合は、半導体チップに加える熱及び超音波並びにワイヤツールがパッドに加える圧力の寄与により、ボンディングワイヤとパッドとを機械的及び電気的に接続する。ＡｕワイヤをＡｕパッドにボンディングする場合は、熱と超音波が主に寄与する（超音波熱圧着）。これに対しＡｌワイヤをＡｌパッドにボンディングする場合は、圧力が主に寄与する。このため、Ａｌワイヤを用いる場合は、Ａｕワイヤに比べ大きな圧力が必要となる。このため、特許文献１のような配線層上にバリア層を介しパッドが形成される構造では、バリア層が破壊されるものと考えられる。そこで、バリア層の破壊を抑制する実施例を以下に説明する。
実施例１は、ＧａＮを用いたＦＥＴ（Ｆｉｅｌｄ Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ）の例である。図２は実施例１に係る半導体装置内の半導体チップの平面図である。サファイア基板またはＳｉＣ（炭化シリコン）等の基板１０上にＧａＮを含む半導体層であるＧａＮ系半導体層が形成されている。ＧａＮ系半導体層上には、上からＡｌ／Ｔｉ（チタン）からなるソース電極５０及びドレイン電極５２、上からＡｕ／Ｎｉ（ニッケル）からなるゲート電極５４が形成されている。ソース電極５０、ドレイン電極５２及びゲート電極５４はフィンガを形成している。ＦＥＴ１４は複数のフィンガで構成されている。すなわち、マルチフィンガ構造を有している。ソース電極５０及びドレイン電極５２上にはそれぞれ配線層３０ａ及び３０ｂが形成されている。配線層３０ａ及び３０ｂは櫛型をしており、フィンガがバスバーに接続されている。配線層３０ａのバスバーがＡｌパッド２０ａ上に延在することにより、配線層３０ａとＡｌパッド２０ａとが電気的に接続されている。配線層３０ｂとＡｌパッド２０ｂにおいても同様である。各ゲート電極５４はバスバー５６を介しゲートパッド５８に接続される。ゲートパッド５８とＡｌパッド２０ｃとは配線層３０ｃを介し接続される。各配線層３０ａから３０ｃは、バリア層とＡｕ層とから構成される。各Ａｌパッド２０ａから２０ｃには、１または複数のＡｌワイヤ４０が接続されている。
図３（ａ）及び図３（ｂ）は基板１０上に設けられたＡｌパッド２０と配線層３０とからなるパッド構造を示す平面図及び断面図である。図３（ａ）及び図３（ｂ）を参照に、基板１０上にＧａＮ系半導体層である化合物半導体層１２が設けられている。化合物半導体層１２上にＡｌパッド２０及び配線層３０が形成されている。なお、化合物半導体層１２上に層間絶縁膜や保護膜等の絶縁膜を介しＡｌパッド２０及び配線層３０が形成されていてもよい。また、Ａｌパッド２０及び配線層３０の一部は、化合物半導体層１２を介さず基板１０上に設けられていてもよい。Ａｌパッド２０上に配線層３０が延在することにより、配線層３０とＡｌパッド２０とが電気的に接続されている。
Ａｌパッド２０は膜厚が例えば２μｍである。Ａｌパッド２０上には太さが２００μｍから３００μｍのＡｌワイヤ４０が接続されている。配線層３０は、バリア層３２とバリア層３２上のＡｕ層３４（Ａｕを含む配線層、Ａｕ配線層）とからなる。バリア層３２は、例えば膜厚が５０ｎｍから３００ｎｍ、好ましくは１００から２００ｎｍのＴｉＮ（窒化チタン）やＴｉＷＮ（窒化チタンタングステン）等である。バリア層３２として、他にＷＮ（窒化タングステン）、ＷＳｉＮ（窒化珪化タングステン）またはＴａＮ（窒化タンタル）等を用いることもできる。バリア層３２の膜厚が薄すぎると膜厚のばらつき等によりより薄い箇所が生じるためバリア性が小さくなってしまう。一方、膜厚が厚すぎると、バリア層３２をエッチングする際のオーバーエッチング時間が長くなり、バリア層３２下の下地（実施例１では化合物半導体層１２）がエッチングされてしまう。また、処理時間も長くなってしまう。よって、バリア層３２の膜厚は例えば５０ｎｍから３００ｎｍであり、好ましくは１００ｎｍから２００ｎｍである。Ａｕ層３４の膜厚は例えば５μｍから１０μｍである。
実施例１によれば、Ａｌパッド２０にＡｌワイヤ４０が接続される領域外において、配線層３０がＡｌパッド２０に電気的に接続している。つまり、Ａｌパッド２０は、Ａｌワイヤ４０が接続すべき領域であるボンディング領域２８と、Ａｕ層３４が接続されている配線接続部２６と、を有しており、配線接続部２６はボンディング領域２８を避けて設けられている。このように、Ａｌワイヤ４０をＡｌパッド２０に接続しているため、Ａｌワイヤ４０とＡｌパッド２０とでは金属間反応は生じない。また、Ａｌパッド２０と配線層３０とは、Ａｌワイヤ４０が接続されるボンディング領域２８以外で接続している。よって、図１の比較例のように、Ａｌワイヤ４０のボンディングにより、Ａｌパッド７０と配線層３０とが反応することを抑制できる。このように、Ａｌパッド２０上にＡｌワイヤ４０を形成することによる、Ａｌパッド２０と配線層３０との反応を抑制することができる。
また、バッド２０の配線接続部２６とＡｕ層３４（Ａｕ配線層）との間にバリア層３２が設けられている。これにより、Ａｌパッド２０と配線層３０とが接触している領域におけるＡｌパッド２０と配線層３０との反応を抑制することができる。バリア層３２はＴｉＮ、ＴｉＷＮ等例示した材料以外にも、ＡｌとＡｕとの反応を抑制する材料であればよい。また、バリア層３２とＡｕ層３４との間またはバリア層４２の下に密着層等の別の導電層が設けられていてもよい。
実施例１に係る半導体装置によれば、使用上限温度は２００℃以上とすることができる。ＡｌパッドとＡｕワイヤとの接合強度はパープルプレーグにより１５０℃〜２００℃以上で劣化することが知られている。ＡｕパッドにＡｌワイヤを接合した場合も同様であると考えられる。よって、半導体装置の使用上限温度が２００℃以上の場合、実施例１のパッド構造が有効である。なお、半導体装置の使用上限温度は、半導体装置を動作させる際、信頼性を保証される温度であり半導体装置ごとに定められた温度である。
また、ＡｌとＡｕとの接触部に不純物が存在するとＡｌとＡｕとによる金属間化合物の生成が加速すると考えられている。半導体チップを樹脂封止する場合、封止樹脂のガラス転位温度は一般的に１５０℃〜２００℃である。ガラス転位温度を越えると封止樹脂の熱膨張係数が増加する。よって、１５０℃〜２００℃以上では樹脂と半導体チップとの間に隙間が生じる。この隙間を介し侵入した酸素が封止樹脂を酸化し、酸化物の分解生成物がＡｌとＡｕの接合部に不純物として供給される。以上により、樹脂封止された半導体装置においては、使用上限温度が２００℃以上の場合、特にＡｌとＡｕの反応が起こりやすい。よって、実施例１のパッド構造が特に有効である。
さらに、高電力用途の半導体装置においては、供給される電流量が大きく発熱量が大きいため、使用環境温度は実質的に２００℃以上となる。よって、高電力用途の半導体装置の場合、実施例１に係る構成を用いることが好ましい。
Ａｌワイヤ４０の太さは１００μｍφ以上であることが好ましい。高電力用途の半導体装置に用いられるＡｌワイヤは、大電流を流すため太線ワイヤとよばれ、１００μｍφ以上５００μｍφ以下の太さを有している。高出力用途の半導体装置以外に用いられるＡｌワイヤの太さは５０μｍφ以下であり、太線ワイヤとはその用途が異なっている。Ａｌワイヤ４０が太い場合は、ワイヤボンディングする際、Ａｌパッド２０に加わる圧力が大きくなる。よって、太線ワイヤを用いる場合バリア層３２が破壊され易く、実施例１に係るパッド構造を用いることが好ましい。なお、例えば、太さ２５μｍφのＡｕワイヤをＡｕパッド上にボンディングする場合の荷重は０．５Ｎ程度であるが、太さ２５０μｍφのＡｌワイヤをＡｌパッド上にボンディングする場合の荷重は５Ｎ程度である。このように、ワイヤの種類と太さが異なることにより１桁大きい圧力がパッドに加わる。
コンバータ、インバータまたはスイッチングレギュレータのスイッチに用いる高出力用途の半導体装置は、印加される電圧の２．５倍の耐圧が要求される。よって、日本における１００Ｖの交流に用いる場合は、耐圧は２５０Ｖ以上が求められる。さらに、各国に使用するため２４０Ｖの交流にも用いられる場合は、６００Ｖ以上の耐圧が求められる。よって、高出力用途の半導体装置とは、例えば、耐圧が２５０Ｖ以上であり、好ましくは６００Ｖ以上である。
高出力用途の半導体装置において求められる耐圧は、ＦＥＴの場合はドレイン耐圧である。バイポーラトランジスタまたは（絶縁ゲートバイポーラトランジスタ）の場合はコレクタ耐圧である。
実施例１は、化合物半導体層１２として、ＧａＮ系半導体層の例であったが、ＧａＡｓ系半導体層であってもよい。ＧａＡｓを用いた半導体装置においても、Ａｕ配線層が一般的に用いられており、Ａｌワイヤをワイヤボンディングする場合は、実施例１に係るパッド構造を適用することが好ましい。このように、化合物半導体層１２はＩＩＩ−Ｖ族化合物半導体層であることが好ましい。
ＧａＮ系半導体層を用いる場合、ソース電極５０及びドレイン電極５２は上からＡｌ／Ｔａ（タンタル）、Ａｌ／Ｐｄ（パラジウム）／Ｔａ、またはＭｏ（モリブデン）／Ｔａを用いることができる。ゲート電極５４としては、上から（Ａｕ、Ｃｕ（銅）またはＡｌ）／ＴｉＷＮ、（Ａｕ、ＣｕまたはＡｌ）／（ＴｉＷＮまたはＰｄ）／（Ｎｉ、ＴｉまたはＩｒ（イリジウム））を用いることができる。化合物半導体層上に形成される電極は、特にこれらに限られないが、いずれかの電極がＡｕを含む場合、Ａｕ配線層を用いることが多い。よって、化合物半導体層上に形成された電極はＡｕを含むことが好ましい。
図４は、実施例２のパッド構造を示す図である。図４を参照に、実施例２においては、Ａｌパッド２０上の配線層３０の端部（ボンディング領域２８と配線接続部２６との間）において、配線層３０がＡｌパッド２０から離間している。その他の構成は実施例１の図３（ｂ）と同じであり説明を省略する。実施例２のように、配線層３０の端部において、配線層３０はＡｌパッド２０から離間していてもよい。
図５（ａ）及び図５（ｂ）は、実施例３のパッド構造を示す図である。図５（ａ）及び図５（ｂ）を参照に、実施例３においては、例えば酸化シリコンまたは窒化シリコンからなる第１絶縁層６２が、Ａｌパッド２０上の配線層３０の端部（ボンディング領域２８と配線接続部２６との間）において、配線層３０とＡｌパッド２０との間に設けられている。その他の構成は実施例１の図３（ａ）及び図３（ｂ）と同じであり説明を省略する。実施例３によれば、Ａｌパッド２０上の配線層３０の端部において、製造工程中にＡｕとＡｌとが接触することを抑制することができる。さらに、半導体装置の動作に伴うイオンマイグレーション等によりＡｕまたはＡｌがバリア層３２表面を移動し、ＡｕとＡｌとが反応することを抑制することができる。
図６（ａ）及び図６（ｂ）は、実施例４のパッド構造を示す図である。図６（ａ）及び図６（ｂ）を参照に、実施例４においては、Ａｌパッド２０の端部において、配線層３０とＡｌパッド２０との間に第２絶縁層６４が設けられている。その他の構成は実施例１の図３（ａ）及び図３（ｂ）と同じであり説明を省略する。配線層３０がＡｌパッド２０上に乗り上げる段差においては、バリア層３２の被覆性劣化等により、ＡｕとＡｌが反応することが起こりうる。実施例４によれば、Ａｌパッド２０の端部におけるＡｕとＡｌが反応を抑制することができる。
図７（ａ）及び図７（ｂ）は、実施例５のパッド構造を示す図である。図７（ａ）及び図７（ｂ）を参照に、実施例５においては、絶縁層６３が、実施例３の第１絶縁層と実施例４の第２絶縁層とを有し、環状をなしている。その他の構成は実施例１の図３（ａ）及び図３（ｂ）と同じであり説明を省略する。実施例５によれば、Ａｌパッド２０上の配線層３０の端部及びＡｌパッド２０端部の配線層３０の乗り上げ部分におけるＡｕとＡｌとの反応を抑制することができる。
図８は、実施例６のパッド構造を示す図である。図８を参照に、実施例６においては、Ａｌパッド２０はＡｌからなる第１層２２と第１層２２上のＡｌからなる第２層２４とからなる。配線層３０は第１層２２上に延在することによりＡｌパッド２０に接続される。Ａｌワイヤ４０は第２層２４上に接続されている。その他の構成は実施例１の図３（ｂ）と同じであり説明を省略する。Ａｌパッド２０の膜厚はＡｌワイヤ４０とＡｌパッド２０との密着強度を保つため、２μｍ以上あることが好ましい。一方、Ａｌパッド２０の膜厚が大きいと、実施例４において説明したように、Ａｌパッド２０端部の配線層３０の乗り上げ部分において、ＡｕとＡｌとが反応しやすい。実施例６によれば、第１層２２の膜厚を小さくすることにより、Ａｌパッド２０端部の配線層３０の乗り上げ部分の段差を小さくすることができる。これにより、ＡｌとＡｕとの反応を抑制することができる。一方、第２層２４を厚くすることにより、Ａｌワイヤ４０とＡｌパッド２０との密着強度を保つことができる。
図９（ａ）及び図９（ｂ）は、実施例７のパッド構造を示す図である。図９（ａ）及び図９（ｂ）を参照に、実施例７においては、第２層２４が配線層３０上に第３絶縁層６６を介し延在している。その他の構成は実施例６の図８（ａ）及び図８（ｂ）と同じであり、説明を省略する。実施例７によれば、配線層３０の端部を第３絶縁層６６及び第２層２４が覆っているため、Ａｌワイヤ４０が配線層３０に接触することを抑制することができる。
図１０（ａ）及び図１０（ｂ）は、実施例８のパッド構造を示す図である。図１０（ａ）及び図１０（ｂ）を参照に、実施例８においては、第１絶縁層６２が、第１層２２上の配線層３０の端部において、配線層３０と第１層２２との間に設けられている。その他の構成は実施例７の図９（ａ）及び図９（ｂ）と同じであり説明を省略する。実施例８によれば、第１絶縁層６２により、第１層２２上の配線層３０の端部においてＡｕとＡｌが反応することを抑制することができる。また、第３絶縁層６６及び第２層２４によりＡｌワイヤ４０が配線層３０に接触することを抑制することができる。
図１１は、実施例９のパッド構造を示す図である。図１１を参照に、実施例９においては、Ａｌパッド２０は配線層３０上に延在することにより配線層３０と接続している。配線層３０はＡｕ層３４上にバリア層３２が形成されている。つまり、Ａｕ層３４とＡｌパッド２０との間にバリア層３２が設けられている。その他の構成は実施例１の図３（ｂ）と同じであり説明を省略する。
図１２は、実施例１０のパッド構造を示す図である。図１２を参照に、実施例１０においては、配線層３０の端部において、配線層３０とＡｌパッド２０との間に第４絶縁層６８が設けられている。その他の構成は実施例９の図１１と同じであり説明を省略する。実施例１０によれば、第４絶縁層６８により、配線層３０の端部におけるＡｌとＡｕの反応を抑制することができる。
ＧａＮを用いたＦＥＴでは、ソース電極５０及びドレイン電極５２はＡｌ／Ｔｉ等のＡｌを含む電極が一般的に用いられる。実施例１から実施例８によれば、このようなＡｌを含む電極を形成する際にＡｌパッド２０を同時に形成することができる。また、Ａｌを含む電極を用いない場合は、Ａｌパッド２０を形成した後に配線層３０を形成してもよいが、実施例９及び実施例１０のように、配線層３０を形成した後にＡｌパッド２０を形成することができる。このように、Ａｌを含む電極を用いる場合及び、用いない場合のいずれの場合も、実施例１から実施例８並びに実施例９及び実施例１０のいずれの構造も選択することができる。
以上、発明の好ましい実施例について詳述したが、本発明は係る特定の実施例に限定されるものではなく、特許請求の範囲に記載された本発明の要旨の範囲内において、種々の変形・変更が可能である。
図１は比較例のパッド構造の断面図である。 図２実施例１の半導体チップの平面図である。 図３（ａ）は、実施例１のパッド構造の平面図、図３（ｂ）は図３（ａ）のＡ−Ａ断面図である。 図４は実施例２のパッド構造の断面図である。 図５（ａ）は、実施例３のパッド構造の平面図、図５（ｂ）は図５（ａ）のＡ−Ａ断面図である。 図６（ａ）は、実施例４のパッド構造の平面図、図６（ｂ）は図６（ａ）のＡ−Ａ断面図である。 図７（ａ）は、実施例５のパッド構造の平面図、図７（ｂ）は図７（ａ）のＡ−Ａ断面図である。 図８は実施例６のパッド構造の断面図である。 図９（ａ）は、実施例７のパッド構造の平面図、図９（ｂ）は図９（ａ）のＡ−Ａ断面図である。 図１０（ａ）は、実施例８のパッド構造の平面図、図１０（ｂ）は図１０（ａ）のＡ−Ａ断面図である。 図１１は実施例９のパッド構造の断面図である。 図１２は実施例１０のパッド構造の断面図である。
符号の説明
１０ 基板
１２ 化合物半導体層
２０ Ａｌパッド
２２ 第１層
２４ 第２層
３０ 配線層
３２ バリア層
３４ Ａｕ層
４０ Ａｌワイヤ
６２ 第１絶縁層
６３ 絶縁層
６４ 第２絶縁層
６６ 第３絶縁層
６８ 第４絶縁層

Claims (10)

  1. 化合物半導体層上に設けられ、Ａｌを含み、かつボンディング領域を避けて設けられた配線接続部を有するパッドと、
    前記パッドの前記配線接続部に電気的に接続されたＡｕを含む配線層と、
    前記配線接続部と前記配線層との間に設けられたバリア層と、を具備することを特徴とする半導体装置。
  2. 前記半導体装置の使用上限温度は２００℃以上であることを特徴とする請求項１記載の半導体装置。
  3. 前記ボンディング領域に接続されるべきボンディングワイヤの太さは１００μｍφ以上であることを特徴とする請求項１記載の半導体装置。
  4. 前記配線層の端部において、前記配線層と前記パッドとの間に設けられた第１絶縁層を具備することを特徴とする請求項１記載の半導体装置。
  5. 前記パッドの端部において、前記配線層と前記パッドとの間に設けられた第２絶縁層を具備することを特徴とする請求項1記載の半導体装置。
  6. 前記パッドは第１層と該第１層上の第２層とからなり、
    前記配線層は前記第１層上に延在することにより前記パッドに接続され、
    前記ボンディング領域は前記第２層に設けられていることを特徴とする請求項１記載の半導体装置。
  7. 前記第２層は前記配線層上に第３絶縁層を介し延在することを特徴とする請求項１記載の半導体装置。
  8. 前記バリア層は、ＴｉＮ、ＴｉＷＮ、ＷＮ、ＷＳｉＮ及びＴａＮのいずれかを含むことを特徴とする請求項１記載の半導体装置。
  9. 前記バリア層の厚さは１００ｎｍから２００ｎｍであることを特徴とする請求項１記載の半導体装置。
  10. 前記ボンディングワイヤはＡｌを含むことを特徴とする請求項３記載の半導体装置。
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US8278667B2 (en) 2009-08-11 2012-10-02 Fuji Xerox Co., Ltd. Light-emitting element and light-emitting element fabrication method
JP2014146780A (ja) * 2013-01-28 2014-08-14 Win Semiconductors Corp 半導体集積回路
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JP2017163111A (ja) * 2016-03-11 2017-09-14 Ｄｏｗａエレクトロニクス株式会社 半導体光デバイスおよびその製造方法

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