CN100472779C - 模块化器件 - Google Patents
模块化器件 Download PDFInfo
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- CN100472779C CN100472779C CNB038015625A CN03801562A CN100472779C CN 100472779 C CN100472779 C CN 100472779C CN B038015625 A CNB038015625 A CN B038015625A CN 03801562 A CN03801562 A CN 03801562A CN 100472779 C CN100472779 C CN 100472779C
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- module part
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- bonded circuitry
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- circuitry substrate
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Abstract
本发明的模块化器件,通过层叠电路基板(3)和接合电路基板(5)并使之一体化,从而实现安装元件(1)的内置。其中,至少在电路基板(3)的单面安装有一个以上的安装元件(1);在接合电路基板(5)上的与安装在上述电路基板(3)的单面上的至少一个以上的安装元件(1)对应的部分,设有能嵌入该安装元件(1)的凹部(4)或孔。这样,可以提供确保层间连接的可靠性、可高精度、高密度地内置多个安装元件、可靠性高的模块化器件。
Description
技术领域
本发明涉及一种在电子产品、通信装置中应用的模块化器件。
背景技术
近年来,在电子产品日益小型化的进程中,非常需要小型、薄型且高精细的多层基板。而且,特开平11—45955号公报公布了将半导体元件及电子元件(电容元件、电阻元件、滤波元件、振荡元件等)等安装元件内置在布线基板上的小型布线基板的技术。上述现有技术的布线基板,由将热固化树脂或热固化性树脂作为主要成分的复合材料构成。而且,所有使用的基板,都是在软质(未固化或半固化状态)的状态下层叠后,将层叠物统一固化的。在层叠的状态时,由于整个基板都尚未固化,所以在固化工序中,容易受到热引起的膨胀收缩的影响。其结果,就出现内部电极相互间的连接可靠性下降这一问题。进而,由于基板尺寸的变化,难以消除内置元件周围的空隙。就是说,还存在因容易吸潮等的影响,引起可靠性下降的问题。
发明内容
本发明的目的在于,减少在层叠一体化后的固化工序中出现的、受热后产生的尺寸变化,以确保层间连接的可靠性。并提供精确地而且是高密度地内置多个安装元件的小型模块式器件。
提供的模块化器件包括:电路基板,其具有至少两层的电路图案和将所述两层的电路图案连接的通路孔;至少一个第一安装元件,安装在所述电路基板的至少单面上;以及接合电路基板,具有凹部或者孔,按照将所述安装元件压入到所述凹部或者孔中的方式层叠在所述电路基板上。其中,所述接合电路基板具有至少一层电路图案和填充了导电性糊料的通路孔,所述安装元件与所述电路基板以及所述接合电路基板之间没有间隙。
另外,优选在上述模块化器件中,所述电路基板在其上面和下面分别具有至少一个安装元件,在所述电路基板的上面和下面分别层叠不同的接合电路基板。
另外,提供的模块化器件包括:第一电路基板,其具有至少两层的电路图案和将所述两层的电路图案连接的通路孔;至少一个安装元件,安装在所述第一电路基板上;接合电路基板,两面具有凹部或者孔,层叠在所述第一电路基板上;第二电路基板,层叠在所述接合电路基板上,安装有至少一个第二安装元件。所述第二安装元件面向所述接合电路基板安装,所述第一和第二安装元件与所述第一电路基板、所述第二电路基板以及所述接合电路基板之间没有间隙;将所述第一和第二安装元件压入到所述凹部或者孔中。
附图说明
图1是本发明第1实施方式的模块化器件的分解剖面图。
图2是本发明第1实施方式的模块化器件的分解立体图。
图3A~图3F是表示本发明第1实施方式的接合电路基板制造工序的剖面图。
图4A和图4B是表示接合电路基板未形成凹部时的状态的剖面图。
图5A和图5B是表示本发明第1实施方式的的接合电路基板形成凹部时的状态的剖面图。
图6A和图6B是表示本发明第1实施方式的模块化器件的剖面图。
图7是表示本发明第1实施方式的接合电路基板形成突起电极的剖面图。
图8是表示本发明第1实施方式的电路基板形成壁的剖面图。
图9A~图9D是表示本发明第1实施方式的接合电路基板的各种凹部的剖面图。
图10A~图10D是表示本发明第1实施方式的各种接合电路基板的剖面图。
图11A和图11B是表示本发明第1实施方式的安装元件的安装工序的剖面图。
图12A和图12B是表示本发明第1实施方式的安装元件的安装工序的剖面图。
图13A~图13D是表示本发明第1实施方式的各种凹部的结构的剖面图。
图14是本发明第1实施方式的统一制造多个模块化器件的状态的分解立体图。
图15A是本发明第2实施方式的模块化器件的分解剖面图。
图15B是本发明第2实施方式的模块化器件的剖面图。
图16A是本发明第3实施方式的模块化器件的分解剖面图。
图16B是本发明第3实施方式的模块化器件的剖面图。
图17A是本发明第4实施方式的模块化器件的分解剖面图。
图17B是本发明第4实施方式的模块化器件的剖面图。
图18A是本发明第4实施方式的模块化器件的其它分解剖面图。
图18B是本发明第4实施方式的模块化器件的其它剖面图。
图19A是本发明第5实施方式的模块化器件的其它分解剖面图。
图19B是本发明第5实施方式的模块化器件的其它剖面图。
符号说明
1、1A、1B、1E—安装部件;2—布线图案;3、3A、3B—电路基板;4、4A、4B—凹部;5、5A、5B、5C、5D—接合电路基板;6、6B、6C、92—通路孔;7—贯穿通路孔;8A、8B—端子;12—底面;13、115—屏蔽层;14—接地电极;15—散热部件;20—钎焊料突起;21—抗蚀剂;31、32、61、62—连接端子;33—常数调整图案;51—定位壁;63—导电性糊料;64—突起电极;65—粘接层;71—密封树脂;81、96—定位孔;91A、91B—叠层片;93—复制薄膜;94—布线图案;95A、95B—孔;102—弹性体;111、112、113—端子;114—端面电极;116—热传导层;141—模块化部件。
具体实施方式
下面,参照附图,讲述本实施方式的示例。此外,附图是示意图,而不是正确显示各相关形位尺寸的图形。
(第1实施方式)
使用图1,讲述第1实施方式的模块化器件。该模块化器件包括:电路基板3、搭载在形成在该电路基板3的一个主面上的连接端子31之上的多个安装元件1、以及具有嵌入该安装元件1的凹部4、且具有与电路基板3电性及机械性接合的功能的接合电路基板5。电路基板3具有布线图案2、通路孔(via hole)6和贯穿通路孔(through hole)7。而且,电路基板3具有2层以上的多层布线结构。在电路基板3的上面,还配置着连接端子31的连接端子32。连接端子31,是旨在安装安装元件1的连接端子。连接端子32与在接合电路基板5上形成的通路孔6进行电连接。这样,就构成模块化器件的电路。作为将模块化器件与主板连接的外部连接端子,该电路基板3还具有端子8A和8B。端子8A具有使用在电路基板3的下面形成众多的端子电极的LGA(Land Grid Array)结构。端子8B具有在电路基板3的侧面形成众多的端面电极结构。进而如图2所示,在电路基板3的上面的电路图案2上,附加常数调整图案33。常数调整图案33的作用如下:在构成模块化器件的电路中,模拟电路等往往需要最终性地调整电路常数,以确保最佳的电特性。可是内置安装元件1后,就不能轻易调整电特性。因此,在电路图案2上,附加电路的常数调整功能。在电路基板3上,使用高速的安装机装置,安装作为安装元件1的矩形片状电阻、电容器、电感器、EMC防止用元件等无源元件。这时,安装元件1的安装,就像敲击电路基板3。其结果,电路基板3将受到相当大的冲击。
为此,电路基板3使用了能够承受这种机械性冲击的刚性较高的基板材料。作为这种刚性较高的基板的例子,在有机系材料方面,可以举出FR—4、CEM—3,在无机系材料方面,可以举出陶瓷基板、金属基板。另外,还可以使用由包含无机充填物和热固化树脂的混合物构成的组合树脂基板的固化件等。
另外,安装元件1,不仅包括上述的无源元件,还包括由半导体构成的经过封装的IC等有源元件。作为安装元件,还包括:类似芯片LCR、CSP那样在下面及侧面等处有连接端子的元件;以及象FET那样,在下面及与下面相对的上面形成连接端子的元件;或者用电极覆盖连接端子以外的面,使之具有散热性和屏蔽效果的高频IC元件等。而且,在电路基板3上安装与这些安装元件对应的连接端子31。
在本第1实施方式中,将安装元件1安装到电路基板3上的方法,采用软钎焊接合。在电路基板3上,使用厚度为150μm的金属掩膜,将Sn—Ag—Cu的膏状钎焊料,涂敷在电路基板3的连接端子31上。接着,将安装元件1放到所定的位置,在峰值温度为260℃中保持5秒钟的回流条件下,熔化后冷却连接固定。
这时,为了进行软钎焊,要激活连接端子31的表面。而且,为了便于进行软钎焊,还要使用助焊剂成分。接合后,如果残留助焊剂成分,就会腐蚀接合部位,造成断线。其结果,使可靠性显著下降。为了避免出现这种情况,就用以异丙醇为主要成分的清洗剂等,去除残留的助焊剂成分。这时安装上去的经过封装的IC及片状元件等安装元件1,和电路基板3之间存在200μm以下的极其微小的间隙。残留在该间隙中的助焊剂成分,不易清洗,但靠浸泡无法完全溶解、彻底去除。于是就使用超声波清洗机及高速流体清洗机,对助焊剂进行彻底的清除。
然后,充填由环氧树脂和无机材料充填物构成的密封(underfill)树脂71,以便消除安装元件1和电路基板3之间的间隙。为了能够完全充填,需要降低密封树脂71的粘度。因此将整个电路基板3加热到60℃左右后充填密封树脂71。然后,再加热到150℃,并保持5分钟,进行固化。采用这种安装方法,可以消除安装元件1和电路基板3之间的间隙,确保连接的可靠性。
接合电路基板5,具有孔95A和孔95B。孔95A,是为了嵌入搭载在电路基板3上的安装元件1的孔。孔95B,则是为了嵌入微调电容器等调整用元件的孔。电容的调整,在模块化器件完成后,用激光或RYUUTA(日本精密机械工作株式会社的商品名,是一种手提式研磨工具)对调整常数图案33进行微调。作为接合电路基板5的材料,使用热固化性树脂及热可塑性树脂等。作为热固化性树脂,最好使用耐热性高的环氧树脂、苯酚树脂或氰酸盐树脂。其中,环氧树脂耐热性特别高,所以可以防止安装元件1的发热使接合电路基板5产生热变形而引起的断线及短路。作为热可塑性树脂,可以使用耐热性高的聚酰亚胺,聚醚枫等。下面,讲述以热固化性树脂为主要成分的材料,如图3A所示,进行片状成形。将叠层片91A或91B保持半固化(B步骤)状态,作为预成型材料而使用。
这次使用的叠层片91A或91B的厚度为500μm。如图3B所示,在叠层片的所需位置形成贯穿通路孔。接着,采取并用网线印刷法和真孔吸引法的方法,往贯穿通路孔内充填由金属粉和树脂构成的导电性糊料,形成通路孔92。再接着,如图3C所示,在复制薄膜93上形成布线图案94。然后,如图3D所示,在形成通路孔92的叠层片上,层叠形成有布线图案94的复制薄膜93后压接。再如图3E所示,去掉复制薄膜93。这样,就在叠层片上形成布线图案94。进而,如图3F所示,作成所需的孔95A或95B。同时,还形成与电路基板层叠时使用的定位孔96。这样,构成接合电路基板5的叠层片91A或91B就作好了。在本第1实施方式中,如图2所示,在每个叠层片91A或91B上复制形成所需的布线图案2。接着,形成与安装元件1对应的孔95A,和与常数调整图案33上对应的孔95B。孔95B是在模块化器件完成后,能从外部微调常数调整图案33的孔。
在另一个叠层片91B上,形成与常数调整图案33上对应的孔95B。此外,在叠层片91A或91B上形成孔时,使用激光加工法。由于使用YAG激光及紫外线激光等波长在2μm以下的激光装置,所以开孔之际产生的热量很小。其结果,叠层片91A或91B的热膨胀收缩很小,所以可以高精度进行孔加工。
另外,也可以取代使用激光装置在叠层片91A或91B上形成孔95A或95B,而使用穿孔装置和金属模具形成孔。
接着,将如此形成的叠层片91A和叠层片91B,依次叠放到电路基板3上。这样一来,就能与安装元件1的体积对应,形成具有任意深度和面积的凹部4的接合电路基板5。叠放时,要将销子***电路基板3的定位孔81和接合电路基板5的定位孔96中。对叠层片91A或91B所使用的热固化树脂的种类,没有特殊要求。可以用环氧树脂及聚酰亚胺树脂或苯酚树脂等。另外,为了提高机械强度及散热性能,还可以往热固化树脂中添加无机充填物。作为无机充填物,可以添加二氧化硅及氧化铝或铁电体等。
添加导热系数特别高的氧化铝的叠层片91A或91B,可以形成导热性优异、散热性良好的接合电路基板5。在温度为150~200℃、加压力为100~200kg/cm2的条件下,用热压力机将如此层叠的接合电路基板5和电路基板3一体化。这时,由于热固化性树脂是半固化状态(B步骤),所以用叠层片91A或91B构成的接合电路基板5软化一次之后固化。这时,如图2所示,在电路基板3的上面形成的连接端子32的位置,和在接合电路基板5的上面形成的通路孔6的位置非常吻合。而且、通过将充填在该通路孔6中的导电性糊剂加热压缩后,能使电路基板3和接合电路基板5电连接。此外,还可以在接合电路基板5上形成连接端子32,在电路基板3上形成通路孔6后接合。另一方面,如图4A所示,将搭载安装元件1的电路基板3和接合电路基板5一体化时,如果不形成与安装元件1对应的凹部4,就会造成如下后果。
即:如图4B所示,将接合电路基板5加压·加热后,设置在接合电路基板5上的各布线图案2及通路孔6,就要按照安装元件1的体积,沿水平方向相应地自由移动变形。
这是由于接合电路基板5的、在B步骤状态中的热固化性树脂软化的缘故。本来,高精度地形成的布线图案2,如前所述,是设定成能将接合电路基板5上通路孔6与电路基板3上的连接端子32电连接。可是,上述的移动变形,却使布线图案2及通路孔6出现了错位。换句话说,为了实现模块化器件的小型化,无论怎样高密度、高精度地形成布线图案2及通路孔6,也由于接合时的接合电路基板5的软化造成的移动变形,而不能高精度地连接。为了进行高精度地连接,就需要根据移动变形造成的错位量,扩大图案及连接的通路孔的形状。因此,无法在规定的基板尺寸中形成电路,结果就难以实现模块化器件的小型化。另外,加压力集中在安装元件1上时,还有可能损坏安装元件1。
可是,如图5A所示,在接合电路基板5上设置凹部4,通过将安装元件1嵌入后,就能杜绝热固化树脂的与安装元件1的体积对应的移动变形。进而还能将搭载在电路基板3上的安装元件1固定,所以能够起防止接合电路基板5的各布线图案2及通路孔6的移动变形的防洪堤的作用。其结果,就能限制布线图案2及通路孔6的错位。这样一来,就能进行图5B所示的那种高精度地连接,实现小型化。该凹部4与安装元件1的尺寸公差,可以在安装元件1的长、宽、高尺寸的1%以下。这样,就能杜绝布线图案2的错位。还因为能使加压力不集中在安装元件1上,所以能杜绝安装元件1的破损。其结果,将能使模块化器件具有很高的可靠性。
这样,由于电路基板3和接合电路基板5接合时要加热,所以电路基板3和接合电路基板5,用具有大致相同的热膨胀系数的材料构成。其结果,就能杜绝所述各基板因膨胀收缩而造成的错位,实现位置精度更高的小型模块化器件。如图6A所示,将电路基板3和接合电路基板5一体化后,安装元件1能被毫无间隙地封装。进而成为可以通过孔95B,从外部追加加工常数调整图案33。这样形成模块化器件后,可以通过激光及RYUUTA(商品名;是一种手提式研磨工具)等调整电路的电路常数。调整后,如图6B所示,用以环氧树脂为主要成分的密封材料11,将安装元件1全部毫无间隙地密封。
经过这样毫无间隙地密封,可以确保安装元件1在吸湿回流试验中的高可靠性。假如将电路基板3和接合电路基板5叠层一体化的模块化器件中存在间隙层时,进行JEDEC回流1级的吸湿条件的吸湿回流试验后,其空隙部就会聚积水分。JEDEC回流1级的吸湿条件,是在85℃、85%RH的环境中,吸湿168小时。将这种吸湿状态的模块化器件,通过相当于250℃的回流炉后,水分由于气化,体积就会急剧膨胀。从而要损坏模块化器件。
象本发明的模块化器件那样,毫无空隙地密封后,即使对1级的吸湿回流试验,也不会受到损坏,确保可靠性。
另外,将电路基板3和接合电路基板5一体化时,电路基板3的平均表面粗糙度(Ra)应在10μm以上。
这样,由于接合电路基板5的接合面,能深入到电路基板3的表面的凹凸中,所以能进一步加强电路基板3和接合电路基板5的密着强度。
另外,如图7所示,在接合电路基板5的连接端子62上,形成突起电极64。作为突起电极64,熔化金丝后,用超声波在连接端子62上形成突起的金双头突起,或通过电解和非电解镀层中的至少某一种方法,形成Ni—Au镀层的突起。再通过加压·加热,可以使在电路基板3上形成的、表面经过镀层处理的连接端子32和突起电极64实现金属结合。其结果就能得到更牢固的、连接电阻低的连接。还可以熔化一定量的钎焊料后形成的钎焊料突起,进行软钎焊连接。
另外,本发明的模块化器件,由于是将接合电路基板5层叠到电路基板3上后形成的,所以采用使电路基板3的面积,与接合电路基板5相同或比它大的结构。这样,便于将接合电路基板5层叠到电路基板3上,所以能够提高生产效率。另外,如图8所示,为了使电路基板3和接合电路基板5层叠的位置吻合,在电路基板3的上面,设置了旨在定位的壁51。设置该壁51后,能防止在接合电路基板5上形成的布线图案2及通路孔6,在面内自由流动。其结果,就能保证很高的接合尺寸精度。另外,如图9A所示,接合电路基板5的凹部4A的大小,做成与安装元件的形状相同或略微小一点。其结果,将安装元件1嵌入凹部4A时,接合电路基板5的凹部4A的侧壁面与安装元件1,就带点压入的样子与凹部4A互相嵌合。这样,就可以提高接合的可靠性,使安装元件1和接合电路基板5之间毫无间隙。
另外,如图9B所示,凹部4A的大小,还可以和安装元件1同等以上。这时,容易进行层叠。而且,在层叠加压时,要填埋凹部4A和安装元件1之间形成的间隙。如图9C所示,在凹部4A的壁面形成弹性体102,填埋安装元件1和凹部4A的壁面之间的间隙。其结果,能够完全与外界的空气隔绝,杜绝与安装元件1之间的间隙。而且,可以进一步提高对吸湿回流试验等的可靠性。作为弹性体,使用硅橡胶、含氟橡胶等。另外,如图9D所示,凹部4B的截面形状,可以是***侧为宽梯形的形状。采用梯形形状后,安装元件1和凹部4B在嵌入时,容易定位。在图9A~图9D中,讲述了凹部4A和4B的截面形状。另外,不仅是凹部4A和4B,形成孔时也能获得同样的效果。还有,在本第1实施方式中,作为接合电路基板5,以使用预成型材料的树脂基板为例,进行了讲述。但也可以使用其它刚性高的基板,在接合电路基板5和电路基板3的接合面上形成粘接层。将电路基板3和接合电路基板5叠层后,利用热及压力或能量线,使粘接层固化,一体化。这样来完成模块化器件的制造。能量线,包括电子线、X射线、放射线等。作为刚性高的基板,可以使用已固化的树脂基板、陶瓷基板、金属基板、将包含无机充填物和热固化树脂的混合物固化的复合树脂基板等。作为无机充填物,最好使用氧化铝。这些陶瓷基板、金属基板、以氧化铝为主要成分的复合树脂基板等,导热系数高,所以可以有效地散发来自发热较大的安装元件1的热量。另外,与用预成型材料构成接合电路基板5的材料的不同之处,是在接合电路基板5和电路基板3的接合面上形成粘接层这一点。图10A所示的接合电路基板5,由多层的陶瓷基板构成。在其内层形成将叠层间电连接的通路孔6。在接合电路基板5的下面,形成与安装元件1对应的凹部4,以及从下面稍微突出来的与电路基板3电连接的端子62。正如图10B所示,在接合电路基板5与电路基板3的接合面相对应的表层,形成粘接层65。该粘接层65,涂敷以环氧树脂为主要成分的粘接剂后形成。在与电路基板3的接合中,上述连接端子62,穿破粘接层65,与电路基板3的连接端子32电连接。另外,如图10C所示,在接合电路基板5的表层形成粘接层65时,要避开和电路基板3连接的连接端子62后形成粘接层65。这样,可以进一步提高与电路基板3连接的可靠性。另外,如图10D所示,要避开接合电路基板5的连接端子62后形成粘接层65。在连接端子62上,形成导电性层63,可以使与电路基板3连接的可靠性得到进一步提高。导电性层63,涂敷导电性糊料后形成。另外,作为粘接剂,还可以使用双液性粘接剂及厌气性粘接剂。进而,不仅可以使用液态的粘接剂,还可以使用粘接片的粘接剂。
作为粘接片,是以热固化性树脂或可塑性树脂为主要成分的树脂片,作为充填物,如果包含导电性粒子,就能进一步减少连接电阻。另外,在开关口部形成导电层,就能更进一步减少连接电阻。
作为将安装元件1安装到电路基板3上的方法,有使用钎焊料及导电性糊料的安装方法。特别是安装半导体的双芯片时,有使用各向异导电性树脂片及导电性糊料,在温度较低的状态中连接的安装方式,和使用钎焊料及金,进行高温连接的安装方式。无论哪种方式,都要求搭载双芯片的电路基板3的接合面的平坦度,在10μm以下。尤其是使用钎焊料的安装,适宜于大批量生产,所以被广泛采用。正如图11A所示,将在双芯片上形成钎焊料突起20的安装元件1E,与电路基板3的表面形成的连接端子31连接时,与在双芯片上形成的钎焊料突起20的间距对应,形成连接端子31,可是,如图11B所示,由于间距比较小,所以与电路基板3接合时,钎焊料熔化,往往要流到所定的连接端子以外的其它连接端子处。其结果,造成连接端子间的短路,不能确保电气特性。为了防止这种短路,如图12A所示,在电路基板3上的连接端子31的端子之间,用以树脂为主要成分的抗蚀剂21形成壁。进而在连接端子32以外的部分,也用抗蚀剂21形成壁。如图所示,该抗蚀剂21,是为了防止钎焊料流到布线图案2上所必需的。另外,还可以不是全面形成,而只在需要防止钎焊料流动的部位形成抗蚀剂21。另外,在电路基板3上形成该抗蚀剂21,还可以使它与接合电路基板5上形成的布线图案2对应。接着,如图13A所示,可在接合电路基板5的凹部4的底面12上,形成端子111。这样,可以使端子111与FET等相对的面上具有端子112的安装元件1进行电连接。这时,电连接也可以将接合电路基板5的底面12的端子111与安装元件1的端子112压焊连接。还可以在端子112上形成导电层或各向异导电性片,进行电阻更低的电连接。
另外,可以如图13B所示,在接合电路基板5的凹部4的侧面,形成端子113,从而与安装元件1的端面电极进行电连接。这样可以不经过电路基板3,直接将接合电路基板5和安装元件1电连接。另外,如图13C所示,在接合电路基板5的凹部4的内部,设置由金及铜等导体构成的屏蔽层115。这样,可以将安装元件1产生的噪声的影响,抑制到最小限度。另外,如图13D所示,在接合电路基板5的凹部4的底面12,使用铜等金属,形成导热层116。使在连接端子以外的部分具有散热层的半导体(电源用半导体)等安装元件1与导热层116接触。其结果,可以更有效地将安装元件产生的热量散发出去。此外,在本第1实施方式中,接合电路基板5的与电路基板3的接合面相反一侧的面上,没有搭载安装元件1,但也可以搭载安装元件1。
在本第1实施方式中,只对一个一个制作模块化器件的情况进行了讲述。但也能如图14所示,采用统一作成多个模块化器件141,接着再切断成模块化器件141的形状的结构。这时,还可以不在每个模块化器件中设置定位孔、突起及定位壁等。另外,为了进一步提高模块化器件与主板连接的可靠性,电路基板3的热膨胀系数最好与接合电路基板5大致相同。如果两者的热膨胀系数大致相同,就能抑制模块化器件与主板经过回流连接时产生的弯曲。就是说,能减少产生的弯曲应力,杜绝布线图案2的断线及短路。这样,能实现可靠性很高的安装。此外,虽然只对凹部4进行了讲述,但也可以使用贯贯穿通路孔。这时,如果安装元件1的连接部与外气接触后,耐环境条件性就要下降。因此,在接合安装元件1后,用环氧树脂等塞住***安装元件1的孔。这样,就能不使连接部位与外气接触,确保其耐环境条件性。另外,在以上的讲述中,只讲述了对一个安装元件1,设置对应的凹部4的结构。但还可以将多个安装元件1邻近配置,设置一个凹部4,将这些安装元件1全部嵌入。
(第2实施方式)
该第2实施方式,是内置本发明的安装元件的模块化器件的其它示例。
正如图15A和图15B所示,在电路基板3A和电路基板3B的每一个表面上,搭载着安装元件1。而且,电路基板3A和电路基板3B成为隔着接合电路基板5的结构。这样,在接合电路基板5上,形成与在电路基板3A上安装的安装元件1对应的凹部4A,和与在电路基板3B上安装的安装元件1对应的凹部4B。
在本结构中,安装元件1要配置成搭载在电路基板3A和3B的每一块上的安装元件1都不相互重叠。这样,就能实现将安装元件1在同一个面上铺满的结构。在现有技术中,为了在安装面积相同的情况下增加电路规模,实现小型·薄形化,就得将布线图案2细微化。这时,将安装元件1铺满电路基板3的表层后,只能通过使布线图案迂回曲折的方法,实现小型化。因此,就得增加通路孔6的数量和电路基板3的叠层数量。其结果是:通路孔6的数量增加后,导致电路基板3的强度下降;叠层数量增加后,则造成电路基板3的厚度增加。就是说,存在无法实现小型·薄性化的问题。采用本发明后,以接合电路基板5为核心,通过将电路基板3A和3B上下配置,从而可以用现有的布线尺寸,提高安装元件1的密度。进而可以使作为模块化器件的厚度变薄,所以可以袖珍化。此外,在本第2实施方式中,在电路基板3A和3B与接合电路基板5的各接合面的相对的各个面上,没有安装元件。但也可以安装元件。
(第3实施方式)
下面,使用图16A和图16B,讲述第3实施方式。
内置第3实施方式的安装元件的模块化器件,是将模拟电路和数字电路混合在一起形成的示例。在电路基板3的上面,搭载安装元件1A,构成模拟电路。而在电路基板3的下面,搭载安装元件1B,构成数字电路。在该电路基板3的内层部,构成屏蔽层13,形成接地电极14。在接合电路基板5A上,形成与搭载在电路基板3的上面的安装元件1A对应的凹部4A。再在接合电路基板5B上,形成与搭载在电路基板3的下面的安装元件1B对应的凹部4B。在该凹部4B的表面,形成屏蔽层13。而且在接合电路基板5B上,还形成与主板电连接的连接端子8C和8D。特别是连接端子8D,与主板侧的GND电极接合。而且,连接端子8D还通过通路孔6B,与电路基板3上形成的接地电极14连接。
叠层方法,与第1实施方式一样。如本结构所示,在电路基板3的上下面构成模拟电路和数字电路时,数字信号,将作为噪声被重叠在模拟信号上,引起误动作。因此,在数字电路中,需要采取屏蔽措施,不要让数字信号作为噪声跑到外面去。在模拟电路中,为了不使模拟信号受到噪声的影响,也要进行屏蔽,确保进行本来处理的信号的可靠性,这是很重要的。
可是,在有限的面积内,采用将模拟电路和数字电路混在一起的结构时,需要用金属板等形成的屏蔽罩屏蔽每个电路。其结果,模块化器件的形状就要变大。而且,在电路基板3的上下面构成一个个电路时,还需要在上下面形成屏蔽罩。这时,还必须将与主板连接用的端子,设置在没有屏蔽罩的部位。结果就使模块化器件的结构复杂。
为了解决这一问题,在电路基板3的内层,形成屏蔽层13;在接合电路基板5A和5B的凹部4A和4B的内壁,形成屏蔽层13。这样,就能分别屏蔽模拟电路和数字电路。其结果,就能不增大模块化器件的形状,还能将与主基板连接的端子,设置在接合电路基板5B的下面。进而还可以使电路基板3构成的、作为各电路的基准GND而形成的屏蔽层13,与主板侧的GND电位,成为相同的电位。这样,就可以使电路基板3构成的电路不产生寄生电容,确保电气信号的可靠性。其结果,可以提供即使在模块化器件内混合模拟电路和数字电路,也不会使电气特性变坏的小型模块化器件。
而且,作为构成电路基板3的材料,可以使用将陶瓷基板和复合树脂基板叠层·一体成型的异种叠层基板。例如:使用将陶瓷和铁电体作为无机充填物的构成的复合树脂基板,可以消除安装元件1及电路图案2产生的噪声。就是说,能将电路基板3内的电路彼此电分离,所以可以作为具有屏蔽结构的电路基板3使用。
另外,异种叠层基板的其它示例,是将被复合树脂基板使用的无机充填物是介电常数高的材料、介电常数低的材料、铁电体材料中的某一个的复合树脂基板彼此叠层而成的基板。使用这种具有不同的介电常数和导磁率的叠层体后,可以在叠层体的内部形成现有技术中搭载在电路基板3上的芯片电容器、电阻及线圈等。其结果,能使模块化器件进一步小型化。在本第3实施方式中,讲述了在电路基板3中形成异种叠层结构的情况,但它也能应用于接合电路基板5。
(第4实施方式)
下面使用图17A和图17B,讲述第4实施方式的模块化器件。在电路基板3的下面,搭载着安装元件1A和1B。在接合电路基板5上,形成与该安装元件1A和1B对应的凹部4A和4B。
特别是在DC/DC变换器用的模块化电路中,作为安装元件1B,使用开关用的电源IC。由于这时产生的热量较大,所以如果不能及时散热,就会达到超过电源IC接合部的耐热温度。其结果将使电源IC受损,不能正常工作。作为对策,在接合电路基板5的凹部4B的底面,形成通路孔6C。而且将铜、铝等热容量大的金属体,作为散热部件15,埋入接合电路基板5的一部分,使之与通路孔6C相接。这样,局部产生高热的安装元件1B的热量,就通过散热部件15,由接合电路基板5上形成的通路孔6C,高效率地热传导给外部连接端子8A。其结果,就能及时向外部散热。进—步,在第1实施方式中,在电路基板3上设置具有LGA结构的端子8A和具有端面电极的端子8B。在第4实施方式中,在接合电路基板5上构成它们。
在现有技术中,进行图案设计之际,需要经常考虑发热的电源IC等的散热问题。因此配置的场所受到限制,难以小型化。
采用本发明后,可以在任意的位置,及时将电路结构中局部产生高热的安装元件1B的热量散热。其结果,还能提高设计自由度,易于进行小型化。图17B,示出在接合电路基板5具有埋入散热部件15的结构的、散热性高的模块化器件。进而还能如图18A和图18B所示,在电路基板3中形成具有埋入散热部件15的结构的、散热性高的模块化器件。另外,作为电路基板3,使用固化的树脂基板、以导热性高的氧化铝为主要成分的陶瓷基板、金属基板、已固化的复合树脂基板等。其结果,可以更有效地将发热量大的安装元件1B产生的热量散发掉,100%地发挥电源IC所具有的特性。
(第5实施方式)
下面,利用图19A和图19B,讲述该第5实施方式的模块化器件。在电路基板3A的上面及下面,搭载安装元件1A,该电路基板3A,构成数字电路。在接合电路基板5A上,形成凹部4A。该凹部4A与搭载在电路基板3A的上面的安装元件1A对应。在该接合电路基板5A的上面,形成屏蔽层13。在接合电路基板5B中,形成凹部4A。该凹部4A,与搭载在电路基板3A的下面的安装元件1A对应。
在该凹部4A的表面,形成屏蔽层13。
而且,在接合电路基板5B中,形成与主板进行电连接的连接端子8C和8D。特别是连接端子8D,与主板侧的GND电极连接。
接着,在电路基板3B的上面,搭载邻接的多个安装元件1B,在其下面也搭载安装元件1B。而且该电路基板3B,构成模拟电路。在接合电路基板5D上,形成凹部4B。该凹部4B,与搭载在电路基板3B的上面的邻接的多个安装元件1B对应。
在接合电路基板5C中,形成凹部4B。该凹部4B,与搭载在电路基板3B的下面的安装元件1B对应。
在该凹部4B的表面,形成屏蔽层13。层叠方法和第1实施方式相同。另外,在第1个模块化器件内构成种类不同的电路的形态,与第3实施方式所示的一样。
在电路规模更大时,如本结构所示,使用多个接合电路基板和电路基板,进行层叠。
其结果,可以确保电路结构的最佳化和模块化器件的电特性。在本第5实施方式中,示出将2个用接合电路基板夹持电路基板而成的结构组合起来的情况,可是,并不限于这种结构,接合电路基板和电路基板,可以采用种种组合,构成模块化器件。
本发明提供能够实现通过确保尺寸精度来提高可靠性、减少安装安装元件时的冲击对基板造成的损坏、减小由热膨胀率的差异引起的叠层基板的弯曲等的可靠性高的、内置安装元件的小型模块化器件。这些效果,是将树脂基板或复合树脂基板彼此层叠、将该叠层物统一热固化后形成的结构所无法获得的。
本发明能提供精度优良、而且高密度地内置多个安装元件的、层间连接的可靠性高的小型模块化器件。
Claims (126)
1、一种模块化器件,其特征在于,包括:
电路基板,其具有至少两层的电路图案和将所述两层的电路图案连接的通路孔;
至少一个安装元件,安装在所述电路基板的至少单面上;以及
接合电路基板,具有凹部或者孔,按照将所述安装元件压入到所述凹部或者孔中的方式层叠在所述电路基板上;
其中,所述接合电路基板具有至少一层电路图案和填充了导电性糊料的通路孔,所述安装元件与所述电路基板以及所述接合电路基板之间没有间隙。
2、如权利要求1所述模块化器件,其特征在于:所述电路基板在其上面和下面分别具有至少一个安装元件,在所述电路基板的上面和下面分别层叠不同的接合电路基板。
3、如权利要求1或2所述模块化器件,其特征在于:所述安装元件,具有散热部件。
4、如权利要求1或2所述模块化器件,其特征在于:所述安装元件,至少一面具有连接端子。
5、如权利要求1或2所述模块化器件,其特征在于:所述安装元件,相对的2个面具有连接端子。
6、如权利要求1或2所述模块化器件,其特征在于:所述安装元件,除一面的之外其它的面,形成屏蔽面。
7、如权利要求1或2所述模块化器件,其特征在于:所述电路基板,平均表面粗糙度在10μm以上。
8、如权利要求1或2所述模块化器件,其特征在于:所述电路基板,具有外部连接端子。
9、如权利要求8所述模块化器件,其特征在于:所述外部连接端子,具有LGA和端面电极中的某一个。
10、如权利要求1或2所述模块化器件,其特征在于:所述电路基板,由具有能够抑制在层叠一体化工序中,所述接合电路基板的热收缩功能的材料构成。
11、如权利要求10所述模块化器件,其特征在于:所述电路基板,由已固化的树脂基板、陶瓷基板、金属基板、已固化的复合树脂基板中至少一个构成。
12、如权利要求1或2所述模块化器件,其特征在于:所述电路基板,具有散热功能。
13、如权利要求1或2所述模块化器件,其特征在于:所述电路基板,至少具有层间屏蔽功能和局部屏蔽功能中的某一个。
14、如权利要求1或2所述模块化器件,其特征在于:所述电路基板,具有至少包含电抗器、电容器、电阻器、滤波器、IC、匹配电路中的一个的电路。
15、如权利要求1或2所述模块化器件,其特征在于:所述电路基板,具有层间耦合和层间连接的某一个的多层布线结构。
16、如权利要求1或2所述模块化器件,其特征在于:所述电路基板,具有与所述接合电路基板连接的连接端子。
17、如权利要求16所述模块化器件,其特征在于:所述电路基板,在所述连接端子的一部分上具有钎焊料流出防止壁。
18、如权利要求1或2所述模块化器件,其特征在于:所述电路基板,具有与所述接合电路基板同等或同等以上的面积。
19、如权利要求1或2所述模块化器件,其特征在于:所述电路基板,用异种层叠体构成。
20、如权利要求1或2所述模块化器件,其特征在于:所述电路基板,具有导热性。
21、如权利要求20所述模块化器件,其特征在于:所述电路基板,具有嵌入散热部件的结构。
22、如权利要求1或2所述模块化器件,其特征在于:所述电路基板,具有和所述接合电路基板相同的热膨胀系数。
23、如权利要求1或2所述模块化器件,其特征在于:所述电路基板,具有消除电噪声的功能。
24、如权利要求1或2所述模块化器件,其特征在于:所述电路基板,内置接地电极。
25、如权利要求1或2所述模块化器件,其特征在于:所述电路基板,具有定位壁。
26、如权利要求1或2所述模块化器件,其特征在于:在所述电路基板和所述接合电路基板的接合面一侧的至少某一方,形成定位用的突起和孔中的某一个。
27、如权利要求1或2所述模块化器件,其特征在于:所述电路基板,具有电特性的常数调整功能。
28、如权利要求1或2所述模块化器件,其特征在于:所述接合电路基板,具有外部连接端子。
29、如权利要求28所述模块化器件,其特征在于:所述外部连接端子,具有LGA和端面电极中的某一个。
30、如权利要求1或2所述模块化器件,其特征在于:在所述接合电路基板上形成的凹部和孔中的某一个,具有能吸收所述安装元件的1%以下的尺寸公差的大小。
31、如权利要求1或2所述模块化器件,其特征在于:在所述接合电路基板上形成的凹部和孔中的某一个,***所述安装元件一侧的开口部分的尺寸,大于其深处部分的尺寸。
32、如权利要求1或2所述模块化器件,其特征在于:在所述接合电路基板上形成的凹部的底面,形成端子。
33、如权利要求1或2所述模块化器件,其特征在于:在所述接合电路基板上形成的凹部和孔中的某一个的侧面,形成端子。
34、如权利要求1或2所述模块化器件,其特征在于:在所述接合电路基板上形成的凹部和孔中的某一个,形成屏蔽层。
35、如权利要求1或2所述模块化器件,其特征在于:在所述接合电路基板上形成的凹部和孔中的某一个,形成导电层。
36、如权利要求1或2所述模块化器件,其特征在于:在所述接合电路基板上形成的凹部和孔中的某一个,形成弹性体层。
37、如权利要求1或2所述模块化器件,其特征在于:在所述接合电路基板上形成的凹部和孔中的某一个,形成热传导层。
38、如权利要求1或2所述模块化器件,其特征在于:所述接合电路基板,由预成型材料构成。
39、如权利要求1或2所述模块化器件,其特征在于:所述接合电路基板,表面具有粘接层。
40、如权利要求39所述模块化器件,其特征在于:所述粘接层,是涂敷双液固化型和厌气型中的某一种粘接剂后形成的。
41、如权利要求39所述模块化器件,其特征在于:所述粘接层,在所述电路基板与所述接合电路基板的电连接部所对应的部分,不布图。
42、如权利要求41所述模块化器件,其特征在于:在所述粘接层的不布图的部分,埋入导电性糊料。
43、如权利要求39所述模块化器件,其特征在于:所述粘接层,由粘接片构成。
44、如权利要求43所述模块化器件,其特征在于:所述粘接层,在所述电路基板与所述接合电路基板的电连接部所对应的部分,具有孔。
45、如权利要求44所述模块化器件,其特征在于:在所述粘接层的孔的部分,埋入导电性糊料。
46、如权利要求43所述模块化器件,其特征在于:所述粘接片,由具有导电性粒子的结构构成。
47、如权利要求1或2所述模块化器件,其特征在于:所述接合电路基板,由热固化树脂和热可塑性树脂中的某一个构成。
48、如权利要求39所述模块化器件,其特征在于:所述接合电路基板,由热固化树脂和热可塑性树脂中的某一个构成。
49、如权利要求39所述模块化器件,其特征在于:所述接合电路基板,由使所述粘接层固化时不发生尺寸变化的材料构成。
50、如权利要求49所述模块化器件,其特征在于:所述接合电路基板,由已固化的树脂基板、陶瓷基板、金属基板、已固化的复合树脂基板中至少一个构成。
51、如权利要求1或2所述模块化器件,其特征在于:所述接合电路基板,具有散热功能。
52、如权利要求1或2所述模块化器件,其特征在于:所述接合电路基板,至少具有层间屏蔽功能和局部屏蔽功能中的某一个。
53、如权利要求1或2所述模块化器件,其特征在于:所述接合电路基板,具有至少包含电抗器、电容器、电阻器、滤波器、IC、匹配电路中的某一个的电路。
54、如权利要求1或2所述模块化器件,其特征在于:所述接合电路基板,具有层间耦合和层间连接中的某一个的多层布线结构。
55、如权利要求1或2所述模块化器件,其特征在于:所述接合电路基板,具有与所述电路基板连接的连接端子。
56、如权利要求55所述模块化器件,其特征在于:所述接合电路基板,在所述连接端子的一部分上具有钎焊料流出防止壁。
57、如权利要求1或2所述模块化器件,其特征在于:所述接合电路基板,是异种层叠体。
58、如权利要求1或2所述模块化器件,其特征在于:所述接合电路基板,具有导热性。
59、如权利要求58所述模块化器件,其特征在于:所述接合电路基板,具有嵌入散热部件的结构。
60、如权利要求1或2所述模块化器件,其特征在于:所述接合电路基板,具有消除电噪声的功能。
61、如权利要求1或2所述模块化器件,其特征在于:所述接合电路基板,内置接地电极。
62、如权利要求1或2所述模块化器件,其特征在于:所述电路基板和所述接合电路基板中的某一个的连接端子,采用向连接侧突出的结构。
63、一种模块化器件,其特征在于:是将权利要求1或2所述模块化器件,至少组合两个以上,层叠而成的模块化器件;其接合面至少是所述电路基板与所述接合电路基板的组合和所述接合电路基板彼此中的某一个。
64、如权利要求63所述模块化器件,其特征在于:位于所述电路基板间的所述接合电路基板,两面都具有嵌入安装在对应的所述电路基板上的所述安装元件的凹部和孔中的某一个。
65、一种模块化器件,其特征在于,包括:
第一电路基板,其具有至少两层的电路图案和将所述两层的电路图案连接的通路孔;
至少一个第一安装元件,安装在所述第一电路基板上;
接合电路基板,两面具有凹部或者孔,层叠在所述第一电路基板上;
第二电路基板,层叠在所述接合电路基板上,安装有至少一个第二安装元件;
所述第二安装元件面向所述接合电路基板安装,所述第一和第二安装元件与所述第一电路基板、所述第二电路基板以及所述接合电路基板之间没有间隙;
将所述第一和第二安装元件压入到所述凹部或者孔中。
66、如权利要求65所述模块化器件,其特征在于:所述第一和第二安装元件,具有散热部件。
67、如权利要求65所述模块化器件,其特征在于:所述第一和第二安装元件,至少一面具有连接端子。
68、如权利要求65所述模块化器件,其特征在于:所述第一和第二安装元件,相对的2个面具有连接端子。
69、如权利要求65所述模块化器件,其特征在于:所述第一和第二安装元件,除一面的之外其它的面,形成屏蔽面。
70、如权利要求65所述模块化器件,其特征在于:所述第一和第二电路基板,平均表面粗糙度在10μm以上。
71、如权利要求65所述模块化器件,其特征在于:所述第一和第二电路基板,具有外部连接端子。
72、如权利要求71所述模块化器件,其特征在于:所述外部连接端子,具有LGA和端面电极中的某一个。
73、如权利要求65所述模块化器件,其特征在于:所述第一和第二电路基板,由具有能够抑制在层叠一体化工序中,所述接合电路基板的热收缩功能的材料构成。
74、如权利要求73所述模块化器件,其特征在于:所述第一和第二电路基板,由已固化的树脂基板、陶瓷基板、金属基板、已固化的复合树脂基板中至少一个构成。
75、如权利要求65所述模块化器件,其特征在于:所述第一和第二电路基板,具有散热功能。
76、如权利要求65所述模块化器件,其特征在于:所述第一和第二电路基板,至少具有层间屏蔽功能和局部屏蔽功能中的某一个。
77、如权利要求65所述模块化器件,其特征在于:所述第一和第二电路基板,具有至少包含电抗器、电容器、电阻器、滤波器、IC、匹配电路中的一个的电路。
78、如权利要求65所述模块化器件,其特征在于:所述第一和第二电路基板,具有层间耦合和层间连接的某一个的多层布线结构。
79、如权利要求65所述模块化器件,其特征在于:所述第一和第二电路基板,具有与所述接合电路基板连接的连接端子。
80、如权利要求79所述模块化器件,其特征在于:所述第一和第二电路基板,在所述连接端子的一部分上具有钎焊料流出防止壁。
81、如权利要求65所述模块化器件,其特征在于:所述第一和第二电路基板,具有与所述接合电路基板同等或同等以上的面积。
82、如权利要求65所述模块化器件,其特征在于:所述第一和第二电路基板,用异种层叠体构成。
83、如权利要求65所述模块化器件,其特征在于:所述第一和第二电路基板,具有导热性。
84、如权利要求83所述模块化器件,其特征在于:所述第一和第二电路基板,具有嵌入散热部件的结构。
85、如权利要求65所述模块化器件,其特征在于:所述第一和第二电路基板,具有和所述接合电路基板相同的热膨胀系数。
86、如权利要求65所述模块化器件,其特征在于:所述第一和第二电路基板,具有消除电噪声的功能。
87、如权利要求65所述模块化器件,其特征在于:所述第一和第二电路基板,内置接地电极。
88、如权利要求65所述模块化器件,其特征在于:所述第一和第二电路基板,具有定位壁。
89、如权利要求65所述模块化器件,其特征在于:在所述第一和第二电路基板和所述接合电路基板的接合面一侧的至少某一方,形成定位用的突起和孔中的某一个。
90、如权利要求65所述模块化器件,其特征在于:所述第一和第二电路基板,具有电特性的常数调整功能。
91、如权利要求65所述模块化器件,其特征在于:所述接合电路基板,具有外部连接端子。
92、如权利要求91所述模块化器件,其特征在于:所述外部连接端子,具有LGA和端面电极中的某一个。
93、如权利要求65所述模块化器件,其特征在于:在所述接合电路基板上形成的凹部和孔中的某一个,具有能吸收所述安装元件的1%以下的尺寸公差的大小。
94、如权利要求65所述模块化器件,其特征在于:在所述接合电路基板上形成的凹部和孔中的某一个,***所述安装元件一侧的开口部分的尺寸,大于其深处部分的尺寸。
95、如权利要求65所述模块化器件,其特征在于:在所述接合电路基板上形成的凹部的底面,形成端子。
96、如权利要求65所述模块化器件,其特征在于:在所述接合电路基板上形成的凹部和孔中的某一个的侧面,形成端子。
97、如权利要求65所述模块化器件,其特征在于:在所述接合电路基板上形成的凹部和孔中的某一个,形成屏蔽层。
98、如权利要求65所述模块化器件,其特征在于:在所述接合电路基板上形成的凹部和孔中的某一个,形成导电层。
99、如权利要求65所述模块化器件,其特征在于:在所述接合电路基板上形成的凹部和孔中的某一个,形成弹性体层。
100、如权利要求65所述模块化器件,其特征在于:在所述接合电路基板上形成的凹部和孔中的某一个,形成热传导层。
101、如权利要求65所述模块化器件,其特征在于:所述接合电路基板,由预成型材料构成。
102、如权利要求65所述模块化器件,其特征在于:所述接合电路基板,表面具有粘接层。
103、如权利要求102所述模块化器件,其特征在于:所述粘接层,是涂敷双液固化型和厌气型中的某一种粘接剂后形成的。
104、如权利要求102所述模块化器件,其特征在于:所述粘接层,在所述第一和第二电路基板与所述接合电路基板的电连接部所对应的部分,不布图。
105、如权利要求104所述模块化器件,其特征在于:在所述粘接层的不布图的部分,埋入导电性糊料。
106、如权利要求102所述模块化器件,其特征在于:所述粘接层,由粘接片构成。
107、如权利要求106所述模块化器件,其特征在于:所述粘接层,在所述第一和第二电路基板与所述接合电路基板的电连接部所对应的部分,具有孔。
108、如权利要求107所述模块化器件,其特征在于:在所述粘接层的孔的部分,埋入导电性糊料。
109、如权利要求106所述模块化器件,其特征在于:所述粘接片,由具有导电性粒子的结构构成。
110、如权利要求65所述模块化器件,其特征在于:所述接合电路基板,由热固化树脂和热可塑性树脂中的某一个构成。
111、如权利要求102所述模块化器件,其特征在于:所述接合电路基板,由热固化树脂和热可塑性树脂中的某一个构成。
112、如权利要求102所述模块化器件,其特征在于:所述接合电路基板,由使所述粘接层固化时不发生尺寸变化的材料构成。
113、如权利要求112所述模块化器件,其特征在于:所述接合电路基板,由已固化的树脂基板、陶瓷基板、金属基板、已固化的复合树脂基板中至少一个构成。
114、如权利要求65所述模块化器件,其特征在于:所述接合电路基板,具有散热功能。
115、如权利要求65所述模块化器件,其特征在于:所述接合电路基板,至少具有层间屏蔽功能和局部屏蔽功能中的某一个。
116、如权利要求65所述模块化器件,其特征在于:所述接合电路基板,具有至少包含电抗器、电容器、电阻器、滤波器、IC、匹配电路中的某一个的电路。
117、如权利要求65所述模块化器件,其特征在于:所述接合电路基板,具有层间耦合和层间连接中的某一个的多层布线结构。
118、如权利要求65所述模块化器件,其特征在于:所述接合电路基板,具有与所述电路基板连接的连接端子。
119、如权利要求118所述模块化器件,其特征在于:所述接合电路基板,在所述连接端子的一部分上具有钎焊料流出防止壁。
120、如权利要求65所述模块化器件,其特征在于:所述接合电路基板,是异种层叠体。
121、如权利要求65所述模块化器件,其特征在于:所述接合电路基板,具有导热性。
122、如权利要求121所述模块化器件,其特征在于:所述接合电路基板,具有嵌入散热部件的结构。
123、如权利要求65所述模块化器件,其特征在于:所述接合电路基板,具有消除电噪声的功能。
124、如权利要求65所述模块化器件,其特征在于:所述接合电路基板,内置接地电极。
125、如权利要求65所述模块化器件,其特征在于:所述第一和第二电路基板和所述接合电路基板中的某一个的连接端子,采用向连接侧突出的结构。
126、一种模块化器件,其特征在于:是将权利要求65所述模块化器件,至少组合两个以上,层叠而成的模块化器件;其接合面至少是所述第一和第二电路基板与所述接合电路基板的组合和所述接合电路基板彼此中的某一个。
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Families Citing this family (62)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003243797A (ja) * | 2002-02-19 | 2003-08-29 | Matsushita Electric Ind Co Ltd | モジュール部品 |
JP2005108625A (ja) | 2003-09-30 | 2005-04-21 | Jst Mfg Co Ltd | 多層異方導電シート |
JP4287733B2 (ja) * | 2003-11-04 | 2009-07-01 | 日本シイエムケイ株式会社 | 電子部品内蔵多層プリント配線板 |
JP2005158770A (ja) * | 2003-11-20 | 2005-06-16 | Matsushita Electric Ind Co Ltd | 積層基板とその製造方法及び前記積層基板を用いたモジュールの製造方法とその製造装置 |
CN1774965A (zh) * | 2004-03-30 | 2006-05-17 | 松下电器产业株式会社 | 模块元件及其制造方法 |
JP4218576B2 (ja) * | 2004-04-19 | 2009-02-04 | パナソニック株式会社 | 積層基板の製造方法 |
JP4251144B2 (ja) * | 2004-04-19 | 2009-04-08 | パナソニック株式会社 | 積層基板の製造方法 |
JP4552524B2 (ja) * | 2004-06-10 | 2010-09-29 | パナソニック株式会社 | 複合型電子部品 |
JP4792749B2 (ja) * | 2005-01-14 | 2011-10-12 | 大日本印刷株式会社 | 電子部品内蔵プリント配線板の製造方法 |
WO2006098364A1 (ja) | 2005-03-17 | 2006-09-21 | Matsushita Electric Industrial Co., Ltd. | モジュール基板 |
WO2006112383A1 (ja) * | 2005-04-14 | 2006-10-26 | Matsushita Electric Industrial Co., Ltd. | 電子回路装置およびその製造方法 |
JP4215024B2 (ja) * | 2005-04-22 | 2009-01-28 | パナソニック株式会社 | 積層基板の製造方法 |
JP4417294B2 (ja) * | 2005-06-16 | 2010-02-17 | パナソニック株式会社 | プローブカード用部品内蔵基板とその製造方法 |
DE102005032489B3 (de) * | 2005-07-04 | 2006-11-16 | Schweizer Electronic Ag | Leiterplatten-Mehrschichtaufbau mit integriertem elektrischem Bauteil und Herstellungsverfahren |
JP4175351B2 (ja) * | 2005-08-26 | 2008-11-05 | 松下電工株式会社 | 凹凸多層回路板モジュール及びその製造方法 |
JP2007158157A (ja) * | 2005-12-07 | 2007-06-21 | Alps Electric Co Ltd | 電子回路装置 |
US20100153836A1 (en) * | 2008-12-16 | 2010-06-17 | Rich Media Club, Llc | Content rendering control system and method |
JP4849926B2 (ja) * | 2006-03-27 | 2012-01-11 | 富士通株式会社 | 半導体装置及び半導体装置の製造方法 |
JP5034289B2 (ja) * | 2006-03-28 | 2012-09-26 | 大日本印刷株式会社 | 多層プリント配線板及びその製造方法 |
JP4992310B2 (ja) | 2006-06-16 | 2012-08-08 | 富士通株式会社 | 積層基板の製造方法 |
JP5082321B2 (ja) * | 2006-07-28 | 2012-11-28 | 大日本印刷株式会社 | 多層プリント配線板及びその製造方法 |
SG139594A1 (en) * | 2006-08-04 | 2008-02-29 | Micron Technology Inc | Microelectronic devices and methods for manufacturing microelectronic devices |
KR100763345B1 (ko) | 2006-08-30 | 2007-10-04 | 삼성전기주식회사 | 전자소자 내장형 인쇄회로기판의 제조방법 |
JP4939916B2 (ja) * | 2006-12-21 | 2012-05-30 | 株式会社フジクラ | 多層プリント配線板およびその製造方法 |
JP4970994B2 (ja) * | 2007-03-19 | 2012-07-11 | ルネサスエレクトロニクス株式会社 | 半導体パッケージ |
EP2136610A4 (en) * | 2008-01-25 | 2011-07-13 | Ibiden Co Ltd | MULTILAYER CONDUCTOR PLATE AND METHOD FOR THE PRODUCTION THEREOF |
TWI434640B (zh) | 2008-01-30 | 2014-04-11 | Murata Manufacturing Co | Electronic parts and their construction methods |
JP5172410B2 (ja) * | 2008-03-24 | 2013-03-27 | 日本特殊陶業株式会社 | 部品内蔵配線基板の製造方法 |
DE102008040906A1 (de) * | 2008-07-31 | 2010-02-04 | Robert Bosch Gmbh | Leiterplatine mit elektronischem Bauelement |
FR2937796A1 (fr) * | 2008-10-29 | 2010-04-30 | St Microelectronics Grenoble | Dispositif semi-conducteur a ecran de protection |
JP5589302B2 (ja) * | 2008-11-12 | 2014-09-17 | 富士通株式会社 | 部品内蔵基板及びその製造方法 |
JP5200870B2 (ja) * | 2008-11-12 | 2013-06-05 | 株式会社村田製作所 | 部品内蔵モジュールの製造方法 |
US7786839B2 (en) * | 2008-12-28 | 2010-08-31 | Pratt & Whitney Rocketdyne, Inc. | Passive electrical components with inorganic dielectric coating layer |
EP2242066A1 (en) * | 2009-04-17 | 2010-10-20 | Nxp B.V. | Inductive components for dc/dc converters and methods of manufacture thereof |
US9070679B2 (en) * | 2009-11-24 | 2015-06-30 | Marvell World Trade Ltd. | Semiconductor package with a semiconductor die embedded within substrates |
US9225379B2 (en) | 2009-12-18 | 2015-12-29 | Intel Corporation | Apparatus and method for embedding components in small-form-factor, system-on-packages |
US8217272B2 (en) * | 2009-12-18 | 2012-07-10 | Intel Corporation | Apparatus and method for embedding components in small-form-factor, system-on-packages |
JP5293692B2 (ja) * | 2010-06-29 | 2013-09-18 | エルナー株式会社 | フレックスリジッド配線基板及びその製造方法 |
CN103053021A (zh) * | 2010-08-18 | 2013-04-17 | 株式会社村田制作所 | 电子元器件及其制造方法 |
US9173299B2 (en) | 2010-09-30 | 2015-10-27 | KYOCERA Circuit Solutions, Inc. | Collective printed circuit board |
JP5667023B2 (ja) * | 2010-09-30 | 2015-02-12 | 京セラサーキットソリューションズ株式会社 | 集合配線基板および電子装置の実装方法 |
US8669777B2 (en) * | 2010-10-27 | 2014-03-11 | Seagate Technology Llc | Assessing connection joint coverage between a device and a printed circuit board |
TWI441305B (zh) * | 2010-12-21 | 2014-06-11 | Ind Tech Res Inst | 半導體裝置 |
JP2013149792A (ja) * | 2012-01-19 | 2013-08-01 | Denso Corp | 電子部品の製造方法 |
ITMI20121134A1 (it) * | 2012-06-27 | 2013-12-28 | St Microelectronics Srl | Dispositivo elettronico flip chip e relativo metodo di produzione |
US8872349B2 (en) * | 2012-09-11 | 2014-10-28 | Intel Corporation | Bridge interconnect with air gap in package assembly |
KR20140079204A (ko) * | 2012-12-18 | 2014-06-26 | 에스케이하이닉스 주식회사 | 반도체 패키지용 기판, 이를 이용한 반도체 패키지 및 그 제조 방법 |
JP2014154813A (ja) * | 2013-02-13 | 2014-08-25 | Ibiden Co Ltd | プリント配線板 |
JP2014165396A (ja) * | 2013-02-26 | 2014-09-08 | Sony Corp | 固体撮像装置および電子機器 |
KR20150119350A (ko) * | 2013-04-10 | 2015-10-23 | 미쓰비시덴키 가부시키가이샤 | 반도체 장치, 반도체 장치의 제조 방법 |
JP6269661B2 (ja) * | 2013-05-08 | 2018-01-31 | 株式会社村田製作所 | 多層配線基板 |
JP6103054B2 (ja) | 2013-06-18 | 2017-03-29 | 株式会社村田製作所 | 樹脂多層基板の製造方法 |
JP5583828B1 (ja) * | 2013-08-05 | 2014-09-03 | 株式会社フジクラ | 電子部品内蔵多層配線基板及びその製造方法 |
US9443758B2 (en) | 2013-12-11 | 2016-09-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Connecting techniques for stacked CMOS devices |
EP2940729A1 (en) * | 2014-04-28 | 2015-11-04 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Electronic assembly comprising a carrier structure made from a printed circuit board |
USD760230S1 (en) * | 2014-09-16 | 2016-06-28 | Daishinku Corporation | Piezoelectric vibration device |
DE102015113421B4 (de) * | 2015-08-14 | 2019-02-21 | Danfoss Silicon Power Gmbh | Verfahren zum Herstellen von Halbleiterchips |
JP6891582B2 (ja) * | 2017-03-27 | 2021-06-18 | 横河電機株式会社 | 防爆部品実装基板 |
KR102259995B1 (ko) * | 2017-10-30 | 2021-06-02 | 니뽄 도쿠슈 도교 가부시키가이샤 | 전극 매설 부재 |
US11497112B2 (en) * | 2020-12-11 | 2022-11-08 | Toyota Motor Engineering & Manufacturing North America, Inc. | Driver board assemblies and methods of forming a driver board assembly |
KR102537710B1 (ko) * | 2021-05-28 | 2023-05-31 | (주)티에스이 | 일괄 접합 방식의 다층 회로기판 및 그 제조 방법 |
WO2023127202A1 (ja) * | 2021-12-27 | 2023-07-06 | 株式会社ダイワ工業 | 配線基板又は配線基板材料の製造方法 |
Family Cites Families (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2080693B3 (zh) * | 1970-02-23 | 1973-05-11 | Keramische K Veb | |
JPS4899657A (zh) * | 1972-03-30 | 1973-12-17 | ||
US5162540A (en) * | 1986-12-18 | 1992-11-10 | Lonza Ltd. | Process for the production of (+) biotin |
JPH0274099A (ja) * | 1988-09-09 | 1990-03-14 | Murata Mfg Co Ltd | 電子部品内蔵多層樹脂基板 |
JPH03190188A (ja) * | 1989-12-19 | 1991-08-20 | Nippon Chemicon Corp | 多層回路装置及びその製造方法 |
JPH06120670A (ja) * | 1991-03-12 | 1994-04-28 | Japan Radio Co Ltd | 多層配線基板 |
EP0544329A3 (en) * | 1991-11-28 | 1993-09-01 | Kabushiki Kaisha Toshiba | Semiconductor package |
JPH0579995U (ja) * | 1992-04-03 | 1993-10-29 | 日本無線株式会社 | 高周波シールド構造を有する多層配線基板 |
JP3288840B2 (ja) * | 1994-02-28 | 2002-06-04 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
WO1998027795A1 (fr) * | 1996-12-17 | 1998-06-25 | Hokuriku Electric Industry Co., Ltd. | Carte de circuit possedant un composant electrique et son procede de fabrication |
JP3051700B2 (ja) | 1997-07-28 | 2000-06-12 | 京セラ株式会社 | 素子内蔵多層配線基板の製造方法 |
JPH1174648A (ja) * | 1997-08-27 | 1999-03-16 | Kyocera Corp | 配線基板 |
JPH11214819A (ja) * | 1998-01-28 | 1999-08-06 | Sony Corp | 配線板及びその製造方法 |
JP2000183536A (ja) * | 1998-12-17 | 2000-06-30 | Sony Corp | 機能モジュール及びその製造方法 |
JP2000182018A (ja) | 1998-12-18 | 2000-06-30 | Dainippon Printing Co Ltd | 耐熱性icカードの製造方法 |
JP3207174B2 (ja) * | 1999-02-01 | 2001-09-10 | 京セラ株式会社 | 電気素子搭載配線基板およびその製造方法 |
JP3213292B2 (ja) * | 1999-07-12 | 2001-10-02 | ソニーケミカル株式会社 | 多層基板、及びモジュール |
JP3619395B2 (ja) * | 1999-07-30 | 2005-02-09 | 京セラ株式会社 | 半導体素子内蔵配線基板およびその製造方法 |
JP3681155B2 (ja) * | 1999-12-22 | 2005-08-10 | 新光電気工業株式会社 | 電子部品の実装構造、電子部品装置、電子部品の実装方法及び電子部品装置の製造方法 |
JP4032589B2 (ja) | 1999-12-28 | 2008-01-16 | 株式会社日立プラントテクノロジー | 防音壁 |
JP2001210954A (ja) * | 2000-01-24 | 2001-08-03 | Ibiden Co Ltd | 多層基板 |
JP4074040B2 (ja) * | 2000-03-14 | 2008-04-09 | イビデン株式会社 | 半導体モジュール |
JP2001267710A (ja) * | 2000-03-15 | 2001-09-28 | Sony Corp | 電子回路装置および多層プリント配線板 |
TW507484B (en) * | 2000-03-15 | 2002-10-21 | Matsushita Electric Ind Co Ltd | Method of manufacturing multi-layer ceramic circuit board and conductive paste used for the same |
JP3951091B2 (ja) * | 2000-08-04 | 2007-08-01 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JP3669255B2 (ja) * | 2000-09-19 | 2005-07-06 | 株式会社村田製作所 | セラミック多層基板の製造方法および未焼成セラミック積層体 |
JP2003124429A (ja) * | 2001-10-15 | 2003-04-25 | Matsushita Electric Ind Co Ltd | モジュール部品 |
JP2003243797A (ja) * | 2002-02-19 | 2003-08-29 | Matsushita Electric Ind Co Ltd | モジュール部品 |
JP2004165501A (ja) * | 2002-11-14 | 2004-06-10 | Alps Electric Co Ltd | 回路モジュール |
TWI251313B (en) * | 2003-09-26 | 2006-03-11 | Seiko Epson Corp | Intermediate chip module, semiconductor device, circuit board, and electronic device |
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- 2002-02-19 JP JP2002041066A patent/JP2003243797A/ja active Pending
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EP1478023A4 (en) | 2008-12-31 |
CN1592968A (zh) | 2005-03-09 |
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US7161371B2 (en) | 2007-01-09 |
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