TWI420635B - 低分佈剖面倒裝功率模組及製造方法 - Google Patents

低分佈剖面倒裝功率模組及製造方法 Download PDF

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TWI420635B
TWI420635B TW097106155A TW97106155A TWI420635B TW I420635 B TWI420635 B TW I420635B TW 097106155 A TW097106155 A TW 097106155A TW 97106155 A TW97106155 A TW 97106155A TW I420635 B TWI420635 B TW I420635B
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printed circuit
circuit
power module
low profile
circuit board
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TW200841445A (en
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Sun Ming
Gong Demei
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Alpha & Omega Semiconductor
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Description

低分佈剖面倒裝功率模組及製造方法
本發明總體涉及電子封裝領域。更具體地，本發明涉及功率半導體模組的封裝。
根據市場的要求，現今電子產品的總體發展趨勢是產品小型化，同時產品功能大幅增加。沒有例外，該發展趨勢同樣適用於功率電子產品領域。因此，甚至在功率電子產品領域中，也已經對產品小型化具有日益增加的需求，同時，也對功率電子產品中凸顯的散熱，電磁干擾/射頻干擾(EMI/RFI)遮罩方面有其他的要求。
本發明的目的在於提供一種低分佈剖面倒裝功率模組及製造方法，用於封裝具有倒裝功率金屬氧化物半導體場效應電晶體(MOSFET)器件的電子系統，具有低分佈剖面，增強的機械堅固性和遮罩EMI/RFI的特徵。
為達上述目的，本發明提供一種用於封裝包括功率MOSFET器件的電子系統的低分佈剖面的功率模組。該功率模組包括導電的正面覆蓋板和實體導電鍵合到正面覆蓋板的背面的多層印刷電路板。該多層印刷電路板具有多個經鍵合的印刷電路層以形成多層電互連結構。尤其是，所述印刷電路板的正面包括多個凹嵌口，每個凹嵌口在其底 面上具有許多印刷電路跡線。多個倒裝的功率MOSFET器件和其他電路元件位於該凹嵌口內，這些功率MOSFET和電路器件導電鍵合到凹嵌口底面上的印刷電路跡線上。由於各個電路元件設置在功率模組內部，因此該功率模組具有低分佈剖面，增強的機械堅固性和遮罩EMI/RFI的特徵。
另外，一些電路元件可以配備正面鍵合層，該正面鍵合層其後被導電鍵合到正面覆蓋板以實現與功率模組內部的雙面鍵合。進一步，以功率模組的取向作為參照，倒裝的功率MOSFET在其背面具有源極觸點和柵極觸點，在其正面具有漏極觸點。為了促使這些雙面鍵合的電路元件的散熱，進一步使所述正面覆蓋板具有熱傳導性而作為散熱片。由於該正面覆蓋板平整，因此外接的散熱器能容易地附接到該正面覆蓋板上以促進功率模組的散熱。
一種製造功率模組的方法，包括以下步驟：A)形成具有多個經鍵合的印刷電路層，正面凹嵌口，位於正面凹嵌口內的電路元件和鍵合到凹嵌口內的印刷電路跡線上的倒裝功率模組的多層印刷電路板；B)提供導電的正面覆蓋板；C)將多層印刷電路板的正面實體導電鍵合到所述正面覆蓋板；作為一種變化，在該步驟中，可以附加地使一些電路元件能正面鍵合併由此導電鍵合到所述正面覆蓋板。
所述形成多層印刷電路板的方法，進一步包括以下步驟：A1)形成多個經鍵合的印刷電路層； A2)通過從該多個經鍵合的印刷電路層的對應層數上去除對應數量的凹嵌口材料，從而沿該印刷電路層的正面產生多個凹嵌口；A3)將各個電路元件放置到凹嵌口內；A4)通過各個電路元件的背面元件鍵合區將該電路元件導電鍵合到所述凹嵌口。
另外一種形成多層印刷電路板的方法，進一步包括以下步驟：A1)根據多層印刷電路板的層次要求，提供多個印刷電路層；A2)對於每個印刷電路層，確定並預先切割出特定數量的每一個都有特定幾何形狀的視窗，因此在其後的層迭時該多個印刷電路層將形成預期的凹嵌口；A3)堆疊並層壓該多個印刷電路層，由此同時形成預期的凹嵌口；A4)如果有因多層印刷電路板的規定的必要，在各個經層迭的印刷電路層上形成諸如所印製的通孔和焊接掩模的其他電路形成特徵；A5)將各個電路元件放置到凹嵌口內；A6)通過各個電路元件的背面元件鍵合區將該電路元件導電鍵合到所述凹嵌口。
通過下文對本發明的敍述，本發明及其多個實施例的各個方面對於本技術領域的普通熟練人員將是顯而易見的。
下文將參考結合附第1圖-附第3A圖及第3B圖對本發明進行詳盡敍述。
上文以及下文結合本文包含的附圖的描述僅用於說明本發明的一個或多個當前的優選實施例，同時也敍述一些示例性的可選特徵和/或替代實施例。所作的描述和附圖用於對本發明進行說明的目的，因此同樣並非是對本發明的限制。如此，本技術領域的普通熟練人員將容易理解本發明的各種變化，修改和替代。這樣的變化，修改和替代也應該被理解為處在本發明的範圍之內。
第1圖是本發明的低分佈剖面功率模組10的橫截面示意圖。所提出的該低分佈剖面功率模組10用於封裝電子系統，為了說明的簡潔，該電子系統包括一個或多個功率MOSFET 64，一個或多個積體電路(IC)60和一個或多個無源元件62。當沒有特別說明時，功率MOSFET 64的有源電路是倒裝結構，以低分佈剖面功率模組10的取向作為參照，其源極觸點和柵極觸點設置在背面。這樣，功率MOSFET 64的源極觸點和柵極觸點通過鍵合區開口66與背面焊接塊24實現電連接。同樣，IC 60的封裝也是倒裝的類型。如圖所示，功率MOSFET漏極68還具有正面元件鍵合層27，以低分佈剖面功率模組10的取向作為參照，該正面元件鍵合層27位於該功率MOSFET 64的正面。
通常，低分佈剖面功率模組10包括導電的正面覆蓋板12和實體導電鍵合到該正面覆蓋板12的多層印刷電路板 14。該多層印刷電路板14具有多個層迭並鍵合的典型的印刷電路層(第一PCB(印刷電路板)層14a，第二PCB層14b，第三PCB層14c和第四PCB層14d)，以形成多層電互連結構。一些PCB層的相關的電路形成構造要素，諸如鍍覆通孔20(技術上也稱“通道孔”)和焊接掩模22也在圖中示出。然而，為了避免不必要的模糊細節，除了將要進行描述的印刷電路跡線26之外，一些其他的電路形成構造要素，諸如兩兩介於各個PCB層14a，14b，14c和14d之間的互連電路跡線在圖中沒有顯示。如本文的定義，“電路形成構造要素”是用於形成電子系統的元件間電連接的互連導電鍵合區，印刷電路跡線，平面，導電通孔，焊接掩膜，球形柵格陣列(BGA)和平面柵格陣列(LGA)的一組預先確定的三維圖形。尤其是，所述多層印刷電路板14的正面包括在其底面上具有印刷電路跡線26的凹嵌口25。因此，功率MOSFET 64，IC 60和無源元件62的各個電路元件也位於該凹嵌口25的底面上與印刷電路跡線26相應的位置上，並通過背面焊接塊24導電鍵合到由該低分佈剖面功率模組10實施的電子系統的其餘部分。由於功率MOSFET 64通常是垂直型器件，其器件電流從半導體襯底的一個主表面流至其相對的主表面。另外，同樣重要的是，需要指出，通過第一PCB層14a，第二PCB層14b，背面焊接塊24，功率MOSFET 64和正面元件鍵合層27之間的適當的厚度匹配，包圍在凹嵌口25和正面覆蓋板12之間的功率MOSFET 64的漏極68導電鍵合到正面覆蓋板12， 並進一步通過鍍覆通孔20連接到多層印刷電路板14的背面。然而，在用側向MOSFET代替垂直MOSFET的任何場合，該類型的雙面導電鍵合是不必要的，因此不必通過鍍覆通孔20將正面覆蓋板12電連接到多層印刷電路板14的背面。在這樣的情況下，功率MOSFET 64仍可以熱接觸正面覆蓋板12以促進散熱。IC 60的襯底通常需要與MOSFET的漏極68絕緣，因此，最好不與正面覆蓋板12電接觸。
為了能進一步與外部系統電連接，低分佈剖面功率模組10包括金相附接到若干相應的鍵合區19和位於多層印刷電路板14背面的鍍覆通孔20的外部球形柵格陣列30。
對於本技術領域的熟練人員而言，通過上文的敍述顯而易見的是，在適當選擇凹嵌口25的尺寸和數量的情況下，所實施的低分佈剖面功率模組10能夠包圍多個MOSFET，IC以及許多其他類型的有源和無源電路元件，諸如但不限於雙極型器件，IC，電容器，電感器，電阻器，二極體。由於各種電路元件被包圍在功率模組內部，因此呈現低分佈剖面，增強的機械堅固性和遮罩EMI/RFI的特徵。當然，可以使正面覆蓋板12具有熱傳導性，以便於促進雙面鍵合的功率MOSFET 64和IC 60的散熱。由於正面覆蓋板12平整，諸如散熱器，冷卻風扇，迴圈流體冷卻模組和熱電模組(TEM，Thermal Electric Module)的附加的外部散熱裝置能容易地附裝到正面覆蓋板12上，由此促進雙面鍵合的功率MOSFET 64的散熱。
對於其材料，正面覆蓋板12由導電材料製成，諸如銅，鋁，鍍鎳/金的其他金屬或層壓板，碳制導電材料和離子導電材料。正面元件鍵合層27由導電材料製成，諸如填充例如功率MOSFET 64的正面和正面覆蓋板12之間的間隙的焊料膏或者導電環氧樹脂。
第2A圖及第2B圖顯示根據本發明的一個實施例的低分佈剖面功率模組10的製造步驟。步驟Ia中，堆疊四層PCB層14a，14b，14c和14d並相互相對于對方套准。雖然沒有在圖中具體顯示，但是四個PCB層14a，14b，14c和14d中的每一層上都已經預先形成電路形成構造要素。然後在步驟IIa中，將該四層PCB層通常在加熱加壓狀態下層迭到一起。在步驟IIIa中，穿過該層迭板鑽通道孔18及不完全鑽孔以形成各個鍵合區開口17。接下來，在步驟IVa中，對各個通道孔18和鍵合區開口17電鍍導電材料以分別成為鍍覆通孔20和鍵合區19。在步驟Va中印製焊接掩膜22以保護各個鍍覆通孔20和鍵合19，防止之後焊料球在其融化而與各個鍍覆通孔20和鍵合區19導電鍵合期間發生溢流。
在步驟VIa中，通過從相應數量的PCB層，在該情況下為PCB層14a和14b選擇性地切除相應的凹嵌口材料，沿鍵合後的PCB層14a，14b，14c和14d的正面形成凹嵌口25。切除的方法有機械銑切，不完全機械鑽孔和鐳射切割。注意，完成步驟VIa後顯現第三PCB層14c頂部的印刷電路跡線26。
在IC封裝技術中被稱為晶片附貼的步驟VII中，首先將功率MOSFET 64，IC 60和無源器件62等各個電路元件置於凹嵌口25內並機械套准。然後，各個電路元件通過其背面焊接塊24導電鍵合到印刷電路跡線26。如現有技術中眾所周知的一樣，取決於所使用的焊料或者環氧樹脂的類型，要求溫度超過200℃以形成永久鍵合。
在步驟VIII中，正面覆蓋板12置於多層印刷電路板14的頂部，此時，各個電路元件已經導電鍵合到凹嵌口25的底面。然後，多層印刷電路板14的正面與功率MOSFET 64的正面組件鍵合層27一起實體導電鍵合到正面覆蓋板12。
在步驟IX中，已經部分製作完成的低分佈剖面功率模組首先被翻轉。隨後，多個焊料球21被置於多層印刷電路板14上其相應的鍵合區19和鍍附通孔20上。
在步驟X中，所述多個焊接球21被金相鍵合到其相應的鍵合區19和鍍附通孔20以形成外部球形柵格陣列30，用於現在完成的低分佈剖面功率模組10與外部系統的進一步的導電連接。
綜上所述，本發明的上述步驟Ia到步驟X可以被劃分為第一部分(步驟Ia到步驟VII)和第二部分(步驟VIII到步驟X)。第一部分形成多層印刷電路板14以及將功率MOSFET 64，IC 60和無源元件62等各個電路元件導電鍵合到凹嵌口25中。第二部分將多層印刷電路板14的正面與功率MOSFET 64的正面一起實體導電鍵合到導電的正 面覆蓋板12。
第3A圖及第3B圖顯示根據本發明的另一個實施例的低分佈剖面功率模組10的製造步驟。除了步驟Ib到步驟VIb之外，其餘的步驟VII到步驟X和前文根據第2A圖及第2B圖的說明相同。在步驟Ib中，堆疊四層PCB層14a，14b，14c和14d並在X-Y平面內相互相對于對方套准。
步驟IIb中，對於四個PCB層14a，14b，14c和14d中的每一個PCB層，通過機械銑切，不完全機械鑽孔和鐳射切割等方法確定和預先切割出每一個都有特定幾何形狀的特定數量的視窗，這樣，在其後的層迭時，所述四個PCB層將形成預期的凹嵌口25。在該情況中，在第一PCB層14a上形成第一預切割視窗15a，在第二PCB層14b上形成第二預切割視窗15b。由此，在步驟IIIb中，四層PCB層14a，14b，14c和14d在層迭的同時形成凹嵌口25。
在步驟IVb中，穿過層迭的印刷電路板鑽通道孔18，與不完全鑽孔一起形成各個鍵合區開口17。接下來，在步驟Vb中對各個通道孔18和鍵合區開口17電鍍導電材料，分別成為鍍覆通孔20和鍵合區19。在步驟VIb中印製焊接掩模22，保護各個鍍覆通孔20和鍵合區19，防止之後焊料球在其融化而與各個鍍覆通孔20和鍵合區19導電鍵合期間發生溢流。
雖然上文的描述包含許多特殊性，但這些特殊性不應被認為是對本發明範圍的相應的限制，而只是提供對本發明的一些優選實施例的說明。例如，在所述功率MOSFET 64 和IC 60的模組之外，本發明也可以在修改後用於封裝多種其他類型的半導體模組，或者甚至封裝諸如微型電機械系統(MEMS，Miniature Electro Mechanical System)器件的微型機械器件。
縱觀全文的說明和附圖，本文參照具體的結構給出若干示例性的實施例。本技術領域的普通熟練人員將理解的是，本發明能夠以若干其他具體的形式實施，並且本技術領域的普通熟練人員能夠實現這樣的其他實施例而不必過分強調經驗。作為本專利檔的目的，本發明的範圍不限於前文描述的特定的示例性實施例，而是由附後的權利要求定義。處於權利要求的等效內容的含義和範圍內的任何及所有修改都將被認為包括在本發明的精神和範圍之內。
10‧‧‧低分佈剖面功率模組
12‧‧‧正面覆蓋板
14‧‧‧多層印刷電路板
14a-14d‧‧‧PCB層
15a-15b‧‧‧預切割視窗
17‧‧‧鍵合區開口
18‧‧‧層迭板鑽通道孔
19‧‧‧鍵合區
20‧‧‧鍍覆通孔
21‧‧‧焊料球
22‧‧‧焊接掩模
24‧‧‧背面焊接塊
25‧‧‧凹嵌口
26‧‧‧印刷電路跡線
27‧‧‧正面元件鍵合層
30‧‧‧外部球形柵格陣列
60‧‧‧積體電路(IC)
62‧‧‧無源元件
64‧‧‧功率MOSFET
66‧‧‧鍵合區開口
68‧‧‧功率MOSFET漏極
MOSFET‧‧‧金屬氧化物半導體場效應電晶體
PCB‧‧‧印刷電路板
第1圖是本發明的低分佈剖面功率模組的橫截面示意圖；第2A圖及第2B圖顯示根據本發明的一個實施例的低分佈剖面功率模組的製造步驟；第3A圖及第3B圖顯示根據本發明的另一個實施例的低分佈剖面功率模組的製造步驟。
10‧‧‧低分佈剖面功率模組
12‧‧‧正面覆蓋板
14‧‧‧多層印刷電路板
19‧‧‧鍵合區
20‧‧‧鍍覆通孔
22‧‧‧焊接掩模
24‧‧‧背面焊接塊
25‧‧‧凹嵌口
26‧‧‧印刷電路跡線
27‧‧‧正面元件鍵合層
30‧‧‧外部球形柵格陣列
60‧‧‧積體電路(IC)
62‧‧‧無源元件
64‧‧‧功率MOSFET
66‧‧‧鍵合區開口
68‧‧‧功率MOSFET漏極

Claims (7)

  1. 一種低分佈剖面功率模組，其特徵在於，該低分佈剖面功率模組包括：導電的正面覆蓋板；多層印刷電路板，該多層印刷電路板進一步包括多個經鍵合的印刷電路層，每一個印刷電路層在其上都具有電路形成裝置，該多層印刷電路板實體導電鍵合到所述正面覆蓋板；球型柵格陣列，該球型柵格陣列附接到該多層印刷電路板的背面，以實現該低分佈剖面功率模組與外部系統的電連接；所述多層印刷電路板沿其正面進一步包括：a)一個凹嵌口，在其底面上具有電路形成裝置；b)位於該凹嵌口內的多個電路元件，每個電路元件都具有背面元件鍵合裝置，該背面元件鍵合裝置導電鍵合到所述電路形成裝置；由此，該低分佈剖面功率模組包圍所述多個電路元件；c)所述多個電路元件中的至少一個元件進一步包括一功率MOSFET器件，該功率MOSFET器件具有導電鍵合到所述正面覆蓋板的漏極觸點，該功率MOSFET器件的正面和背面都具有觸點；d)所述多個電路元件中的至少一個元件是倒裝的組件，以該低分佈剖面功率模組的取向作為參照，該元件的有源器件區域及其元件鍵合裝置的第一部分位於 其背面，其元件鍵合裝置的第二部分位於其正面；e)以該低分佈剖面功率模組的取向作為參照，所述的功率MOSFET器件進一步具有位於其背面的源極觸點和柵極觸點以及位於其正面的漏極觸點；所述的多層印刷電路板進一步具有多個電鍍的通孔，用以將該球型柵格陣列的一部份導電連接至該正面覆蓋板，從而使得該低分佈剖面功率模組具有增強的機械堅固性和對電磁干擾/射頻干擾的遮罩；所述正面覆蓋板具有熱傳導性，以促進所述多個電路元件中的至少一個電路元件的散熱；以及該低分佈剖面功率模組進一步包括散熱裝置，該散熱裝置從外部通過熱傳導方式，附接到所述正面覆蓋板的正面，以促進所述多個電路元件中的至少一個電路元件的散熱。
  2. 如申請專利範圍第1項所述的低分佈剖面功率模組，其中，所述正面覆蓋板由銅，鋁，鍍鎳/金的金屬或層壓板，碳制導電材料或離子導電材料製成。
  3. 如申請專利範圍第1項所述的低分佈剖面功率模組，其中，所述倒裝的組件是積體電路，功率MOSFET或者二極體。
  4. 一種低分佈剖面功率模組，其特徵在於，該低分佈剖面功率模組包括：導電的正面覆蓋板；多層印刷電路板，該多層印刷電路板進一步包括多個 經鍵合的印刷電路層，每一個印刷電路層在其上都具有電路形成裝置，該多層印刷電路板實體導電鍵合到所述正面覆蓋板；球型柵格陣列，該球型柵格陣列附接到該多層印刷電路板的背面，以實現該低分佈剖面功率模組與外部系統的電連接；所述多層印刷電路板沿其正面進一步包括：a)一個凹嵌口，在其底面上具有電路形成裝置；b)位於該凹嵌口內的多個電路元件，每個電路元件都具有背面元件鍵合裝置，該背面元件鍵合裝置導電鍵合到所述電路形成裝置；由此，該低分佈剖面功率模組包圍所述多個電路元件；c)所述多個電路元件中的至少一個元件進一步包括一功率MOSFET器件，該功率MOSFET器件具有導電鍵合到所述正面覆蓋板的漏極觸點，該功率MOSFET器件的正面和背面都具有觸點；d)所述正面覆蓋板具有熱傳導性，以促進所述多個電路元件中的至少一個電路元件的散熱；所述的多層印刷電路板進一步具有多個電鍍的通孔，用以將該球型柵格陣列的一部份導電連接至該正面覆蓋板；該低分佈剖面功率模組進一步包括散熱裝置，該散熱裝置從外部通過熱傳導方式，附接到所述正面覆蓋板的正面，以促進所述多個電路元件中的至少一個電路元件的散熱，從而使得該低分佈剖面功率模組具有增強的 機械堅固性和對電磁干擾/射頻干擾的遮罩；其中，所述多個電路元件中的至少一個元件是倒裝的組件，以該低分佈剖面功率模組的取向作為參照，該元件的有源器件區域及其元件鍵合裝置的第一部分位於其背面，其元件鍵合裝置的第二部分位於其正面；該倒裝的組件是積體電路，功率MOSFET或者二極體。
  5. 如申請專利範圍第4項所述的低分佈剖面功率模組，其中，所述正面覆蓋板由銅，鋁，鍍鎳/金的金屬或層壓板，碳制導電材料或離子導電材料製成。
  6. 一種包圍多個電路元件的低分佈剖面功率模組的製造方法，其特徵在於，該方法包括：A)形成多層印刷電路板，該多層印刷電路板具有：(1)多個經鍵合的印刷電路層，每一個印刷電路層在其上都具有電路形成裝置；和(2)沿該多層印刷電路板的正面的：(2a)多個凹嵌口，每一個凹嵌口在其底面上都具有電路形成裝置；和(2b)位於多個凹嵌口內的多個電路元件，每一個電路元件都具有導電鍵合到所述電路形成裝置的背面元件鍵合裝置；B)提供導電的正面覆蓋板；和C)將多層印刷電路板的正面實體導電鍵合到所述正面覆蓋板的背面；其中，形成多層印刷電路板的步驟進一步包括： A1)形成多個經鍵合的印刷電路層，每一個印刷電路層在其上都具有電路形成裝置；A2)通過從該印刷電路層的相應層數中選擇性地去除相應的多個凹嵌口材料，沿該多個經鍵合的印刷電路層的正面產生多個凹嵌口；A3)將多個電路元件放置到該多個凹嵌口內；和A4)通過各個電路元件的該背面元件鍵合裝置將多個電路元件導電鍵合到所述電路形成裝置。
  7. 一種包圍多個電路元件的低分佈剖面功率模組的製造方法，其特徵在於，該方法包括：A)形成多層印刷電路板，該多層印刷電路板具有：(1)多個經鍵合的印刷電路層，每一個印刷電路層在其上都具有電路形成裝置；和(2)沿該多層印刷電路板的正面的：(2a)多個凹嵌口，每一個凹嵌口在其底面上都具有電路形成裝置；和(2b)位於多個凹嵌口內的多個電路元件，每一個電路元件都具有導電鍵合到所述電路形成裝置的背面元件鍵合裝置；B)提供導電的正面覆蓋板；和C)將多層印刷電路板的正面實體導電鍵合到所述正面覆蓋板的背面；其中，形成多層印刷電路板的步驟進一步包括：A1)根據多層印刷電路板的層次要求提供多個印刷電 路層，每一個印刷電路層在其上都具有電路形成裝置；A2)對於每個印刷電路層，確定並預先切割出每一個都具有特定幾何形狀的特定數量的視窗，因此在其後的層迭時，該多個印刷電路層將形成所述多個凹嵌口；A3)堆疊並層壓該多個印刷電路層，因此同時形成所述多個凹嵌口；A4)如有因多層印刷電路板的規定的必要，在所述多個經層迭的印刷電路層的每一層上形成其他電路形成裝置；A5)將多個電路元件放置到所述多個凹嵌口內；和A6)通過各個電路元件的背面元件鍵合裝置將多個電路元件導電鍵合到所述電路形成裝置。
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