TWI443826B - 具有整合蕭特基二極體(Schottky diode)之高密度溝槽場效電晶體及其製造方法 - Google Patents
具有整合蕭特基二極體(Schottky diode)之高密度溝槽場效電晶體及其製造方法 Download PDFInfo
- Publication number
- TWI443826B TWI443826B TW096109324A TW96109324A TWI443826B TW I443826 B TWI443826 B TW I443826B TW 096109324 A TW096109324 A TW 096109324A TW 96109324 A TW96109324 A TW 96109324A TW I443826 B TWI443826 B TW I443826B
- Authority
- TW
- Taiwan
- Prior art keywords
- region
- trench
- layer
- germanium
- body region
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 51
- 238000004519 manufacturing process Methods 0.000 title 1
- 210000000746 body region Anatomy 0.000 claims description 150
- 229910052732 germanium Inorganic materials 0.000 claims description 83
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 83
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 25
- 239000013078 crystal Substances 0.000 claims description 21
- 238000002513 implantation Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 10
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 9
- 229910052707 ruthenium Inorganic materials 0.000 claims description 9
- 239000002019 doping agent Substances 0.000 claims description 8
- 239000007943 implant Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 230000001360 synchronised effect Effects 0.000 claims description 3
- 238000005382 thermal cycling Methods 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 4
- 230000000873 masking effect Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 230000002441 reversible effect Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 230000002829 reductive effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000001143 conditioned effect Effects 0.000 description 1
- 210000003298 dental enamel Anatomy 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000002062 proliferating effect Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
本申請案與共同轉讓的美國專利申請案第11/026,276號(申請日:2004年12月29日)有關,其揭示內容併入本文作為參考資料用於所有目的。
大體而言,本發明有關於半導體功率元件技術,特別是有關於用於形成單晶體整合溝槽式閘極場效電晶體(FET)及蕭特基二極體的結構與方法。
在現今的電子裝置中,使用多種電源供應範圍是常見的。例如,在有些應用系統中,中央處理單元係經設計成可取決於計算負載在特定時間以不同的供給電壓操作。結果,電子裝置的直流/直流轉換器已在激增以滿足電路對於電源供應範圍加大的需要。常見的直流/直流轉換器使用通常以功率MOSFET實作的高效率開關。功率開關係經控制成可使用例如脈衝寬度調變(PWM)法來輸送調節過的能量給負載。
第1圖為習知直流/直流轉換器的電路示意圖。PWM控制器100驅動一對功率MOSFET Q1與Q2的閘極端子以調節輸送給負載的電量。MOSFET開關Q2在電路中是用作同步整流器。為了避免突穿電流(shoot-through current),兩個開關其中之一在被開啟之前兩個必須同時關閉。在”無電流時間”期間,每一MOSFET開關的內部二極體(通常被稱作本體二極體(body diode))可導電。可惜本體二極體有相對高正向電壓而會浪費能量。為了改善電路的轉換效率,常外加與MOSFET(Q2)本體二極體並聯的蕭特基二極體102。由於蕭特基二極體有比本體二極體低的正向電壓,因此蕭特基二極體102可有效取代MOSFET本體二極體。以致正向電壓較低的蕭特基二極體可改善耗電量。
多年來,蕭特基二極體係實作於MOSFET開關封裝體外。最近,有些製造商導入離散型蕭特基二極體和離散型功率MOSFET元件一起封裝的產品。也已出現功率MOSFET與蕭特基二極體的單晶體實作。第2圖的例子為習知單晶體整合溝槽式MOSFET及蕭特基二極體。蕭特基二極體210形成於外圍被溝槽MOSFET單元包圍的兩個溝槽200-3、200-4之間。N型基板202形成蕭特基二極體210的陰極端子和溝槽MOSFET的汲極端子。導電層218提供二極體陽極端子而且也用作MOSFET單元的源極互連層。溝槽200-1、200-2、200-3、200-4及200-5內的閘極在第三維度連接在一起且一起被驅動。溝槽MOSFET單元包含具有源極區212和重度本體區(heavy body region)214於其中的本體區208。
第2圖的蕭特基二極體係穿插於溝槽MOSFET單元之間。結果,蕭特基二極體會用掉相當部份的有效面積,導致有較低的電流額定值(current rating)或較大的晶粒尺寸。因此,亟須有優異性能特性且以單晶體及密集整合而成的蕭特基二極體及溝槽閘極FET。
根據本發明之一具體實施例,一種單晶體整合溝槽式FET及蕭特基二極體包含一對結尾於第一導電型第一矽區的溝槽。兩個用第一導電型第二矽區隔開的第二導電型本體區均位於該對溝槽之間。一第一導電型源極區位於各個本體區上方。一接觸開孔(contact opening)在該對溝槽之間延伸成有低於該等源極區的深度。一互連層填滿該接觸開孔以便電氣接觸該等源極區與該第二矽區。在該互連層與該第二矽區電氣接觸處,形成一蕭特基接觸(Schottky contact)。
在一具體實施例中,該第一矽區有比該第二矽區高的摻雜濃度。
在另一具體實施例中,各個本體區在對應源極區與該第一矽區之間垂直延伸,而且該互連層與該第二矽區在深至該等本體區之下半段的地方電氣接觸。
在另一具體實施例中,該兩個本體區各具有大體均勻的摻雜濃度。
在另一具體實施例中,在該對溝槽之間形成一第二導電型重度本體區使得該重度本體區電氣接觸各該兩個本體區與該第二矽區。
在另一具體實施例中,該兩個本體區、該等源極區、以及該重度本體區均與該對溝槽自對準。
在另一具體實施例中,該兩個本體區與該第二矽區大體有相同的深度。
根據本發明另一具體實施例,以下形成一種單晶體整合溝槽式FET及蕭特基二極體。形成兩個溝槽延伸通過一上矽層且在一下矽層內結尾。該等上、下矽層有第一導電型,而且該上矽層在該下矽層上方延伸。在該對溝槽之間的該上矽層內形成第二導電型的第一及第二矽區。在該對溝槽之間形成一伸入該第一及該第二矽區的第一導電型第三矽區使得該第一及該第二矽區的其餘下半部形成兩個以該上矽層之一部份隔開的本體區。進行矽蝕刻(silicon etch)以形成一延伸通過該第一矽區的接觸開孔藉此保留該第一矽區的外部。該第一矽區的外部係形成數個源極區。形成一填滿該接觸開孔的互連層以便電氣接觸該等源極區與該上矽層之該部份。在該互連層與該第二矽區電氣接觸處,形成一蕭特基接觸。
在一具體實施例中,該下矽層有比該上矽層高的摻雜濃度。
在另一具體實施例中,使該互連層與該上矽層之該部份在深度低於該等源極區的地方電氣接觸。
在另一具體實施例中,每一該第一區及該第二區有大體均勻的摻雜濃度。
在另一具體實施例中,在該對溝槽之間形成一第二導電型重度本體區。該重度本體區係延伸進入該兩個本體區且進入該上矽層之該部份。
在另一具體實施例中,該兩個本體區、該等源極區、以及該重度本體區均與該對溝槽自對準。
參考本專利說明書其餘部份及附圖可進一步理解本文所揭示之本發明的本質與優點。
第1圖為習知使用有蕭特基二極體之功率MOSFET的直流/直流轉換器的電路示意圖;第2圖為習知單晶體整合溝槽式MOSFET及蕭特基二極體的橫截面圖;第3圖的示範簡化等角視圖係根據本發明之一具體實施例圖示條狀單元(stripe-shaped cell)陣列中之一部份,其中各有溝槽MOSFET和整合於其中的蕭特基二極體;第4圖為第3圖沿著重度本體區326繪出的橫截面圖;第5圖的簡化橫截面圖係根據本發明之一具體實施例圖示第3圖及第4圖中之重度本體區的替代實作;第6A圖至第6F圖的簡化橫截面圖係根據本發明之一具體實施例圖示用於形成第3圖單晶體整合溝槽式MOSFET及蕭特基二極體的示範製程順序;以及,第7A圖至第7C圖係圖示有3種不同凹洞深度(dimple depth)之單晶體整合溝槽式MOSFET及蕭特基二極體結構的模擬突崩電流線(simulated avalanche current flow lines)。
根據本發明的具體實施例,在單元陣列中,多次重覆以最佳方式把蕭特基二極體和溝槽MOSFET整合於單一單元內。整合蕭特基二極體所犧牲的有效面積為零到最低程度,但蕭特基二極體的總面積大到足以百分之百處理二極體的正向導電。因此,MOSFET本體二極體永不開啟,這可排除反向恢復的損耗。此外,由於蕭特基二極體有比MOSFET本體二極體低的正向壓降,因此可降低功率損耗。
此外,蕭特基二極體與MOSFET的整合係使得蕭特基接觸在MOSFET源極區的下面形成。這有利於使突崩電流由該等源極區轉移到蕭特基區,可防止寄生雙極電晶體(parasitic bipolar transistor)打開。因此,能改善裝置的耐用度。本發明此一特徵在極大程度上也排除對於重度本體區的需要,而先前技術結構的每一MOSFET單元通常需要重度本體區用來防止寄生雙極電晶體打開。重度本體區的島體反而以間歇方式加上且彼此遠離僅僅為了確保源極金屬與本體區有良好的接觸。本質上,在極大程度上用蕭特基二極體取代在先前技術溝槽MOSFET中是必要的重度本體區。因此,不需分配額外的矽面積給蕭特基二極體。
第3圖的示範簡化等角視圖係根據本發明之一具體實施例圖示條狀單元陣列中之一部份,其中各有溝槽MOSFET和整合於其中的蕭特基二極體。重度摻雜N型(N+)區302覆蓋在N型矽基板上(未圖示),該N型矽基板已有比N+區302高出很多的摻雜濃度(N++)。多個溝槽304在N+區302內延伸至預定深度。各溝槽304內嵌入一遮蔽電極(shield electrode)305與一上覆閘極308。在一具體實施例中,遮蔽電極305與閘極308由多晶矽構成。極間介電質(inter-electrode dielectric)310使得該閘極與遮蔽電極彼此絕緣。遮蔽介電層312覆蓋各溝槽304的下側壁及底部,且使遮蔽電極305與周遭的N+區302絕緣。比遮蔽介電質(shield dielectric)312薄些的閘極介電質316覆蓋溝槽304的上側壁。介電質蓋體(dielectric cap)314在各閘極308上方延伸。在一具體實施例中,遮蔽電極305沿著第三維度與源極區電氣連接,且因而在操作期間被偏壓成與該等源極區有相同的電位。在其他具體實施例中,遮蔽電極305沿著第三維度電氣受制於(或允許浮動)閘極308。
配置兩個以輕度摻雜N型(N-)區320隔開的P型本體區318於每兩個相鄰溝槽304之間。各本體區318沿著一個溝槽側壁延伸。在圖示於附圖及揭示於本文的各種具體實施例中,本體區318與N-區320有大體相同的深度,不過本體區318可比N-區320稍微淺些或深些,這對裝置操作不會有明顯的影響。配置一重度摻雜N型源極區322於各個本體區318正上方。源極區322垂直重疊於閘極308,且由於有形成接觸開孔的凹洞324而有圓弧狀外形。在對應源極區322的下面,各凹洞324在每兩個相鄰溝槽之間延伸。如圖示,源極區322與本體區318一起形成凹洞324的圓形側壁,且N-區320是沿著凹洞324底部延伸。在一具體實施例中,N+區302為一N+磊晶層,而且N-區320均為有數個本體區318及源極區322形成於其中之N-磊晶層的部份。當MOSFET 300被開啟時,各本體區318中沿著溝槽側壁在各個源極區322與重度摻雜區302之間形成垂直通道。
蕭特基屏蔽金屬層(Schottky barrier metal)330(第3圖中被揭開以暴露底下的區域)會填滿凹洞324且在介電質蓋體314上方延伸。蕭特基屏蔽金屬層330係沿著凹洞324底部與N-區320電氣接觸,從而形成蕭特基接觸。蕭特基屏蔽金屬層330也用來作為在上面的源極互連,電氣接觸源極區322與重度本體區326。
在反向偏壓期間,在各本體/N-接面形成的空乏區有利地併入N-區320從而使在蕭特基接觸下方的N-區320完全空乏。這可排除蕭特基洩露電流,接著可用功函數較低的屏蔽金屬。因此,蕭特基二極體可得到更低的正向電壓。
如圖示,重度本體區326的島體是沿著單元條帶間歇地形成。重度本體區326延伸通過N-區320。這在第4圖會更清楚,第4圖為第3圖沿著重度本體區326繪出的橫截面圖。第4圖的橫截面圖在極大程度上與沿著第3圖等角視圖正面繪出的橫截面圖相似,除了第4圖中在每兩個相鄰溝槽之間的兩個源極區用一延伸通過N-區320的連續重度本體區326取代。重度本體區326提供源極金屬330與本體區318之間的歐姆接觸。由於重度本體區326延伸通過N-區320,所以不會有蕭特基二極體形成於該等區域。在該等區域中也不會有MOSFET電流,因為沒有源極區。
第5圖的簡化橫截面圖係根據本發明之一具體實施例圖示第3圖及第4圖中之重度本體區的替代實作。第5圖中,重度本體區526只沿著各凹洞524的底部部份延伸使得源極區522保持原樣。因此,MOSFET電流不會在這些區域中流動,但重度本體區526可防止蕭特基屏蔽金屬層430與N-區310接觸從而在該等區域中不會形成蕭特基二極體。
請再參考第3圖,間歇放置重度本體區326的方式不同於重度本體區是沿著單元條帶全長於兩個相鄰源極區之間延伸的習知實作(如第2圖的先前技術結構)。由於有蕭特基二極體與溝槽MOSFET整合的方式,所以第3圖的結構不需要連續的重度本體區。由第3圖可見,藉由使凹洞324在源極區322下充分延伸,同樣可源極區322下形成蕭特基接觸。如以下結合第7A圖至第7C圖所做更完整的描述,藉由配置蕭特基接觸於源極區322正下方,使突崩電流由源極區322轉移到蕭特基區,從而可防止寄生雙極電晶體打開。這可排除通常在先前技術結構中為必需沿著單元條帶配置連續重度本體區的需要。重度本體區326的島體反而以間歇方式加上且彼此遠離僅僅為了確保源極金屬330與本體區318有良好的接觸。藉由在極大程度上用蕭特基區取代連續重度本體區,不需分配額外的矽面積給蕭特基二極體。因此,整合蕭特基二極體不用犧牲矽面積。
在一些具體實施例中,沿著條帶安排重度本體區326的頻率則視裝置切換上的要求而定。對於切換較快的裝置,沿著條帶安排重度本體區的頻率較高。對於該等裝置,可能需要額外的矽面積分配給蕭特基二極體(例如,藉由增加單元間距)。對於切換較慢的裝置,沿著條帶需要較少的重度本體區。對於該等裝置,安排重度本體區於條帶各端可能就夠,從而使蕭特基二極體面積最大化。
第6A圖至第6F圖的簡化橫截面圖係根據本發明之一具體實施例圖示用於形成第3圖整合MOSFET-蕭特基結構的示範製程順序。第6A圖中,使用習知技術形成覆蓋著矽基板(未圖示)的兩個磊晶層602與620。屬於輕度摻雜N型層(N-)的磊晶層620是在重度摻雜N型層(N+)的磊晶層620上方延伸。形成、圖樣化及蝕刻一硬遮罩(例如,由氧化物組成)以形成硬遮罩島體601於N-磊晶層620上方。從而,通過由硬遮罩島體601界定的開孔606暴露出N-磊晶層620的表面積。在一具體實施例中,界定溝槽寬度的開孔606各約為0.3微米,而且各硬遮罩島體601的寬度是在0.4至0.8微米的範圍內。這些尺寸係界定單元(MOSFET及蕭特基二極體形成於其中)的間距。影響該等尺寸的因子包括微影設備的性能和設計及性能目標。
第6B圖中,使用習知矽蝕刻技術,通過開孔606藉由蝕刻矽來形成在N-磊晶層620內結尾的溝槽603。在一具體實施例中,溝槽603有約1微米的深度。然後,使用習知選擇性磊晶成長(SEG)製程在各個溝槽603內成長重度摻雜P型(P+)矽區618A。在一具體實施例中,P+矽區618A大約有5x1017
厘米-3
的摻雜濃度。在另一具體實施例中,在形成P+區618之前,形成一覆蓋溝槽608側壁及底部的高品質矽薄層。該薄矽層係用來作為適合成長P+矽的無瑕矽表面。
第6C圖中,進行擴散製程以使P+區618A內的p型摻雜物擴散至N-磊晶層620。因而,形成在硬遮罩島體601下側向延伸且向下延伸至N-磊晶層620的向外擴散之P+區618B。可進行多次熱循環以達成想要的外擴散。第6C圖中的點線圖示溝槽603的輪廓。此一擴散製程,以及製程中其他的熱循環會導致N+磊晶層602向上擴散。在選定N-磊晶層620厚度時,需要考慮到N+磊晶層602的向上擴散。
第6D圖中,使用硬遮罩島體601,進行深溝槽蝕刻製程以形成延伸通過P+區618B及N-磊晶層620、在N+磊晶層602中結尾的溝槽604。在一具體實施例中,溝槽604約有2微米的深度。該溝槽蝕刻製程切斷且移除各P+矽區618B的中央部份,留下沿著溝槽側壁延伸、垂直在外的P+長條618C。
在本發明另一具體實施例中,P+長條618C都用二回合斜向植入(two-pass angled implant)形成,而不是以第6B圖至第6D圖圖示的SEG技術,隨後會加以描述。第6B圖中,在通過遮罩開孔606形成溝槽603後,使用習知二回合斜向植入技術將諸如硼之類的P型摻雜物植入相對的溝槽側壁。硬遮罩島體604用來作為植入製程期間的堵塞結構以防止植入離子進入平台區(mesa region)且使植入離子的位置局限於N-磊晶層620中想要的區域。為了得到第6D圖的結構,在二回合斜向植入後,進行第二次溝槽蝕刻以使溝槽603的深度延伸至N+磊晶層602。在一變體中,只做一回溝槽蝕刻(而不是二回合)如下。第6B圖中,使用硬遮罩島體601,進行溝槽蝕刻以形成溝槽能伸入N+磊晶層602約有與第6D圖溝槽604一樣的深度。然後,進行二回合斜向植入以植入P型摻雜物至相對的溝槽側壁。調整植入角度與硬遮罩島體601的厚度以界定要接受植入離子的上溝槽側壁區。
第6E圖中,使用習知技術在溝槽604中形成遮蔽閘極結構。形成覆蓋溝槽604下側壁及底部的遮蔽介電質612。然後,形成填滿溝槽604下半部的遮蔽電極605。然後,形成極間介電層610於遮蔽電極605上方。然後形成覆蓋上溝槽側壁的閘極介電質616。在一具體實施例中,閘極介電質616是在階段的較早階段中形成。形成填滿溝槽604上半部的凹陷閘極608。介電質蓋體區614在閘極608上方延伸且填滿溝槽604的其餘部份。
接下來,將N型摻雜物植入所有露出的矽區,接著是驅入擴散製程(drive in process),藉此形成N+區622A。在形成N+區622A時,作用區不使用遮罩。如第6E圖所示,與形成遮蔽閘極結構及N+區622A有關的各種熱循環使得P型區618C向外擴散從而形成較寬且較高的本體區618D。如前述,該等熱循環也使N+磊晶層602向上擴散,如第6E圖所示。重要的是要確保在完成製程後,在每兩個相鄰溝槽之間的兩個本體區仍然分開且不會合併,否則蕭特基二極體會被排除。設計該製程的另一目標是要確保N-磊晶層620與本體區618D在製程完成後有大體相同的深度,然而深度稍有不同對於裝置的操作不會有致命傷害。達成該等目標可藉由調整製程步驟數目及參數,包括熱循環、第一溝槽凹陷的深度(第6B圖)、以及各區的摻雜濃度,包括本體區、N-磊晶層區、以及N+磊晶層區。
第6F圖中,作用區中不使用遮罩,進行凹洞蝕刻製程以蝕穿N+區622A藉此保留N+區622A的外部622B。留下的外部622A會形成源極區。從而,在每兩個相鄰溝槽之間形成凹洞624。凹洞624會形成在源極區622B上延伸且進入N-區620的接觸開孔。本揭示內容所用的”凹洞蝕刻”係指導致形成有斜度圓弧外形之矽區(如第6F圖中之源極區622B)的矽蝕刻技術。在一具體實施例中,該等凹洞向下延伸至本體區618D的下半段內。如前述,較深的凹洞導致在該等源極區下面形成蕭特基接觸。這有助於使反向突崩電流由源極轉向,從而防止寄生雙極電晶體打開。儘管上述凹洞蝕刻在作用區中不需要遮罩,在一替代具體實施例中,使用一遮罩以在N+區622A界定蝕穿至想要深度的中央部份。因此可保留N+區622A在該遮罩下面延伸的外部。該等外部區係形成該等源極區。
使用遮罩層,將P型摻雜物植入以間歇方式沿著各條帶的凹洞區。從而,在每兩個相鄰溝槽之間形成重度本體區(未圖示)的島體。如果想要第4圖的重度本體實作,在重度本體植入期間要用夠高劑量的P型摻雜物以便反向摻雜(counter-dope)待形成為重度本體區的源極區部份。如果想要第5圖的重度本體實作,在重度本體植入期間要用較低劑量的使得該等源極區不被反向摻雜從而保持原樣。
第6F圖中,可用習知技術在結構上方形成蕭特基屏蔽金屬層630。蕭特基屏蔽金屬層630填滿凹洞624,且在金屬630與N-區620電氣接觸處,形成一蕭特基二極體。金屬層630也使源極區622B與重度本體區接觸。
在以第6A圖至第6F圖圖示的製程順序中,兩個所用之遮罩都不需有高標準的對齊。結果,整合MOSFET-蕭特基結構有許多垂直及水平自對準特徵。此外,上述製程具體實施例使得減少通道長度成為有可能。習知製程係使用植入及驅入技術以形成該等本體區。此種技術導致通道區中有錐狀摻雜外形以致需要較長的通道長度。相比之下,上述選擇性磊晶成長與二回合斜向植入用於形成本體區的替代技術在通道區中可提供均勻的摻雜外形,從而可使用較短的通道長度。從而,可改善裝置的接通電阻(on-resistance)。
此外,使用雙磊晶結構可提供能優化崩潰電壓及通電阻同時保持緊密控制MOSFET臨界電壓(Vth)的設計彈性。藉由在N-磊晶層618中形成本體區618,與N+磊晶層602相比,摻雜濃度一致性及可預測性會更高,而可實現MOSFET臨界電壓(Vth)的緊密控制。在摻雜濃度可預測的下,在背景區中形成本體區使得更緊密地控制臨界電壓成為有可能。另一方面,就相同的崩潰電壓而言,伸入N+磊晶層602的遮蔽電極605使得N+磊晶層602可使用較高的摻雜濃度。從而,相同的崩潰電壓可得到較低的接通電阻而對於MOSFET臨界電壓的緊密控制不會有負面影響。
第7A圖至第7C圖係圖示有3種不同凹洞深度之整合溝槽MOSFET-蕭特基二極體結構的模擬突崩電流線。在第7A圖的結構中,凹洞729A剛好延伸到在源極區722下面的深度。在第7B圖的結構中,凹洞729B延伸較深到約有本體區718的一半高度。在第7C圖的結構中,凹洞729C延伸更深剛好到本體區718的底面上。在第7A圖至第7C圖中,在上金屬730中出現間隙。包含此間隙係僅供模擬用,且在實務上,上金屬中不會有這種間隙,這在本揭示內容其他附圖是顯而易見的。
由第7A圖可見,突崩電流線732A與源極區722靠得很近,然而由於凹洞的深度在第7B圖中有增加且在第7C圖為更深,以致突崩電流線732B與732C更為遠離源極區722而移向蕭特基區。突崩電流離開源極區有助於防止寄生雙極電晶體打開,從而改善裝置的耐用度。本質上,在使突崩電流集中時,蕭特基區的作用類似重度本體區,從而就此目的而言,可排除對於重度本體區的需要。重度本體區仍然需要以使本體區有良好的接觸,但與習知MOSFET結構相比,重度本體區的頻率及尺寸可顯著減少。這可釋出分配給蕭特基二極體的大矽面積。因此,就第7A圖至第7C圖的示範模擬結構而言,深度延伸到本體區718下半段內的凹洞可提供最佳結果。
儘管已用數個遮蔽閘極溝槽MOSFET具體實施例來描述本發明,熟諳此藝者於閱讀本揭示內容後,會明白本發明還有其他遮蔽閘極MOSFET結構和有厚底介電質之溝槽閘極MOSFET以及其他類型之功率元件的具體實作。例如,上述用於整合蕭特基二極體與MOSFET的技術可同樣實作於上述美國專利申請案第11/026,276號(2004年12月29日申請)所揭示的各種功率元件中,特別是圖示於例如第1、2A、3A、3B、4A、4C、5C、9B、9C、10至12圖及第24圖的溝槽閘極、遮蔽閘極、以及電量平衡裝置(charge balance device)。
儘管以上圖示及描述了許多特定具體實施例,但本發明的具體實施例不受限於這些。例如,儘管本發明有些具體實施例是用開放單元結構(open cell structure)來描述,然而熟諳此藝者在閱讀本揭示內容後會明白實作本發明可使用有各種幾何形狀的封閉單元結構,例如多邊形、圓形、以及矩形。此外,儘管本發明的具體實施例是用n-通道裝置來描述,然而該等具體實施例中之矽區的導電型可顛倒以得到p-通道裝置。因此,請勿參考上述說明來判定本發明的範疇,而應參考隨附之申請專利範圍以及彼等之全範圍等價陳述來判定。
100...PWN控制器
102...蕭特基二極體
200-1,200-2,200-3,200-4,200-5...溝槽
202...N型基板
208...本體區
210...蕭特基二極體
212...源極區
214...重度本體區
218...導電層
300...MOSFET
302...N+區
304...溝槽
305...遮蔽電極
308...上覆閘極
310...極間介電質
312...遮蔽介電層
314...介電質蓋體
316...閘極介電質
318...的P型本體區
320...輕度摻雜N型(N-)區
322...重度摻雜N型源極區
324...凹洞
326...重度本體
330...蕭特基屏蔽金屬層
430...蕭特基屏蔽金屬層
522...源極區
524...凹洞
526...重度本體區
601...硬遮罩島體
602...磊晶層
603...溝槽
604...硬遮罩島體
605...遮蔽電極
606...開孔
608...溝槽
610...極間介電層
612...遮蔽介電質
614...介電質蓋體區
616...閘極介電質
618...P+區
618A...重度摻雜P型(P+)矽區
618B...向外擴散之P+區
618C...P+長條
618D...本體區
620...磊晶層
622A...N+區
622B...外部
624...凹洞
630...蕭特基屏蔽金屬層
718...本體區
722...源極區
729A,729B...凹洞
730...上金屬
732A,732B,732C...突崩電流線
第1圖為習知使用有蕭特基二極體之功率MOSFET的直流/直流轉換器的電路示意圖;第2圖為習知單晶體整合溝槽式MOSFET及蕭特基二極體的橫截面圖;第3圖的示範簡化等角視圖係根據本發明之一具體實施例圖示條狀單元(stripe-shaped cell)陣列中之一部份,其中各有溝槽MOSFET和整合於其中的蕭特基二極體;第4圖為第3圖沿著重度本體區326繪出的橫截面圖;第5圖的簡化橫截面圖係根據本發明之一具體實施例圖示第3圖及第4圖中之重度本體區的替代實作;第6A圖至第6F圖的簡化橫截面圖係根據本發明之一具體實施例圖示用於形成第3圖單晶體整合溝槽式MOSFET及蕭特基二極體的示範製程順序;以及,第7A圖至第7C圖係圖示有3種不同凹洞深度(dimple depth)之單晶體整合溝槽式MOSFET及蕭特基二極體結構的模擬突崩電流線(simulated avalanche current flow lines)。
300...MOSFET
302...N+區
304...溝槽
305...遮蔽電極
308...上覆閘極
310...極間介電質
312...遮蔽介電層
314...介電質蓋體
316...閘極介電質
318...的P型本體區
320...輕度摻雜N型(N-)區
322...重度摻雜N型源極區
324...凹洞
326...重度本體
330...蕭特基屏蔽金屬層
Claims (45)
- 一種包含一單晶體整合溝槽式FET及蕭特基二極體之結構,該單晶體整合溝槽式FET及蕭特基二極體包含:一第一溝槽,其係終止於一第一導電型的第一矽區;一第二溝槽,其係終止於該第一導電型的第一矽區;一第二導電型的第一本體區;一第二導電型的第二本體區,該第一本體區及該第二本體區設置在該第一溝槽及該第二溝槽之間,該第一本體區及該第二本體區係以有第一導電型的一第二矽區隔開;一第一導電型的第一源極區,其設在該第一本體區上方;一第一導電型的第二源極區,其設在該第二本體區上方;一接觸開孔,其延伸於該第一溝槽與該第二溝槽之間直至一深度,該深度係低於該第一源極區與該第二源極區中之至少一者的深度;以及,一互連層,其係填滿該接觸開孔並且電氣接觸該第一源極區、該第二源極區及該第二矽區,該互連層與該第二矽區形成一蕭特基接觸。
- 如申請專利範圍第1項之結構,其中該第一矽區具有比該第二矽區高的摻雜濃度。
- 如申請專利範圍第1項之結構,其中該第一本體區及該第二本體區之各者係於該第一矽區與該第一源極區及該第二源極區中之一相對者之間垂直延伸,而且該互連層與該第二矽區在深至大於該第一本體區及該第二本體區中至少一者的一半深度處電氣接觸。
- 如申請專利範圍第1項之結構,其中該第一本體區及該第二本體區中至少一者的摻雜濃度是均勻的。
- 如申請專利範圍第1項之結構,其中該第一矽區為一第一磊晶層,而該第二矽區為一第二磊晶層,該第一磊晶層係於一第一導電型基板上方延伸,該基板具有比該第一磊晶層高的摻雜濃度,而該第一磊晶層具有比該第二磊晶層高的摻雜濃度。
- 如申請專利範圍第1項之結構,其中該第一本體區與該第一源極區係與該第一溝槽自對準。
- 如申請專利範圍第1項之結構,其更包含一形成於該第一溝槽與該第二溝槽之間的第二導電型之重度本體區藉此該重度本體區電氣接觸該第一本體區、該第二本體區與該第二矽區,該重度本體區具有比該第一本體區及該第二本體區中之一者高的摻雜濃度。
- 如申請專利範圍第7項之結構,其中該第一本體區、該第一源極區以及該重度本體區係與該第一溝槽自對準。
- 如申請專利範圍第1項之結構,其中該第二本體區與該第二矽區具有相同的深度。
- 如申請專利範圍第1項之結構,其更包含:一設在該第一溝槽中的凹陷閘極;以及,一使該凹陷閘極與該互連層絕緣的介電質蓋體。
- 如申請專利範圍第10項之結構,其更包含:一設在該凹陷閘極下面且在該第一溝槽內的遮蔽電極;以及,一使該遮蔽電極與該第一矽區絕緣的遮蔽介電質。
- 如申請專利範圍第10項之結構,其更包含:一厚底介電質,其係沿著該第一溝槽之底部在該凹陷閘極正下方延伸。
- 如申請專利範圍第1項之結構,其更包含一直流至直流同步降壓式轉換器,其中該單晶體整合溝槽式FET及蕭特基二極體係耦合至一負載作為低端開關。
- 如申請專利範圍第1項之結構,其中該互連層為一蕭特基屏蔽金屬層。
- 一種包含一單晶體整合溝槽式MOSFET及蕭特基二極體之結構,該單晶體整合溝槽式MOSFET及蕭特基二極體包含:一第一導電型之第一磊晶層;一設在該第一磊晶層上方的第一導電型之第二磊晶層,該第一磊晶層具有比該第二磊晶層高的摻雜濃度;一第一溝槽及一第二溝槽,各個係延伸通過該第二磊晶層且終止於該第一磊晶層; 一第二導電型的第一本體區;一第二導電型的第二本體區,該第一本體區及該第二本體區設在該第一溝槽及該第二溝槽之間,該第一本體區及該第二本體區係藉由該第二磊晶層之一部份而隔開;一第一導電型的第一源極區,其設在該第一本體區上方;一第一導電型的第二源極區,其設在該第一本體區上方;一接觸開孔,其延伸於該第一溝槽與該第二溝槽之間直至一深度,該深度係低於該第一源極區與該第二源極區中之至少一者的深度;以及,一蕭特基屏蔽金屬層,其係填滿該等接觸開孔以及電氣接觸該第一源極區、該第二源極區與該第二磊晶層之該部份,該蕭特基屏蔽金屬層與該第二磊晶層之該部份形成一蕭特基接觸。
- 如申請專利範圍第15項之結構,其中該第一本體區在該第一源極區與該第一磊晶層之間垂直延伸,而且該蕭特基屏蔽金屬層與該第二磊晶層之該部份在深至大於該第一本體區之一半深度處電氣接觸。
- 如申請專利範圍第15項之結構,其中該第一本體區及該第二本體區中至少一者具有均勻的摻雜濃度。
- 如申請專利範圍第15項之結構,其中該第一磊晶層係於一第一導電型之基板上方延伸,該基板具有比該第 一磊晶層高的摻雜濃度。
- 如申請專利範圍第15項之結構,其中該第一本體區與該第一源極區係與該第一溝槽自對準。
- 如申請專利範圍第15項之結構,其更包含形成於該第一溝槽與該第二溝槽之間的一第二導電型之重度本體區,藉此該重度本體區電氣接觸該第一本體區、該第二本體區與該第二磊晶層位於該第一溝槽及該第二溝槽之間的部份。
- 如申請專利範圍第20項之結構,其中該第一本體區、該第一源極區、以及該重度本體區係與該第一溝槽自對準。
- 如申請專利範圍第15項之結構,其中該第一本體區與該第二磊晶層具有相同的深度。
- 如申請專利範圍第15項之結構,其更包含:一設在該第一溝槽中的凹陷閘極;以及,一使該凹陷閘極與該蕭特基屏蔽金屬層絕緣的介電質蓋體。
- 如申請專利範圍第23項之結構,其更包含:一設在該凹陷閘極下面且在該第一溝槽內的遮蔽電極;以及,一使該遮蔽電極與該第一磊晶層絕緣的遮蔽介電質。
- 如申請專利範圍第23項之結構,其更包含:一厚底介電質,其係沿著該第一溝槽之底部在該凹 陷閘極正下方延伸。
- 如申請專利範圍第15項之結構,其更包含一直流至直流同步降壓式轉換器,其中該單晶體整合溝槽式MOSFET及蕭特基二極體係耦合至一負載作為低端開關。
- 一種形成單晶體整合溝槽式FET及蕭特基二極體的方法,該方法包含:形成一第一溝槽及一第二溝槽,各個係延伸通過一上矽層且終止在一下矽層內,該上、下矽層具有第一導電型,該上矽層在該下矽層上方延伸;在該第一溝槽與該第二溝槽之間的該上矽層內形成第二導電型的一第一矽區及一第二矽區;在該第一溝槽與一第二溝槽之間形成一延伸入該第一矽區及該第二矽區的第一導電型之第三矽區,使得該第一矽區的下半部及該第二矽區的下半部分別形成一第一本體區及一第二本體區,該第一本體區及第二本體區以該上矽層之一部份隔開;進行矽蝕刻以形成一延伸通過該第一矽區的接觸開孔,藉此保留該第一矽區的外部,該第一矽區的外部係形成一源極區;以及,形成一填滿該接觸開孔以及電氣接觸該源極區與該上矽層之該部份的互連層,該互連層與該上矽層之該部份形成一蕭特基接觸。
- 如申請專利範圍第27項之方法,其中該下矽層具有 比該上矽層高的摻雜濃度。
- 如申請專利範圍第27項之方法,其中使該互連層與該上矽層之該部份在深度低於該源極區的地方電氣接觸。
- 如申請專利範圍第27項之方法,其中使該互連層與該上矽層之該部份在深至一大於該第一本體區之一半深度處電氣接觸。
- 如申請專利範圍第27項之方法,其中該第一本體區及該第二本體區中至少一者具有均勻的摻雜濃度。
- 如申請專利範圍第27項之方法,其中在一第一導電型基板上方磊晶形成該下矽層,且在該下矽層上方磊晶形成該上矽層,其中該基板具有比該下矽層高的摻雜濃度,以及該下矽層具有比該上矽層高的摻雜濃度。
- 如申請專利範圍第27項之方法,其中該第一本體區與該源極區係與該第一溝槽自對準。
- 如申請專利範圍第27項之方法,其更包含:在該第一溝槽與該第二溝槽之間形成一第二導電型的重度本體區,該重度本體區係延伸進入該第一本體區、該第二本體區且進入該上矽層之該部份,該重度本體區具有比該第一本體區及該第二本體區中至少一者高的摻雜濃度。
- 如申請專利範圍第34項之方法,其中該第一本體區、該源極區以及該重度本體區係與該第一溝槽自對準。
- 如申請專利範圍第27項之方法,其中該第一本體區與該上矽層具有相同的深度。
- 如申請專利範圍第27項之方法,其更包含:形成一在該第一溝槽中的凹陷閘極;以及,形成一使該凹陷閘極與該互連層絕緣的介電質蓋體。
- 如申請專利範圍第37項之方法,其更包含:在形成該凹陷閘極之前,在該第一溝槽的底部部份中形成一遮蔽電極。
- 如申請專利範圍第37項之方法,其更包含:在形成該凹陷閘極之前,形成一沿著該第一溝槽之底部延伸的厚底介電質。
- 如申請專利範圍第27項之方法,其中該互連層為一蕭特基屏蔽金屬層。
- 一種形成單晶體整合溝槽式MOSFET及蕭特基二極體的方法,該方法包含:使用一遮罩,形成延伸進入且終止於一第一導電型之上矽層的多數第一溝槽,該上矽層設在一第一導電型之下矽層上方;用一第二導電型之矽材料填滿該等多數第一溝槽;進行熱循環以使該矽材料的一部分向外擴散進入該上矽層且到該遮罩下面;使用該遮罩,形成延伸通過該矽材料、該上矽層且終止於該下矽層內的多數第二溝槽,使得該矽材料在該 遮罩下的向外擴散部份保留在該各個第二溝槽的一邊上;形成一延伸進入該向外擴散部份的第一導電型之第一矽區,使得該向外擴散部份在該等多數第二溝槽的每兩個相鄰溝槽之間的其餘下半部形成一第一本體區及一第二本體區,該第一本體區及該第二本體區係以該上矽層之一部份隔開;進行矽蝕刻以形成一延伸通過該第一矽區的接觸開孔,藉此保留該第一矽區的外部,該第一矽區的外部係形成一源極區;以及,形成一填滿該接觸開孔以及電氣接觸該源極區與該上矽層之該部份的互連層,該互連層與該上矽層之該部份形成一蕭特基接觸。
- 一種形成單晶體整合溝槽式MOSFET及蕭特基二極體的方法,該方法包含:使用一遮罩,形成延伸通過一第一導電型之上矽層且終止於一第一導電型之下矽層內的一第一溝槽及一第二溝槽,該上矽層設在該下矽層上方;進行二回合斜向植入以沿著該第一溝槽及該第二溝槽之各者之一上側壁在該上矽層中形成一第二導電型的第一矽區;在該第一溝槽與該第二溝槽之間形成延伸入該第一矽區的一第一導電型之第二矽區,使得該第一矽區的其餘下半部在該第一溝槽與該第二溝槽之間形成一第 一本體區及一第二本體區,該第一本體區及該第二本體區係藉由該上矽層之一部份而隔開;進行矽蝕刻以形成一延伸通過該第二矽區的接觸開孔,藉此保留該第二矽區的外部於該第一溝槽與該第二溝槽之間,該第二矽區的外部形成一源極區;以及,形成一填滿該接觸開孔以及電氣接觸該源極區與該上矽層之該部份的互連層,該互連層與該上矽層之該部份形成一蕭特基接觸。
- 如申請專利範圍第42項之方法,其中該上矽層在該二回合斜向植入期間接受摻雜物的區域是用該植入角度及該遮罩的厚度來界定。
- 一種形成單晶體整合溝槽式MOSFET及蕭特基二極體的方法,該方法包含:使用一遮罩,形成延伸進入且終止於一第一導電型的上矽層內之第一深度的多數溝槽,該上矽層設在一第一導電層的下矽層上方;進行二回合斜向植入以沿著各個溝槽的一側壁在該上矽層中形成一第二導電型的第一矽區;使用該遮罩,在該下矽層內使該等多數溝槽較深地延伸而有第二深度;在該等多數溝槽的每兩個相鄰溝槽之間形成一延伸入該第一矽區的一第一導電型第二矽區,使得該第一矽區的其餘下半部形成在該等多數溝槽的每兩個相鄰溝槽之間的一第一本體區及一第二本體區,該第一本體 區及該第二本體區係藉由該上矽層之一部份隔開;進行矽蝕刻以形成一延伸通過該第二矽區的接觸開孔,藉此保留該第二矽區的外部於該等多數溝槽的每兩個相鄰溝槽之間,該第二矽區的外部形成一源極區;以及,形成一填滿該接觸開孔以及電氣接觸該源極區與該上矽層之該部份的互連層,該互連層與該上矽層之該部份形成一蕭特基接觸。
- 如申請專利範圍第44項之方法,其中該上矽層在該二回合斜向植入期間接受摻雜物的一區域是用該等多數溝槽的第一深度、該遮罩的厚度、以及該植入角度來界定。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/388,790 US7446374B2 (en) | 2006-03-24 | 2006-03-24 | High density trench FET with integrated Schottky diode and method of manufacture |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200742079A TW200742079A (en) | 2007-11-01 |
TWI443826B true TWI443826B (zh) | 2014-07-01 |
Family
ID=38532425
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW096109324A TWI443826B (zh) | 2006-03-24 | 2007-03-19 | 具有整合蕭特基二極體(Schottky diode)之高密度溝槽場效電晶體及其製造方法 |
Country Status (8)
Country | Link |
---|---|
US (2) | US7446374B2 (zh) |
JP (1) | JP2009531836A (zh) |
KR (1) | KR101361239B1 (zh) |
CN (1) | CN101454882B (zh) |
AT (1) | AT505583A2 (zh) |
DE (1) | DE112007000700B4 (zh) |
TW (1) | TWI443826B (zh) |
WO (1) | WO2007112187A2 (zh) |
Families Citing this family (82)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6838722B2 (en) * | 2002-03-22 | 2005-01-04 | Siliconix Incorporated | Structures of and methods of fabricating trench-gated MIS devices |
US8362547B2 (en) * | 2005-02-11 | 2013-01-29 | Alpha & Omega Semiconductor Limited | MOS device with Schottky barrier controlling layer |
US8093651B2 (en) * | 2005-02-11 | 2012-01-10 | Alpha & Omega Semiconductor Limited | MOS device with integrated schottky diode in active region contact trench |
US7952139B2 (en) * | 2005-02-11 | 2011-05-31 | Alpha & Omega Semiconductor Ltd. | Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout |
US7285822B2 (en) * | 2005-02-11 | 2007-10-23 | Alpha & Omega Semiconductor, Inc. | Power MOS device |
US8283723B2 (en) * | 2005-02-11 | 2012-10-09 | Alpha & Omega Semiconductor Limited | MOS device with low injection diode |
US7948029B2 (en) | 2005-02-11 | 2011-05-24 | Alpha And Omega Semiconductor Incorporated | MOS device with varying trench depth |
US7446374B2 (en) | 2006-03-24 | 2008-11-04 | Fairchild Semiconductor Corporation | High density trench FET with integrated Schottky diode and method of manufacture |
JP5222466B2 (ja) | 2006-08-09 | 2013-06-26 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US8008716B2 (en) * | 2006-09-17 | 2011-08-30 | Alpha & Omega Semiconductor, Ltd | Inverted-trench grounded-source FET structure with trenched source body short electrode |
US7544571B2 (en) * | 2006-09-20 | 2009-06-09 | Fairchild Semiconductor Corporation | Trench gate FET with self-aligned features |
US20080150013A1 (en) * | 2006-12-22 | 2008-06-26 | Alpha & Omega Semiconductor, Ltd | Split gate formation with high density plasma (HDP) oxide layer as inter-polysilicon insulation layer |
US8686493B2 (en) * | 2007-10-04 | 2014-04-01 | Fairchild Semiconductor Corporation | High density FET with integrated Schottky |
US7932556B2 (en) * | 2007-12-14 | 2011-04-26 | Fairchild Semiconductor Corporation | Structure and method for forming power devices with high aspect ratio contact openings |
US7772668B2 (en) * | 2007-12-26 | 2010-08-10 | Fairchild Semiconductor Corporation | Shielded gate trench FET with multiple channels |
US7965126B2 (en) | 2008-02-12 | 2011-06-21 | Transphorm Inc. | Bridge circuits and their components |
US9882049B2 (en) * | 2014-10-06 | 2018-01-30 | Alpha And Omega Semiconductor Incorporated | Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method |
US7977768B2 (en) * | 2008-04-01 | 2011-07-12 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
JP5530602B2 (ja) * | 2008-04-09 | 2014-06-25 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US9093521B2 (en) * | 2008-06-30 | 2015-07-28 | Alpha And Omega Semiconductor Incorporated | Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout |
US7936009B2 (en) * | 2008-07-09 | 2011-05-03 | Fairchild Semiconductor Corporation | Shielded gate trench FET with an inter-electrode dielectric having a low-k dielectric therein |
US8304829B2 (en) | 2008-12-08 | 2012-11-06 | Fairchild Semiconductor Corporation | Trench-based power semiconductor devices with increased breakdown voltage characteristics |
US8174067B2 (en) | 2008-12-08 | 2012-05-08 | Fairchild Semiconductor Corporation | Trench-based power semiconductor devices with increased breakdown voltage characteristics |
US8362552B2 (en) * | 2008-12-23 | 2013-01-29 | Alpha And Omega Semiconductor Incorporated | MOSFET device with reduced breakdown voltage |
US8227855B2 (en) | 2009-02-09 | 2012-07-24 | Fairchild Semiconductor Corporation | Semiconductor devices with stable and controlled avalanche characteristics and methods of fabricating the same |
US8148749B2 (en) | 2009-02-19 | 2012-04-03 | Fairchild Semiconductor Corporation | Trench-shielded semiconductor device |
TWI388059B (zh) * | 2009-05-01 | 2013-03-01 | Niko Semiconductor Co Ltd | The structure of gold-oxygen semiconductor and its manufacturing method |
US8049276B2 (en) | 2009-06-12 | 2011-11-01 | Fairchild Semiconductor Corporation | Reduced process sensitivity of electrode-semiconductor rectifiers |
CN101609801B (zh) * | 2009-07-03 | 2011-05-25 | 英属维京群岛商节能元件股份有限公司 | 沟槽式肖特基二极管及其制作方法 |
US7952141B2 (en) | 2009-07-24 | 2011-05-31 | Fairchild Semiconductor Corporation | Shield contacts in a shielded gate MOSFET |
US8252647B2 (en) * | 2009-08-31 | 2012-08-28 | Alpha & Omega Semiconductor Incorporated | Fabrication of trench DMOS device having thick bottom shielding oxide |
TWI380448B (en) * | 2009-09-16 | 2012-12-21 | Anpec Electronics Corp | Overlapping trench gate semiconductor device and manufacturing method thereof |
US9425305B2 (en) | 2009-10-20 | 2016-08-23 | Vishay-Siliconix | Structures of and methods of fabricating split gate MIS devices |
US20120220092A1 (en) * | 2009-10-21 | 2012-08-30 | Vishay-Siliconix | Method of forming a hybrid split gate simiconductor |
US9419129B2 (en) * | 2009-10-21 | 2016-08-16 | Vishay-Siliconix | Split gate semiconductor device with curved gate oxide profile |
US8247296B2 (en) | 2009-12-09 | 2012-08-21 | Semiconductor Components Industries, Llc | Method of forming an insulated gate field effect transistor device having a shield electrode structure |
JP5636254B2 (ja) | 2009-12-15 | 2014-12-03 | 株式会社東芝 | 半導体装置 |
JP5736394B2 (ja) | 2010-03-02 | 2015-06-17 | ヴィシェイ−シリコニックス | 半導体装置の構造及びその製造方法 |
CN101882617B (zh) * | 2010-06-12 | 2011-11-30 | 中国科学院上海微***与信息技术研究所 | 肖特基二极管、半导体存储器及其制造工艺 |
US8252648B2 (en) * | 2010-06-29 | 2012-08-28 | Alpha & Omega Semiconductor, Inc. | Power MOSFET device with self-aligned integrated Schottky and its manufacturing method |
JP5740108B2 (ja) * | 2010-07-16 | 2015-06-24 | 株式会社東芝 | 半導体装置 |
CN102347359B (zh) * | 2010-07-29 | 2014-03-26 | 万国半导体股份有限公司 | 一种功率mosfet器件及其制造方法 |
JP5674530B2 (ja) * | 2010-09-10 | 2015-02-25 | ルネサスエレクトロニクス株式会社 | 半導体装置の制御装置 |
US8461646B2 (en) * | 2011-02-04 | 2013-06-11 | Vishay General Semiconductor Llc | Trench MOS barrier schottky (TMBS) having multiple floating gates |
US8587059B2 (en) * | 2011-04-22 | 2013-11-19 | Infineon Technologies Austria Ag | Transistor arrangement with a MOSFET |
US8502302B2 (en) * | 2011-05-02 | 2013-08-06 | Alpha And Omega Semiconductor Incorporated | Integrating Schottky diode into power MOSFET |
JP2014518017A (ja) | 2011-05-18 | 2014-07-24 | ビシャイ‐シリコニックス | 半導体デバイス |
JP6290526B2 (ja) | 2011-08-24 | 2018-03-07 | ローム株式会社 | 半導体装置およびその製造方法 |
CN104380441A (zh) * | 2012-04-30 | 2015-02-25 | 维西埃-硅化物公司 | 集成电路设计 |
US8921931B2 (en) | 2012-06-04 | 2014-12-30 | Infineon Technologies Austria Ag | Semiconductor device with trench structures including a recombination structure and a fill structure |
KR101828495B1 (ko) | 2013-03-27 | 2018-02-12 | 삼성전자주식회사 | 평탄한 소스 전극을 가진 반도체 소자 |
KR101934893B1 (ko) | 2013-03-27 | 2019-01-03 | 삼성전자 주식회사 | 그루브 소스 컨택 영역을 가진 반도체 소자의 제조 방법 |
KR20150035198A (ko) * | 2013-09-27 | 2015-04-06 | 삼성전자주식회사 | 반도체 소자 및 그 제조방법 |
KR102046663B1 (ko) * | 2013-11-04 | 2019-11-20 | 매그나칩 반도체 유한회사 | 반도체 소자 및 그 제조방법 |
DE112014003712T5 (de) * | 2013-12-16 | 2016-04-28 | Fuji Electric Co., Ltd. | Halbleitervorrichtung und Verfahren zum Herstellen einer Halbleitervorrichtung |
CN115483211A (zh) | 2014-08-19 | 2022-12-16 | 维西埃-硅化物公司 | 电子电路 |
US9755043B2 (en) * | 2014-12-04 | 2017-09-05 | Shuk-Wa FUNG | Trench gate power semiconductor field effect transistor |
US10008384B2 (en) | 2015-06-25 | 2018-06-26 | Varian Semiconductor Equipment Associates, Inc. | Techniques to engineer nanoscale patterned features using ions |
JP6217708B2 (ja) * | 2015-07-30 | 2017-10-25 | トヨタ自動車株式会社 | 半導体装置とその製造方法 |
US9780088B1 (en) | 2016-03-31 | 2017-10-03 | International Business Machines Corporation | Co-fabrication of vertical diodes and fin field effect transistors on the same substrate |
CN105957884A (zh) * | 2016-06-24 | 2016-09-21 | 上海格瑞宝电子有限公司 | 一种分栅栅极沟槽结构和沟槽肖特基二极管及其制备方法 |
KR101836258B1 (ko) | 2016-07-05 | 2018-03-08 | 현대자동차 주식회사 | 반도체 소자 및 그 제조 방법 |
US10304971B2 (en) | 2016-07-16 | 2019-05-28 | Champion Microelectronic Corp. | High speed Schottky rectifier |
CN109643656A (zh) * | 2016-09-02 | 2019-04-16 | 新电元工业株式会社 | Mosfet以及电力转换电路 |
US10770599B2 (en) | 2016-09-03 | 2020-09-08 | Champion Microelectronic Corp. | Deep trench MOS barrier junction all around rectifier and MOSFET |
US10211333B2 (en) * | 2017-04-26 | 2019-02-19 | Alpha And Omega Semiconductor (Cayman) Ltd. | Scalable SGT structure with improved FOM |
JP2019046991A (ja) * | 2017-09-04 | 2019-03-22 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US11081554B2 (en) * | 2017-10-12 | 2021-08-03 | Semiconductor Components Industries, Llc | Insulated gate semiconductor device having trench termination structure and method |
CN108231900A (zh) * | 2017-12-28 | 2018-06-29 | 中山汉臣电子科技有限公司 | 一种功率半导体器件及其制备方法 |
JP6923457B2 (ja) * | 2018-01-19 | 2021-08-18 | 株式会社日立製作所 | 炭化ケイ素半導体装置およびその製造方法、電力変換装置、自動車並びに鉄道車両 |
DE102018103849B4 (de) * | 2018-02-21 | 2022-09-01 | Infineon Technologies Ag | Siliziumcarbid-Halbleiterbauelement mit einer in einer Grabenstruktur ausgebildeten Gateelektrode |
CN108346701B (zh) * | 2018-04-12 | 2020-05-26 | 电子科技大学 | 一种屏蔽栅功率dmos器件 |
US11031472B2 (en) | 2018-12-28 | 2021-06-08 | General Electric Company | Systems and methods for integrated diode field-effect transistor semiconductor devices |
US11217541B2 (en) | 2019-05-08 | 2022-01-04 | Vishay-Siliconix, LLC | Transistors with electrically active chip seal ring and methods of manufacture |
CN110492761A (zh) * | 2019-07-12 | 2019-11-22 | 西安科锐盛创新科技有限公司 | 一种整流电路***、整流天线和微波无线能量传输*** |
JP7237772B2 (ja) * | 2019-08-20 | 2023-03-13 | 株式会社東芝 | 半導体装置 |
US11183514B2 (en) | 2019-09-05 | 2021-11-23 | Globalfoundries U.S. Inc. | Vertically stacked field effect transistors |
US11218144B2 (en) | 2019-09-12 | 2022-01-04 | Vishay-Siliconix, LLC | Semiconductor device with multiple independent gates |
US11114558B2 (en) * | 2019-10-18 | 2021-09-07 | Nami MOS CO., LTD. | Shielded gate trench MOSFET integrated with super barrier rectifier |
US11869967B2 (en) | 2021-08-12 | 2024-01-09 | Alpha And Omega Semiconductor International Lp | Bottom source trench MOSFET with shield electrode |
CN114664926A (zh) * | 2022-03-30 | 2022-06-24 | 电子科技大学 | 一种功率半导体器件结构 |
DE102022110998A1 (de) | 2022-05-04 | 2023-11-09 | Infineon Technologies Ag | Halbleitervorrichtung und verfahren zum herstellen einer halbleitervorrichtung |
Family Cites Families (318)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3257626A (en) * | 1962-12-31 | 1966-06-21 | Ibm | Semiconductor laser structures |
US3404295A (en) | 1964-11-30 | 1968-10-01 | Motorola Inc | High frequency and voltage transistor with added region for punch-through protection |
US3412297A (en) | 1965-12-16 | 1968-11-19 | United Aircraft Corp | Mos field-effect transistor with a onemicron vertical channel |
US3497777A (en) | 1967-06-13 | 1970-02-24 | Stanislas Teszner | Multichannel field-effect semi-conductor device |
US3564356A (en) | 1968-10-24 | 1971-02-16 | Tektronix Inc | High voltage integrated circuit transistor |
US3660697A (en) * | 1970-02-16 | 1972-05-02 | Bell Telephone Labor Inc | Monolithic semiconductor apparatus adapted for sequential charge transfer |
US4003072A (en) | 1972-04-20 | 1977-01-11 | Sony Corporation | Semiconductor device with high voltage breakdown resistance |
US4337474A (en) | 1978-08-31 | 1982-06-29 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
US4638344A (en) | 1979-10-09 | 1987-01-20 | Cardwell Jr Walter T | Junction field-effect transistor controlled by merged depletion regions |
US4698653A (en) | 1979-10-09 | 1987-10-06 | Cardwell Jr Walter T | Semiconductor devices controlled by depletion regions |
US4338616A (en) | 1980-02-19 | 1982-07-06 | Xerox Corporation | Self-aligned Schottky metal semi-conductor field effect transistor with buried source and drain |
US4868624A (en) | 1980-05-09 | 1989-09-19 | Regents Of The University Of Minnesota | Channel collector transistor |
US4300150A (en) | 1980-06-16 | 1981-11-10 | North American Philips Corporation | Lateral double-diffused MOS transistor device |
US4326332A (en) | 1980-07-28 | 1982-04-27 | International Business Machines Corp. | Method of making a high density V-MOS memory array |
DE3070786D1 (en) * | 1980-11-12 | 1985-07-25 | Ibm Deutschland | Electrically switchable read-only memory |
US4324038A (en) * | 1980-11-24 | 1982-04-13 | Bell Telephone Laboratories, Incorporated | Method of fabricating MOS field effect transistors |
GB2089119A (en) | 1980-12-10 | 1982-06-16 | Philips Electronic Associated | High voltage semiconductor devices |
US4974059A (en) | 1982-12-21 | 1990-11-27 | International Rectifier Corporation | Semiconductor high-power mosfet device |
JPS6016420A (ja) | 1983-07-08 | 1985-01-28 | Mitsubishi Electric Corp | 選択的エピタキシヤル成長方法 |
US4639761A (en) | 1983-12-16 | 1987-01-27 | North American Philips Corporation | Combined bipolar-field effect transistor resurf devices |
US4568958A (en) * | 1984-01-03 | 1986-02-04 | General Electric Company | Inversion-mode insulated-gate gallium arsenide field-effect transistors |
FR2566179B1 (fr) | 1984-06-14 | 1986-08-22 | Commissariat Energie Atomique | Procede d'autopositionnement d'un oxyde de champ localise par rapport a une tranchee d'isolement |
US5208657A (en) | 1984-08-31 | 1993-05-04 | Texas Instruments Incorporated | DRAM Cell with trench capacitor and vertical channel in substrate |
US4824793A (en) * | 1984-09-27 | 1989-04-25 | Texas Instruments Incorporated | Method of making DRAM cell with trench capacitor |
US4694313A (en) * | 1985-02-19 | 1987-09-15 | Harris Corporation | Conductivity modulated semiconductor structure |
US4673962A (en) * | 1985-03-21 | 1987-06-16 | Texas Instruments Incorporated | Vertical DRAM cell and method |
US4774556A (en) | 1985-07-25 | 1988-09-27 | Nippondenso Co., Ltd. | Non-volatile semiconductor memory device |
US4956308A (en) | 1987-01-20 | 1990-09-11 | Itt Corporation | Method of making self-aligned field-effect transistor |
US5262336A (en) | 1986-03-21 | 1993-11-16 | Advanced Power Technology, Inc. | IGBT process to produce platinum lifetime control |
US5034785A (en) | 1986-03-24 | 1991-07-23 | Siliconix Incorporated | Planar vertical channel DMOS structure |
US4767722A (en) * | 1986-03-24 | 1988-08-30 | Siliconix Incorporated | Method for making planar vertical channel DMOS structures |
US4716126A (en) | 1986-06-05 | 1987-12-29 | Siliconix Incorporated | Fabrication of double diffused metal oxide semiconductor transistor |
JPH0693512B2 (ja) | 1986-06-17 | 1994-11-16 | 日産自動車株式会社 | 縦形mosfet |
US5607511A (en) | 1992-02-21 | 1997-03-04 | International Business Machines Corporation | Method and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers |
US4746630A (en) | 1986-09-17 | 1988-05-24 | Hewlett-Packard Company | Method for producing recessed field oxide with improved sidewall characteristics |
US4941026A (en) | 1986-12-05 | 1990-07-10 | General Electric Company | Semiconductor devices exhibiting minimum on-resistance |
JP2577330B2 (ja) | 1986-12-11 | 1997-01-29 | 新技術事業団 | 両面ゲ−ト静電誘導サイリスタの製造方法 |
JPS63171856A (ja) | 1987-01-09 | 1988-07-15 | Hitachi Ltd | 耐熱鋼 |
US5105243A (en) | 1987-02-26 | 1992-04-14 | Kabushiki Kaisha Toshiba | Conductivity-modulation metal oxide field effect transistor with single gate structure |
US4821095A (en) | 1987-03-12 | 1989-04-11 | General Electric Company | Insulated gate semiconductor device with extra short grid and method of fabrication |
US4745079A (en) * | 1987-03-30 | 1988-05-17 | Motorola, Inc. | Method for fabricating MOS transistors having gates with different work functions |
US4823176A (en) | 1987-04-03 | 1989-04-18 | General Electric Company | Vertical double diffused metal oxide semiconductor (VDMOS) device including high voltage junction exhibiting increased safe operating area |
US4801986A (en) | 1987-04-03 | 1989-01-31 | General Electric Company | Vertical double diffused metal oxide semiconductor VDMOS device with increased safe operating area and method |
US4811065A (en) | 1987-06-11 | 1989-03-07 | Siliconix Incorporated | Power DMOS transistor with high speed body diode |
US5164325A (en) | 1987-10-08 | 1992-11-17 | Siliconix Incorporated | Method of making a vertical current flow field effect transistor |
US4893160A (en) | 1987-11-13 | 1990-01-09 | Siliconix Incorporated | Method for increasing the performance of trenched devices and the resulting structure |
US4914058A (en) | 1987-12-29 | 1990-04-03 | Siliconix Incorporated | Grooved DMOS process with varying gate dielectric thickness |
US4967245A (en) | 1988-03-14 | 1990-10-30 | Siliconix Incorporated | Trench power MOSFET device |
US4903189A (en) | 1988-04-27 | 1990-02-20 | General Electric Company | Low noise, high frequency synchronous rectifier |
US5283201A (en) * | 1988-05-17 | 1994-02-01 | Advanced Power Technology, Inc. | High density power device fabrication process |
KR0173111B1 (ko) | 1988-06-02 | 1999-02-01 | 야마무라 가쯔미 | 트렌치 게이트 mos fet |
JPH0216763A (ja) | 1988-07-05 | 1990-01-19 | Toshiba Corp | 半導体装置の製造方法 |
US4853345A (en) | 1988-08-22 | 1989-08-01 | Delco Electronics Corporation | Process for manufacture of a vertical DMOS transistor |
US5268311A (en) | 1988-09-01 | 1993-12-07 | International Business Machines Corporation | Method for forming a thin dielectric layer on a substrate |
US5156989A (en) | 1988-11-08 | 1992-10-20 | Siliconix, Incorporated | Complementary, isolated DMOS IC technology |
US5346834A (en) * | 1988-11-21 | 1994-09-13 | Hitachi, Ltd. | Method for manufacturing a semiconductor device and a semiconductor memory device |
US5072266A (en) | 1988-12-27 | 1991-12-10 | Siliconix Incorporated | Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry |
US5111253A (en) | 1989-05-09 | 1992-05-05 | General Electric Company | Multicellular FET having a Schottky diode merged therewith |
US4992390A (en) | 1989-07-06 | 1991-02-12 | General Electric Company | Trench gate structure with thick bottom oxide |
EP0450082B1 (en) | 1989-08-31 | 2004-04-28 | Denso Corporation | Insulated gate bipolar transistor |
US4982260A (en) | 1989-10-02 | 1991-01-01 | General Electric Company | Power rectifier with trenches |
US5248894A (en) | 1989-10-03 | 1993-09-28 | Harris Corporation | Self-aligned channel stop for trench-isolated island |
US5242845A (en) | 1990-06-13 | 1993-09-07 | Kabushiki Kaisha Toshiba | Method of production of vertical MOS transistor |
US5126807A (en) | 1990-06-13 | 1992-06-30 | Kabushiki Kaisha Toshiba | Vertical MOS transistor and its production method |
US5071782A (en) | 1990-06-28 | 1991-12-10 | Texas Instruments Incorporated | Vertical memory cell array and method of fabrication |
US5079608A (en) | 1990-11-06 | 1992-01-07 | Harris Corporation | Power MOSFET transistor circuit with active clamp |
US5065273A (en) | 1990-12-04 | 1991-11-12 | International Business Machines Corporation | High capacity DRAM trench capacitor and methods of fabricating same |
US5684320A (en) * | 1991-01-09 | 1997-11-04 | Fujitsu Limited | Semiconductor device having transistor pair |
CN1019720B (zh) | 1991-03-19 | 1992-12-30 | 电子科技大学 | 半导体功率器件 |
US5164802A (en) | 1991-03-20 | 1992-11-17 | Harris Corporation | Power vdmosfet with schottky on lightly doped drain of lateral driver fet |
US5250450A (en) | 1991-04-08 | 1993-10-05 | Micron Technology, Inc. | Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance |
JP2603886B2 (ja) | 1991-05-09 | 1997-04-23 | 日本電信電話株式会社 | 薄層soi型絶縁ゲート型電界効果トランジスタの製造方法 |
KR940002400B1 (ko) | 1991-05-15 | 1994-03-24 | 금성일렉트론 주식회사 | 리세스 게이트를 갖는 반도체장치의 제조방법 |
US5219793A (en) | 1991-06-03 | 1993-06-15 | Motorola Inc. | Method for forming pitch independent contacts and a semiconductor device having the same |
KR940006702B1 (ko) | 1991-06-14 | 1994-07-25 | 금성일렉트론 주식회사 | 모스패트의 제조방법 |
JP2570022B2 (ja) | 1991-09-20 | 1997-01-08 | 株式会社日立製作所 | 定電圧ダイオード及びそれを用いた電力変換装置並びに定電圧ダイオードの製造方法 |
JPH0613627A (ja) | 1991-10-08 | 1994-01-21 | Semiconductor Energy Lab Co Ltd | 半導体装置およびその作製方法 |
US5366914A (en) | 1992-01-29 | 1994-11-22 | Nec Corporation | Vertical power MOSFET structure having reduced cell area |
US5283452A (en) * | 1992-02-14 | 1994-02-01 | Hughes Aircraft Company | Distributed cell monolithic mircowave integrated circuit (MMIC) field-effect transistor (FET) amplifier |
US5315142A (en) | 1992-03-23 | 1994-05-24 | International Business Machines Corporation | High performance trench EEPROM cell |
US5554862A (en) | 1992-03-31 | 1996-09-10 | Kabushiki Kaisha Toshiba | Power semiconductor device |
JPH06196723A (ja) | 1992-04-28 | 1994-07-15 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
US5640034A (en) | 1992-05-18 | 1997-06-17 | Texas Instruments Incorporated | Top-drain trench based resurf DMOS transistor structure |
US5233215A (en) | 1992-06-08 | 1993-08-03 | North Carolina State University At Raleigh | Silicon carbide power MOSFET with floating field ring and floating field plate |
US5430324A (en) | 1992-07-23 | 1995-07-04 | Siliconix, Incorporated | High voltage transistor having edge termination utilizing trench technology |
US5558313A (en) | 1992-07-24 | 1996-09-24 | Siliconix Inorporated | Trench field effect transistor with reduced punch-through susceptibility and low RDSon |
US5910669A (en) * | 1992-07-24 | 1999-06-08 | Siliconix Incorporated | Field effect Trench transistor having lightly doped epitaxial region on the surface portion thereof |
US5294824A (en) | 1992-07-31 | 1994-03-15 | Motorola, Inc. | High voltage transistor having reduced on-resistance |
GB9216599D0 (en) | 1992-08-05 | 1992-09-16 | Philips Electronics Uk Ltd | A semiconductor device comprising a vertical insulated gate field effect device and a method of manufacturing such a device |
US5300447A (en) | 1992-09-29 | 1994-04-05 | Texas Instruments Incorporated | Method of manufacturing a minimum scaled transistor |
JPH06163907A (ja) | 1992-11-20 | 1994-06-10 | Hitachi Ltd | 電圧駆動型半導体装置 |
US5275965A (en) | 1992-11-25 | 1994-01-04 | Micron Semiconductor, Inc. | Trench isolation using gated sidewalls |
US5326711A (en) | 1993-01-04 | 1994-07-05 | Texas Instruments Incorporated | High performance high voltage vertical transistor and method of fabrication |
DE4300806C1 (de) | 1993-01-14 | 1993-12-23 | Siemens Ag | Verfahren zur Herstellung von vertikalen MOS-Transistoren |
US5418376A (en) | 1993-03-02 | 1995-05-23 | Toyo Denki Seizo Kabushiki Kaisha | Static induction semiconductor device with a distributed main electrode structure and static induction semiconductor device with a static induction main electrode shorted structure |
US5341011A (en) | 1993-03-15 | 1994-08-23 | Siliconix Incorporated | Short channel trenched DMOS transistor |
DE4309764C2 (de) | 1993-03-25 | 1997-01-30 | Siemens Ag | Leistungs-MOSFET |
GB9306895D0 (en) * | 1993-04-01 | 1993-05-26 | Philips Electronics Uk Ltd | A method of manufacturing a semiconductor device comprising an insulated gate field effect device |
KR960012585B1 (en) * | 1993-06-25 | 1996-09-23 | Samsung Electronics Co Ltd | Transistor structure and the method for manufacturing the same |
US5349224A (en) * | 1993-06-30 | 1994-09-20 | Purdue Research Foundation | Integrable MOS and IGBT devices having trench gate structure |
US5371396A (en) * | 1993-07-02 | 1994-12-06 | Thunderbird Technologies, Inc. | Field effect transistor having polycrystalline silicon gate junction |
US5365102A (en) | 1993-07-06 | 1994-11-15 | North Carolina State University | Schottky barrier rectifier with MOS trench |
BE1007283A3 (nl) | 1993-07-12 | 1995-05-09 | Philips Electronics Nv | Halfgeleiderinrichting met een most voorzien van een extended draingebied voor hoge spanningen. |
US5420061A (en) | 1993-08-13 | 1995-05-30 | Micron Semiconductor, Inc. | Method for improving latchup immunity in a dual-polysilicon gate process |
JPH07122749A (ja) | 1993-09-01 | 1995-05-12 | Toshiba Corp | 半導体装置及びその製造方法 |
JP3400846B2 (ja) | 1994-01-20 | 2003-04-28 | 三菱電機株式会社 | トレンチ構造を有する半導体装置およびその製造方法 |
US5429977A (en) | 1994-03-11 | 1995-07-04 | Industrial Technology Research Institute | Method for forming a vertical transistor with a stacked capacitor DRAM cell |
US5449925A (en) * | 1994-05-04 | 1995-09-12 | North Carolina State University | Voltage breakdown resistant monocrystalline silicon carbide semiconductor devices |
US5434435A (en) | 1994-05-04 | 1995-07-18 | North Carolina State University | Trench gate lateral MOSFET |
DE4417150C2 (de) | 1994-05-17 | 1996-03-14 | Siemens Ag | Verfahren zur Herstellung einer Anordnung mit selbstverstärkenden dynamischen MOS-Transistorspeicherzellen |
US5454435A (en) * | 1994-05-25 | 1995-10-03 | Reinhardt; Lisa | Device for facilitating insertion of a beach umbrella in sand |
US5405794A (en) | 1994-06-14 | 1995-04-11 | Philips Electronics North America Corporation | Method of producing VDMOS device of increased power density |
US5424231A (en) | 1994-08-09 | 1995-06-13 | United Microelectronics Corp. | Method for manufacturing a VDMOS transistor |
US5583368A (en) | 1994-08-11 | 1996-12-10 | International Business Machines Corporation | Stacked devices |
DE69525003T2 (de) | 1994-08-15 | 2003-10-09 | Siliconix Inc | Verfahren zum Herstellen eines DMOS-Transistors mit Grabenstruktur unter Verwendung von sieben Masken |
US5581100A (en) | 1994-08-30 | 1996-12-03 | International Rectifier Corporation | Trench depletion MOSFET |
US5508542A (en) * | 1994-10-28 | 1996-04-16 | International Business Machines Corporation | Porous silicon trench and capacitor structures |
JP3708998B2 (ja) * | 1994-11-04 | 2005-10-19 | シーメンス アクチエンゲゼルシヤフト | 電界効果により制御可能の半導体デバイスの製造方法 |
US5583065A (en) | 1994-11-23 | 1996-12-10 | Sony Corporation | Method of making a MOS semiconductor device |
US6008520A (en) | 1994-12-30 | 1999-12-28 | Siliconix Incorporated | Trench MOSFET with heavily doped delta layer to provide low on- resistance |
US5674766A (en) | 1994-12-30 | 1997-10-07 | Siliconix Incorporated | Method of making a trench MOSFET with multi-resistivity drain to provide low on-resistance by varying dopant concentration in epitaxial layer |
US5597765A (en) | 1995-01-10 | 1997-01-28 | Siliconix Incorporated | Method for making termination structure for power MOSFET |
JPH08204179A (ja) | 1995-01-26 | 1996-08-09 | Fuji Electric Co Ltd | 炭化ケイ素トレンチmosfet |
US5670803A (en) | 1995-02-08 | 1997-09-23 | International Business Machines Corporation | Three-dimensional SRAM trench structure and fabrication method therefor |
JP3325736B2 (ja) | 1995-02-09 | 2002-09-17 | 三菱電機株式会社 | 絶縁ゲート型半導体装置 |
EP0726603B1 (en) | 1995-02-10 | 1999-04-21 | SILICONIX Incorporated | Trenched field effect transistor with PN depletion barrier |
JP3291957B2 (ja) | 1995-02-17 | 2002-06-17 | 富士電機株式会社 | 縦型トレンチmisfetおよびその製造方法 |
US5595927A (en) | 1995-03-17 | 1997-01-21 | Taiwan Semiconductor Manufacturing Company Ltd. | Method for making self-aligned source/drain mask ROM memory cell using trench etched channel |
US5592005A (en) | 1995-03-31 | 1997-01-07 | Siliconix Incorporated | Punch-through field effect transistor |
US5554552A (en) * | 1995-04-03 | 1996-09-10 | Taiwan Semiconductor Manufacturing Company | PN junction floating gate EEPROM, flash EPROM device and method of manufacture thereof |
US5744372A (en) | 1995-04-12 | 1998-04-28 | National Semiconductor Corporation | Fabrication of complementary field-effect transistors each having multi-part channel |
JPH08306914A (ja) | 1995-04-27 | 1996-11-22 | Nippondenso Co Ltd | 半導体装置およびその製造方法 |
US5567634A (en) | 1995-05-01 | 1996-10-22 | National Semiconductor Corporation | Method of fabricating self-aligned contact trench DMOS transistors |
KR0143459B1 (ko) | 1995-05-22 | 1998-07-01 | 한민구 | 모오스 게이트형 전력 트랜지스터 |
US6049108A (en) | 1995-06-02 | 2000-04-11 | Siliconix Incorporated | Trench-gated MOSFET with bidirectional voltage clamping |
US6140678A (en) | 1995-06-02 | 2000-10-31 | Siliconix Incorporated | Trench-gated power MOSFET with protective diode |
US5648670A (en) | 1995-06-07 | 1997-07-15 | Sgs-Thomson Microelectronics, Inc. | Trench MOS-gated device with a minimum number of masks |
GB9512089D0 (en) | 1995-06-14 | 1995-08-09 | Evans Jonathan L | Semiconductor device fabrication |
US5689128A (en) * | 1995-08-21 | 1997-11-18 | Siliconix Incorporated | High density trenched DMOS transistor |
US5629543A (en) | 1995-08-21 | 1997-05-13 | Siliconix Incorporated | Trenched DMOS transistor with buried layer for reduced on-resistance and ruggedness |
US5847464A (en) | 1995-09-27 | 1998-12-08 | Sgs-Thomson Microelectronics, Inc. | Method for forming controlled voids in interlevel dielectric |
US5705409A (en) | 1995-09-28 | 1998-01-06 | Motorola Inc. | Method for forming trench transistor structure |
JPH09102602A (ja) * | 1995-10-05 | 1997-04-15 | Nippon Telegr & Teleph Corp <Ntt> | Mosfet |
US5616945A (en) * | 1995-10-13 | 1997-04-01 | Siliconix Incorporated | Multiple gated MOSFET for use in DC-DC converter |
US5692569A (en) * | 1995-10-17 | 1997-12-02 | Mustad, Incorporated | Horseshoe system |
US5949124A (en) | 1995-10-31 | 1999-09-07 | Motorola, Inc. | Edge termination structure |
US6037632A (en) | 1995-11-06 | 2000-03-14 | Kabushiki Kaisha Toshiba | Semiconductor device |
US5780343A (en) | 1995-12-20 | 1998-07-14 | National Semiconductor Corporation | Method of producing high quality silicon surface for selective epitaxial growth of silicon |
US5637898A (en) | 1995-12-22 | 1997-06-10 | North Carolina State University | Vertical field effect transistors having improved breakdown voltage capability and low on-state resistance |
GB2309336B (en) | 1996-01-22 | 2001-05-23 | Fuji Electric Co Ltd | Semiconductor device |
WO1997029518A1 (de) | 1996-02-05 | 1997-08-14 | Siemens Aktiengesellschaft | Durch feldeffekt steuerbares halbleiterbauelement |
US6084268A (en) | 1996-03-05 | 2000-07-04 | Semiconductor Components Industries, Llc | Power MOSFET device having low on-resistance and method |
US5821583A (en) | 1996-03-06 | 1998-10-13 | Siliconix Incorporated | Trenched DMOS transistor with lightly doped tub |
DE19611045C1 (de) | 1996-03-20 | 1997-05-22 | Siemens Ag | Durch Feldeffekt steuerbares Halbleiterbauelement |
DE69630944D1 (de) | 1996-03-29 | 2004-01-15 | St Microelectronics Srl | Hochspannungsfester MOS-Transistor und Verfahren zur Herstellung |
US5895951A (en) * | 1996-04-05 | 1999-04-20 | Megamos Corporation | MOSFET structure and fabrication process implemented by forming deep and narrow doping regions through doping trenches |
US5770878A (en) | 1996-04-10 | 1998-06-23 | Harris Corporation | Trench MOS gate device |
US5767004A (en) | 1996-04-22 | 1998-06-16 | Chartered Semiconductor Manufacturing, Ltd. | Method for forming a low impurity diffusion polysilicon layer |
US5818084A (en) | 1996-05-15 | 1998-10-06 | Siliconix Incorporated | Pseudo-Schottky diode |
DE69739206D1 (de) | 1996-07-19 | 2009-02-26 | Siliconix Inc | Hochdichte-graben-dmos-transistor mit grabenbodemimplantierung |
US5808340A (en) | 1996-09-18 | 1998-09-15 | Advanced Micro Devices, Inc. | Short channel self aligned VMOS field effect transistor |
DE19638438A1 (de) | 1996-09-19 | 1998-04-02 | Siemens Ag | Durch Feldeffekt steuerbares, vertikales Halbleiterbauelement |
JP2891205B2 (ja) | 1996-10-21 | 1999-05-17 | 日本電気株式会社 | 半導体集積回路の製造方法 |
JP3397057B2 (ja) | 1996-11-01 | 2003-04-14 | 日産自動車株式会社 | 半導体装置 |
US6207994B1 (en) | 1996-11-05 | 2001-03-27 | Power Integrations, Inc. | High-voltage transistor with multi-layer conduction region |
US6168983B1 (en) | 1996-11-05 | 2001-01-02 | Power Integrations, Inc. | Method of making a high-voltage transistor with multiple lateral conduction layers |
KR100233832B1 (ko) | 1996-12-14 | 1999-12-01 | 정선종 | 반도체 소자의 트랜지스터 및 그 제조방법 |
US6011298A (en) | 1996-12-31 | 2000-01-04 | Stmicroelectronics, Inc. | High voltage termination with buried field-shaping region |
JPH10256550A (ja) | 1997-01-09 | 1998-09-25 | Toshiba Corp | 半導体装置 |
KR100218260B1 (ko) | 1997-01-14 | 1999-09-01 | 김덕중 | 트랜치 게이트형 모스트랜지스터의 제조방법 |
SE9700141D0 (sv) | 1997-01-20 | 1997-01-20 | Abb Research Ltd | A schottky diode of SiC and a method for production thereof |
JP3938964B2 (ja) | 1997-02-10 | 2007-06-27 | 三菱電機株式会社 | 高耐圧半導体装置およびその製造方法 |
US5877528A (en) | 1997-03-03 | 1999-03-02 | Megamos Corporation | Structure to provide effective channel-stop in termination areas for trenched power transistors |
US6057558A (en) | 1997-03-05 | 2000-05-02 | Denson Corporation | Silicon carbide semiconductor device and manufacturing method thereof |
US5981354A (en) | 1997-03-12 | 1999-11-09 | Advanced Micro Devices, Inc. | Semiconductor fabrication employing a flowable oxide to enhance planarization in a shallow trench isolation process |
KR100225409B1 (ko) | 1997-03-27 | 1999-10-15 | 김덕중 | 트렌치 디-모오스 및 그의 제조 방법 |
US6163052A (en) | 1997-04-04 | 2000-12-19 | Advanced Micro Devices, Inc. | Trench-gated vertical combination JFET and MOSFET devices |
US6281547B1 (en) | 1997-05-08 | 2001-08-28 | Megamos Corporation | Power transistor cells provided with reliable trenched source contacts connected to narrower source manufactured without a source mask |
JPH113936A (ja) | 1997-06-13 | 1999-01-06 | Nec Corp | 半導体装置の製造方法 |
US6096608A (en) | 1997-06-30 | 2000-08-01 | Siliconix Incorporated | Bidirectional trench gated power mosfet with submerged body bus extending underneath gate trench |
US5907776A (en) | 1997-07-11 | 1999-05-25 | Magepower Semiconductor Corp. | Method of forming a semiconductor structure having reduced threshold voltage and high punch-through tolerance |
US6188093B1 (en) | 1997-09-02 | 2001-02-13 | Nikon Corporation | Photoelectric conversion devices and photoelectric conversion apparatus employing the same |
DE19740195C2 (de) | 1997-09-12 | 1999-12-02 | Siemens Ag | Halbleiterbauelement mit Metall-Halbleiterübergang mit niedrigem Sperrstrom |
DE19743342C2 (de) | 1997-09-30 | 2002-02-28 | Infineon Technologies Ag | Feldeffekttransistor hoher Packungsdichte und Verfahren zu seiner Herstellung |
KR100249505B1 (ko) | 1997-10-28 | 2000-03-15 | 정선종 | 수평형 이중 확산 전력 소자의 제조 방법 |
US6337499B1 (en) | 1997-11-03 | 2002-01-08 | Infineon Technologies Ag | Semiconductor component |
US5943581A (en) | 1997-11-05 | 1999-08-24 | Vanguard International Semiconductor Corporation | Method of fabricating a buried reservoir capacitor structure for high-density dynamic random access memory (DRAM) circuits |
GB9723468D0 (en) | 1997-11-07 | 1998-01-07 | Zetex Plc | Method of semiconductor device fabrication |
US6081009A (en) | 1997-11-10 | 2000-06-27 | Intersil Corporation | High voltage mosfet structure |
US6429481B1 (en) | 1997-11-14 | 2002-08-06 | Fairchild Semiconductor Corporation | Field effect transistor and method of its manufacture |
US6426260B1 (en) | 1997-12-02 | 2002-07-30 | Magepower Semiconductor Corp. | Switching speed improvement in DMO by implanting lightly doped region under gate |
US5949104A (en) | 1998-02-07 | 1999-09-07 | Xemod, Inc. | Source connection structure for lateral RF MOS devices |
JP3641547B2 (ja) | 1998-03-25 | 2005-04-20 | 株式会社豊田中央研究所 | 横型mos素子を含む半導体装置 |
US5897343A (en) | 1998-03-30 | 1999-04-27 | Motorola, Inc. | Method of making a power switching trench MOSFET having aligned source regions |
US5945724A (en) | 1998-04-09 | 1999-08-31 | Micron Technology, Inc. | Trench isolation region for semiconductor device |
US6150697A (en) | 1998-04-30 | 2000-11-21 | Denso Corporation | Semiconductor apparatus having high withstand voltage |
US6303969B1 (en) | 1998-05-01 | 2001-10-16 | Allen Tan | Schottky diode with dielectric trench |
US6063678A (en) | 1998-05-04 | 2000-05-16 | Xemod, Inc. | Fabrication of lateral RF MOS devices with enhanced RF properties |
DE19820223C1 (de) | 1998-05-06 | 1999-11-04 | Siemens Ag | Verfahren zum Herstellen einer Epitaxieschicht mit lateral veränderlicher Dotierung |
US6104054A (en) | 1998-05-13 | 2000-08-15 | Texas Instruments Incorporated | Space-efficient layout method to reduce the effect of substrate capacitance in dielectrically isolated process technologies |
US6015727A (en) | 1998-06-08 | 2000-01-18 | Wanlass; Frank M. | Damascene formation of borderless contact MOS transistors |
DE19828191C1 (de) | 1998-06-24 | 1999-07-29 | Siemens Ag | Lateral-Hochspannungstransistor |
KR100372103B1 (ko) | 1998-06-30 | 2003-03-31 | 주식회사 하이닉스반도체 | 반도체소자의소자분리방법 |
US6054365A (en) | 1998-07-13 | 2000-04-25 | International Rectifier Corp. | Process for filling deep trenches with polysilicon and oxide |
US6156611A (en) | 1998-07-20 | 2000-12-05 | Motorola, Inc. | Method of fabricating vertical FET with sidewall gate electrode |
DE69818289T2 (de) | 1998-07-23 | 2004-07-01 | Mitsubishi Denki K.K. | Verfahren zur Herstellung einer Halbleiteranordnung und dadurch erzeugbare Halbleiteranordnung |
JP4253374B2 (ja) | 1998-07-24 | 2009-04-08 | 千住金属工業株式会社 | プリント基板のはんだ付け方法および噴流はんだ槽 |
JP2000056281A (ja) | 1998-08-07 | 2000-02-25 | Mitsubishi Electric Corp | 光変調器とその製造方法 |
US6242770B1 (en) * | 1998-08-31 | 2001-06-05 | Gary Bela Bronner | Diode connected to a magnetic tunnel junction and self aligned with a metallic conductor and method for forming the same |
DE19839970C2 (de) | 1998-09-02 | 2000-11-02 | Siemens Ag | Randstruktur und Driftbereich für ein Halbleiterbauelement sowie Verfahren zu ihrer Herstellung |
US6316280B1 (en) | 1998-09-07 | 2001-11-13 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing semiconductor devices separated from a wafer |
JP3382163B2 (ja) | 1998-10-07 | 2003-03-04 | 株式会社東芝 | 電力用半導体装置 |
US7462910B1 (en) | 1998-10-14 | 2008-12-09 | International Rectifier Corporation | P-channel trench MOSFET structure |
DE19848828C2 (de) | 1998-10-22 | 2001-09-13 | Infineon Technologies Ag | Halbleiterbauelement mit kleiner Durchlaßspannung und hoher Sperrfähigkeit |
US5998833A (en) | 1998-10-26 | 1999-12-07 | North Carolina State University | Power semiconductor devices having improved high frequency switching and breakdown characteristics |
US6194741B1 (en) | 1998-11-03 | 2001-02-27 | International Rectifier Corp. | MOSgated trench type power semiconductor with silicon carbide substrate and increased gate breakdown voltage and reduced on-resistance |
US6096629A (en) | 1998-11-05 | 2000-08-01 | Taiwan Semiconductor Manufacturing Company | Uniform sidewall profile etch method for forming low contact leakage schottky diode contact |
JP3951522B2 (ja) | 1998-11-11 | 2007-08-01 | 富士電機デバイステクノロジー株式会社 | 超接合半導体素子 |
US6291856B1 (en) | 1998-11-12 | 2001-09-18 | Fuji Electric Co., Ltd. | Semiconductor device with alternating conductivity type layer and method of manufacturing the same |
JP3799888B2 (ja) | 1998-11-12 | 2006-07-19 | 富士電機デバイステクノロジー株式会社 | 超接合半導体素子およびその製造方法 |
US6156606A (en) | 1998-11-17 | 2000-12-05 | Siemens Aktiengesellschaft | Method of forming a trench capacitor using a rutile dielectric material |
JP2000156978A (ja) | 1998-11-17 | 2000-06-06 | Fuji Electric Co Ltd | ソフトスイッチング回路 |
US6084264A (en) | 1998-11-25 | 2000-07-04 | Siliconix Incorporated | Trench MOSFET having improved breakdown and on-resistance characteristics |
DE19854915C2 (de) | 1998-11-27 | 2002-09-05 | Infineon Technologies Ag | MOS-Feldeffekttransistor mit Hilfselektrode |
US6222229B1 (en) | 1999-02-18 | 2001-04-24 | Cree, Inc. | Self-aligned shield structure for realizing high frequency power MOSFET devices with improved reliability |
JP3751463B2 (ja) | 1999-03-23 | 2006-03-01 | 株式会社東芝 | 高耐圧半導体素子 |
DE19913375B4 (de) | 1999-03-24 | 2009-03-26 | Infineon Technologies Ag | Verfahren zur Herstellung einer MOS-Transistorstruktur |
JP3417336B2 (ja) | 1999-03-25 | 2003-06-16 | 関西日本電気株式会社 | 絶縁ゲート型半導体装置およびその製造方法 |
US6316806B1 (en) | 1999-03-31 | 2001-11-13 | Fairfield Semiconductor Corporation | Trench transistor with a self-aligned source |
US6188105B1 (en) | 1999-04-01 | 2001-02-13 | Intersil Corporation | High density MOS-gated power device and process for forming same |
TW425701B (en) | 1999-04-27 | 2001-03-11 | Taiwan Semiconductor Mfg | Manufacturing method of stack-type capacitor |
US6433385B1 (en) | 1999-05-19 | 2002-08-13 | Fairchild Semiconductor Corporation | MOS-gated power device having segmented trench and extended doping zone and process for forming same |
US6198127B1 (en) | 1999-05-19 | 2001-03-06 | Intersil Corporation | MOS-gated power device having extended trench and doping zone and process for forming same |
US6291298B1 (en) | 1999-05-25 | 2001-09-18 | Advanced Analogic Technologies, Inc. | Process of manufacturing Trench gate semiconductor device having gate oxide layer with multiple thicknesses |
US6373098B1 (en) | 1999-05-25 | 2002-04-16 | Fairchild Semiconductor Corporation | Trench-gated device having trench walls formed by selective epitaxial growth and process for forming device |
US6191447B1 (en) | 1999-05-28 | 2001-02-20 | Micro-Ohm Corporation | Power semiconductor devices that utilize tapered trench-based insulating regions to improve electric field profiles in highly doped drift region mesas and methods of forming same |
AU5458400A (en) | 1999-06-03 | 2000-12-28 | General Semiconductor, Inc. | High voltage power mosfet having low on-resistance |
EP1058318B1 (en) | 1999-06-03 | 2008-04-16 | STMicroelectronics S.r.l. | Power semiconductor device having an edge termination structure comprising a voltage divider |
JP3851744B2 (ja) | 1999-06-28 | 2006-11-29 | 株式会社東芝 | 半導体装置の製造方法 |
GB9917099D0 (en) | 1999-07-22 | 1999-09-22 | Koninkl Philips Electronics Nv | Cellular trench-gate field-effect transistors |
JP3971062B2 (ja) | 1999-07-29 | 2007-09-05 | 株式会社東芝 | 高耐圧半導体装置 |
TW411553B (en) | 1999-08-04 | 2000-11-11 | Mosel Vitelic Inc | Method for forming curved oxide on bottom of trench |
JP4774580B2 (ja) | 1999-08-23 | 2011-09-14 | 富士電機株式会社 | 超接合半導体素子 |
US6077733A (en) | 1999-09-03 | 2000-06-20 | Taiwan Semiconductor Manufacturing Company | Method of manufacturing self-aligned T-shaped gate through dual damascene |
US6566804B1 (en) | 1999-09-07 | 2003-05-20 | Motorola, Inc. | Field emission device and method of operation |
JP3507732B2 (ja) | 1999-09-30 | 2004-03-15 | 株式会社東芝 | 半導体装置 |
US6222233B1 (en) | 1999-10-04 | 2001-04-24 | Xemod, Inc. | Lateral RF MOS device with improved drain structure |
US6103619A (en) | 1999-10-08 | 2000-08-15 | United Microelectronics Corp. | Method of forming a dual damascene structure on a semiconductor wafer |
JP4450122B2 (ja) | 1999-11-17 | 2010-04-14 | 株式会社デンソー | 炭化珪素半導体装置 |
US6184092B1 (en) | 1999-11-23 | 2001-02-06 | Mosel Vitelic Inc. | Self-aligned contact for trench DMOS transistors |
US6461918B1 (en) | 1999-12-20 | 2002-10-08 | Fairchild Semiconductor Corporation | Power MOS device with improved gate charge performance |
US6285060B1 (en) | 1999-12-30 | 2001-09-04 | Siliconix Incorporated | Barrier accumulation-mode MOSFET |
US6346469B1 (en) | 2000-01-03 | 2002-02-12 | Motorola, Inc. | Semiconductor device and a process for forming the semiconductor device |
JP2001192174A (ja) | 2000-01-12 | 2001-07-17 | Occ Corp | 誘導巻取り装置 |
JP4765012B2 (ja) | 2000-02-09 | 2011-09-07 | 富士電機株式会社 | 半導体装置及びその製造方法 |
US6376878B1 (en) | 2000-02-11 | 2002-04-23 | Fairchild Semiconductor Corporation | MOS-gated devices with alternating zones of conductivity |
GB0003184D0 (en) | 2000-02-12 | 2000-04-05 | Koninkl Philips Electronics Nv | A semiconductor device and a method of fabricating material for a semiconductor device |
US6274420B1 (en) | 2000-02-23 | 2001-08-14 | Advanced Micro Devices, Inc. | Sti (shallow trench isolation) structures for minimizing leakage current through drain and source silicides |
US6271100B1 (en) | 2000-02-24 | 2001-08-07 | International Business Machines Corporation | Chemically enhanced anneal for removing trench stress resulting in improved bipolar yield |
JP2001244461A (ja) | 2000-02-28 | 2001-09-07 | Toyota Central Res & Dev Lab Inc | 縦型半導体装置 |
GB0005650D0 (en) | 2000-03-10 | 2000-05-03 | Koninkl Philips Electronics Nv | Field-effect semiconductor devices |
US6246090B1 (en) | 2000-03-14 | 2001-06-12 | Intersil Corporation | Power trench transistor device source region formation using silicon spacer |
JP3636345B2 (ja) | 2000-03-17 | 2005-04-06 | 富士電機デバイステクノロジー株式会社 | 半導体素子および半導体素子の製造方法 |
TW439176B (en) | 2000-03-17 | 2001-06-07 | United Microelectronics Corp | Manufacturing method of capacitors |
DE60140350D1 (de) | 2000-03-17 | 2009-12-17 | Gen Semiconductor Inc | DMOS-Transistorzelle mit einer Graben-Gateelektrode, sowie entsprechender DMOS-Transistor und Verfahren zu dessen Herstellung |
US6376315B1 (en) | 2000-03-31 | 2002-04-23 | General Semiconductor, Inc. | Method of forming a trench DMOS having reduced threshold voltage |
US6392290B1 (en) | 2000-04-07 | 2002-05-21 | Siliconix Incorporated | Vertical structure for semiconductor wafer-level chip scale packages |
JP4534303B2 (ja) | 2000-04-27 | 2010-09-01 | 富士電機システムズ株式会社 | 横型超接合半導体素子 |
JP4240752B2 (ja) | 2000-05-01 | 2009-03-18 | 富士電機デバイステクノロジー株式会社 | 半導体装置 |
US6509240B2 (en) | 2000-05-15 | 2003-01-21 | International Rectifier Corporation | Angle implant process for cellular deep trench sidewall doping |
DE10026924A1 (de) | 2000-05-30 | 2001-12-20 | Infineon Technologies Ag | Kompensationsbauelement |
US6479352B2 (en) | 2000-06-02 | 2002-11-12 | General Semiconductor, Inc. | Method of fabricating high voltage power MOSFET having low on-resistance |
JP3798951B2 (ja) | 2000-06-07 | 2006-07-19 | シャープ株式会社 | 回路内蔵受光素子、その製造方法および該受光素子を用いた光学装置 |
EP1170803A3 (en) | 2000-06-08 | 2002-10-09 | Siliconix Incorporated | Trench gate MOSFET and method of making the same |
US6472678B1 (en) | 2000-06-16 | 2002-10-29 | General Semiconductor, Inc. | Trench MOSFET with double-diffused body profile |
JP3833903B2 (ja) | 2000-07-11 | 2006-10-18 | 株式会社東芝 | 半導体装置の製造方法 |
US6555895B1 (en) | 2000-07-17 | 2003-04-29 | General Semiconductor, Inc. | Devices and methods for addressing optical edge effects in connection with etched trenches |
US6921939B2 (en) | 2000-07-20 | 2005-07-26 | Fairchild Semiconductor Corporation | Power MOSFET and method for forming same using a self-aligned body implant |
JP2002043571A (ja) | 2000-07-28 | 2002-02-08 | Nec Kansai Ltd | 半導体装置 |
US6437386B1 (en) | 2000-08-16 | 2002-08-20 | Fairchild Semiconductor Corporation | Method for creating thick oxide on the bottom surface of a trench structure in silicon |
US6472708B1 (en) | 2000-08-31 | 2002-10-29 | General Semiconductor, Inc. | Trench MOSFET with structure having low gate charge |
US6355501B1 (en) | 2000-09-21 | 2002-03-12 | International Business Machines Corporation | Three-dimensional chip stacking assembly |
FR2816113A1 (fr) | 2000-10-31 | 2002-05-03 | St Microelectronics Sa | Procede de realisation d'une zone dopee dans du carbure de silicium et application a une diode schottky |
EP1205980A1 (en) | 2000-11-07 | 2002-05-15 | Infineon Technologies AG | A method for forming a field effect transistor in a semiconductor substrate |
US6362112B1 (en) | 2000-11-08 | 2002-03-26 | Fabtech, Inc. | Single step etched moat |
US6608350B2 (en) | 2000-12-07 | 2003-08-19 | International Rectifier Corporation | High voltage vertical conduction superjunction semiconductor device |
US6677641B2 (en) * | 2001-10-17 | 2004-01-13 | Fairchild Semiconductor Corporation | Semiconductor structure with improved smaller forward voltage loss and higher blocking capability |
US6713813B2 (en) | 2001-01-30 | 2004-03-30 | Fairchild Semiconductor Corporation | Field effect transistor having a lateral depletion structure |
US7345342B2 (en) * | 2001-01-30 | 2008-03-18 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
KR100485297B1 (ko) | 2001-02-21 | 2005-04-27 | 미쓰비시덴키 가부시키가이샤 | 반도체 장치 및 그 제조 방법 |
TW543146B (en) | 2001-03-09 | 2003-07-21 | Fairchild Semiconductor | Ultra dense trench-gated power device with the reduced drain-source feedback capacitance and miller charge |
KR100393201B1 (ko) | 2001-04-16 | 2003-07-31 | 페어차일드코리아반도체 주식회사 | 낮은 온 저항과 높은 브레이크다운 전압을 갖는 고전압수평형 디모스 트랜지스터 |
DE10214160B4 (de) * | 2002-03-28 | 2014-10-09 | Infineon Technologies Ag | Halbleiteranordnung mit Schottky-Kontakt |
JP3312905B2 (ja) | 2001-06-25 | 2002-08-12 | 株式会社リコー | 画像形成装置 |
JP2003017701A (ja) * | 2001-07-04 | 2003-01-17 | Denso Corp | 半導体装置 |
US20030015756A1 (en) | 2001-07-23 | 2003-01-23 | Motorola, Inc. | Semiconductor structure for integrated control of an active subcircuit and process for fabrication |
US6875671B2 (en) | 2001-09-12 | 2005-04-05 | Reveo, Inc. | Method of fabricating vertical integrated circuits |
US6465304B1 (en) | 2001-10-04 | 2002-10-15 | General Semiconductor, Inc. | Method for fabricating a power semiconductor device having a floating island voltage sustaining layer |
WO2003103056A2 (en) * | 2002-05-31 | 2003-12-11 | Koninklijke Philips Electronics N.V. | Trench-gate semiconductor device,corresponding module and apparatus ,and method of operating the device |
US6878994B2 (en) * | 2002-08-22 | 2005-04-12 | International Rectifier Corporation | MOSgated device with accumulated channel region and Schottky contact |
JP4158453B2 (ja) | 2002-08-22 | 2008-10-01 | 株式会社デンソー | 半導体装置及びその製造方法 |
GB0229212D0 (en) * | 2002-12-14 | 2003-01-22 | Koninkl Philips Electronics Nv | Method of manufacture of a trench semiconductor device |
DE10259373B4 (de) | 2002-12-18 | 2012-03-22 | Infineon Technologies Ag | Überstromfeste Schottkydiode mit niedrigem Sperrstrom |
JP4166102B2 (ja) * | 2003-02-26 | 2008-10-15 | トヨタ自動車株式会社 | 高耐圧電界効果型半導体装置 |
GB0312512D0 (en) * | 2003-05-31 | 2003-07-09 | Koninkl Philips Electronics Nv | Termination structures for semiconductor devices and the manufacture thereof |
JP4799829B2 (ja) * | 2003-08-27 | 2011-10-26 | 三菱電機株式会社 | 絶縁ゲート型トランジスタ及びインバータ回路 |
WO2005065385A2 (en) * | 2003-12-30 | 2005-07-21 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
US7405452B2 (en) | 2004-02-02 | 2008-07-29 | Hamza Yilmaz | Semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics |
US6951112B2 (en) | 2004-02-10 | 2005-10-04 | General Electric Company | Methods and apparatus for assembling gas turbine engines |
US20050199918A1 (en) | 2004-03-15 | 2005-09-15 | Daniel Calafut | Optimized trench power MOSFET with integrated schottky diode |
JP2005285913A (ja) * | 2004-03-29 | 2005-10-13 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
JP4176734B2 (ja) * | 2004-05-14 | 2008-11-05 | 株式会社東芝 | トレンチmosfet |
US7501702B2 (en) * | 2004-06-24 | 2009-03-10 | Fairchild Semiconductor Corporation | Integrated transistor module and method of fabricating same |
DE102004057235B4 (de) | 2004-11-26 | 2007-12-27 | Infineon Technologies Ag | Vertikaler Trenchtransistor und Verfahren zu dessen Herstellung |
CN102867825B (zh) | 2005-04-06 | 2016-04-06 | 飞兆半导体公司 | 沟栅场效应晶体管结构及其形成方法 |
CN102738239A (zh) | 2005-05-26 | 2012-10-17 | 飞兆半导体公司 | 沟槽栅场效应晶体管及其制造方法 |
US7446374B2 (en) | 2006-03-24 | 2008-11-04 | Fairchild Semiconductor Corporation | High density trench FET with integrated Schottky diode and method of manufacture |
US7768075B2 (en) * | 2006-04-06 | 2010-08-03 | Fairchild Semiconductor Corporation | Semiconductor die packages using thin dies and metal substrates |
-
2006
- 2006-03-24 US US11/388,790 patent/US7446374B2/en active Active
-
2007
- 2007-03-08 CN CN2007800190574A patent/CN101454882B/zh active Active
- 2007-03-08 DE DE112007000700.1T patent/DE112007000700B4/de active Active
- 2007-03-08 WO PCT/US2007/063612 patent/WO2007112187A2/en active Application Filing
- 2007-03-08 AT AT0914007A patent/AT505583A2/de not_active Application Discontinuation
- 2007-03-08 KR KR1020087024224A patent/KR101361239B1/ko active IP Right Grant
- 2007-03-08 JP JP2009501633A patent/JP2009531836A/ja active Pending
- 2007-03-19 TW TW096109324A patent/TWI443826B/zh active
-
2008
- 2008-10-10 US US12/249,889 patent/US7713822B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
TW200742079A (en) | 2007-11-01 |
KR20090003306A (ko) | 2009-01-09 |
DE112007000700B4 (de) | 2018-01-11 |
US20070221952A1 (en) | 2007-09-27 |
WO2007112187A3 (en) | 2008-04-17 |
CN101454882B (zh) | 2011-08-31 |
CN101454882A (zh) | 2009-06-10 |
US7446374B2 (en) | 2008-11-04 |
KR101361239B1 (ko) | 2014-02-11 |
AT505583A2 (de) | 2009-02-15 |
US7713822B2 (en) | 2010-05-11 |
JP2009531836A (ja) | 2009-09-03 |
DE112007000700T5 (de) | 2009-01-29 |
WO2007112187A2 (en) | 2007-10-04 |
US20090035900A1 (en) | 2009-02-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI443826B (zh) | 具有整合蕭特基二極體(Schottky diode)之高密度溝槽場效電晶體及其製造方法 | |
US11888047B2 (en) | Lateral transistors and methods with low-voltage-drop shunt to body diode | |
TWI469321B (zh) | 具有整合蕭特基二極體之高密度場效電晶體 | |
CN209087847U (zh) | 半导体器件结构 | |
KR101296984B1 (ko) | 전하 균형 전계 효과 트랜지스터 | |
US8946002B2 (en) | Method of forming a semiconductor device having a patterned gate dielectric and structure therefor | |
CN111081779B (zh) | 一种屏蔽栅沟槽式mosfet及其制造方法 | |
TWI685899B (zh) | 金屬氧化物半導體閘極式裝置之單元佈線及製造技術之強化 | |
US20090026533A1 (en) | Trench MOSFET with multiple P-bodies for ruggedness and on-resistance improvements | |
US11004839B1 (en) | Trench power MOSFET with integrated-schottky in non-active area | |
CN107863378B (zh) | 超结mos器件及其制造方法 | |
KR101096579B1 (ko) | 전력용 반도체 소자 및 그의 제조 방법 |