WO2007112187A2 - High density trench fet with integrated schottky diode and method of manufacture - Google Patents
High density trench fet with integrated schottky diode and method of manufacture Download PDFInfo
- Publication number
- WO2007112187A2 WO2007112187A2 PCT/US2007/063612 US2007063612W WO2007112187A2 WO 2007112187 A2 WO2007112187 A2 WO 2007112187A2 US 2007063612 W US2007063612 W US 2007063612W WO 2007112187 A2 WO2007112187 A2 WO 2007112187A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- silicon
- regions
- layer
- region
- trenches
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 52
- 238000004519 manufacturing process Methods 0.000 title description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 148
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 148
- 239000010703 silicon Substances 0.000 claims abstract description 148
- 210000000746 body region Anatomy 0.000 claims abstract description 121
- 239000002184 metal Substances 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000007943 implant Substances 0.000 claims description 18
- 230000004888 barrier function Effects 0.000 claims description 13
- 239000002019 doping agent Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- 230000001360 synchronised effect Effects 0.000 claims description 3
- 239000002210 silicon-based material Substances 0.000 claims 4
- 235000012054 meals Nutrition 0.000 claims 1
- 230000008569 process Effects 0.000 description 15
- 230000003071 parasitic effect Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 230000002441 reversible effect Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000003116 impacting effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000779 depleting effect Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
Definitions
- the present invention relates in general to semiconductor power device technology, and in particular to structures and methods for forming a monolithically integrated trench gate field effect transistor (FET) and Schottky diode.
- FET trench gate field effect transistor
- dc/dc converters In today's electronic devices it is common to find the use of multiple power supply ranges. For example, in some applications, central processing units are designed to operate with a different supply voltage at a particular time depending on the computing load. Consequently, dc/dc converters have proliferated in electronics to satisfy the wide ranging power supply needs of the circuitry. Common dc/dc converters utilize high efficiency switches typically implemented by power MOSFETs. The power switch is controlled to deliver regulated quanta of energy to the load using, for example, a pulse width modulated (PWM) methodology.
- PWM pulse width modulated
- FIG. 1 shows a circuit schematic for a conventional dc/dc converter.
- a PWM controller 100 drives the gate terminals of a pair of power MOSFETs Ql and Q2 to regulate the delivery of charge to the load.
- MOSFET switch Q2 is used in the circuit as a synchronous rectifier. In order to avoid shoot-through current, both switches must be off simultaneously before one of them is turned on. During this "dead time," the internal diode of each MOSFET switch, commonly referred to as body diode, can conduct current. Unfortunately the body diode has relatively high forward voltage and energy is wasted. To improve the conversion efficiency of the circuit, a Schottky diode 102 is often externally added in parallel with the MOSFET (Q2) body diode.
- Q2 MOSFET
- Schottky diode 102 effectively replaces the MOSFET body diode.
- the lower forward voltage of the Schottky diode results in improved power consumption.
- the Schottky diode was implemented external to the MOSFET switch package. More recently, some manufacturers have introduced products in which discrete Schottky diodes are co-packaged with discrete power MOSFET devices. There have also been monolithic implementations of power MOSFETs with Schottky diode. An example of a conventional monolithically integrated trench MOSFET and Schottky diode is shown in Fig. 2.
- a Schottky diode 210 is formed between two trenches 200-3 and 200-4 surrounded by trench MOSFET cells on either side.
- N-type substrate 202 forms the cathode terminal of Schottky diode 210 as well as the drain terminal of the trench MOSFET.
- Conductive layer 218 provides the diode anode terminal and also serves as the source interconnect layer for MOSFET cells.
- the gate electrode in trenches 200-1 , 200-2, 200-3, 200-4 and 200-5 are connected together in a third dimension and are therefore similarly driven.
- the trench MOSFET cells further include body regions 208 with source region 212 and heavy body regions 214 therein.
- the Schottky diodes in Fig. 2 are interspersed between trench MOSFET cells. As a result, the Schottky diodes consume a significant portion of the active area, resulting in lower current ratings or a large die size. There is therefore a need for a monolithically and densely integrated Schottky diode and trench gate FET with superior performance characteristics.
- a monolithically integrated trench FET and Schottky diode includes a pair of trenches terminating in a first silicon region of first conductivity type. Two body regions of a second conductivity type separated by a second silicon region of the first conductivity type are located between the pair of trenches. A source region of the first conductivity type is located over each body region. A contact opening extends between the pair of trenches to a depth below the source regions. An interconnect layer fills the contact opening so as to electrically contact the source regions and the second silicon region. Where the interconnect layer electrically contacts the second silicon region, a Schottky contact is formed.
- the first silicon region has a higher doping concentration that the second silicon region.
- each body region vertically extends between a corresponding source region and the first silicon region, and the interconnect layer electrically contacts the second silicon region at a depth along the bottom half of the body regions.
- each of the two body regions has a substantially uniform doping concentration.
- a heavy body region of the second conductivity type is formed between the pair of trenches such that the heavy body region electrically contacts each of the two body regions and the second silicon region.
- the two body regions, the source regions, and the heavy body region are self-aligned to the pair of trenches.
- the two body regions and the second silicon region have substantially the same depth.
- a monolithically integrated trench FET and Schottky diode is formed as follows. Two trenches are formed extending through an upper silicon layer and terminating within a lower silicon layer. The upper and lower silicon layers have a first conductivity type, and the upper silicon layer extends over the lower silicon layer. First and second silicon regions of a second conductivity type are formed in the upper silicon layer between the pair of trenches. A third silicon region of the first conductivity type is formed extending into the first and second silicon regions between the pair of trenches such that remaining lower portions of the first and second silicon regions form two body regions separated by a portion of the upper silicon layer.
- a silicon etch is performed to form a contact opening extending through the first silicon region such that outer portions of the first silicon region remain.
- the outer portions of the first silicon region form source regions.
- An interconnect layer is formed filling the contact opening so as to electrically contact the source regions and the portion of the upper silicon layer. Where the interconnect layer electrically contacts the second silicon region, a Schottky contact is formed.
- the lower silicon layer has a higher doping concentration that the upper silicon layer.
- the electrical contact between the interconnect layer and the portion of the upper silicon layer is made at a depth below the source regions.
- each of the first and second regions has a substantially uniform doping concentration.
- a heavy body region of the second conductivity type is formed between the pair of trenches.
- the heavy body region extends into the two body regions and into the portion of the upper silicon layer.
- the two body regions, the source regions, and the heavy body region are self-aligned to the pair of trenches.
- Fig. 1 is a circuit schematic for a conventional dc/dc converter using power MOSFETs with a Schottky diode;
- FIG. 2 shows a cross-sectional view of a conventional monolithically integrated trench MOSFET and Schottky diode
- FIG. 3 is an exemplary simplified isometric view of a portion of an array of stripe- shaped cells each having a trench MOSFET and a Schottky diode integrated therein, in accordance with an embodiment of the invention
- Fig. 4 shows a cross-section view along heavy body regions 326 in Fig. 3;
- FIG. 5 is a simplified cross section view showing an alternate implementation of the heavy body region to that shown in Figs 3 and 4, in accordance with an embodiment of the invention
- FIGs. 6A-6F are simplified cross section views illustrating an exemplary process sequence for forming the monolithically integrated trench MOSFET and Schottky diode shown in Fig. 3, according to an embodiment of the present invention.
- Figs. 7A-7C show simulated avalanche current flow lines for three different dimple depths in a monolithically integrated trench MOSFET and Schottky diode structure.
- a Schottky diode is optimally integrated with a trench MOSFET in a single cell repeated many times in an array of such cells. Minimal to no active area is sacrificed in integrating the Schottky diode, yet the total Schottky diode area is large enough to handle 100% of the diode forward conduction. The MOSFET body diode thus never turns on, eliminating reverse recovery losses. Further, because of Schottky diode's lower forward voltage drop compared to that of the MOSFET body diode, power losses are reduced.
- the Schottky diode is integrated with the MOSFET such that the Schottky contact is formed below the MOSFET source regions. This advantageously diverts the avalanche current away from the source regions toward the Schottky regions, preventing the parasitic bipolar transistor from turning on. The device ruggedness is thus improved.
- This feature of the invention also eliminates, for the most part, the need for heavy body regions typically required in each MOSFET cell of prior art structures to prevent the parasitic bipolar transistor from turning on. Instead, islands of heavy body regions are incorporated intermittently and far apart from one another merely to ensure good source metal to body region contact. In essence, the heavy body regions required in prior art trench MOSFETs are, for the most part, replaced with Schottky diode. Accordingly, no additional silicon area is allocated to the Schottky diode.
- Fig. 3 is an exemplary simplified isometric view of a portion of an array of stripe- shaped cells each having a trench MOSFET and a Schottky diode integrated therein, in accordance with an embodiment of the invention.
- a highly doped N-type (N+) region 302 overlies an N-type silicon substrate (not shown) which has an even higher doping concentration (N++) than N+ region 302.
- a plurality of trenches 304 extend to a predetermined depth within N+ region 302.
- a shield electrode 305 and an overlying gate electrode 308 are embedded in each trench 304.
- shield electrodes 305 and gate electrodes 308 comprise polysilicon.
- An inter-electrode dielectric 310 insulates the gate and shield electrodes from one another.
- Shield dielectric layer 312 lines lower sidewalls and bottom of each trench 304, and insulates shield electrodes 305 from surrounding N+ region 302.
- a gate dielectric 316 which is thinner than shield dielectric 312, lines the upper sidewalls of trenches 304.
- a dielectric cap 314 extends over each gate electrode 308.
- shield electrodes 305 are electrically connected to source regions along a third dimension, and thus are biased to the same potential as the source regions during operation. In other embodiments, shield electrodes 305 are electrically tied to gate electrodes 308 along a third dimension, or are allowed to float.
- Two P-type body regions 318 separated by a lightly doped N-type (N-) region 320 are located between every two adjacent trenches 304. Each body region 318 extends along one trench sidewall. In the various embodiments shown in the figures and described herein, body regions 318 and N- region 320 have substantially the same depth, however body regions 318 may be slightly shallower or deeper than N- region 320 and vice versa without any significant impact on the device operation.
- a highly doped N-type source region 322 is located directly above each body region 318. Source regions 322 vertically overlap gate electrode 308, and possess a rounded outer profile due to the presence of dimples 324 forming contact openings.
- Each dimple 324 extends below corresponding source regions 322 between every two adjacent trenches. As shown, source regions 322 and body regions 318 together form the rounded sidewalls of dimples 324, and N- regions 320 extend along the bottom of dimples 324.
- N+ region 302 is an N+ epitaxial layer
- N- regions 320 are portions of an N- epitaxial layer in which body regions 318 and source regions 322 are formed.
- a Schottky barrier metal 330 which is peeled back in Fig. 3 to expose the underlying regions, fills dimples 324 and extends over dielectric caps 314. Schottky barrier metal 330 electrically contacts N- regions 320 along the bottom of dimples 324, thus forming a Schottky contact. Schottky barrier metal 330 also serves as the top-side source interconnect, electrically contacting source regions 322 and heavy body regions 326.
- the depletion regions formed at each body/N- junction advantageously merge in N- region 320 thus fully depleting N- region 320 beneath the
- Islands of heavy body regions 326 are formed intermittently along the cell stripes, as shown. Heavy body regions 326 extend through N- regions 320. This is more clearly shown in Fig. 4 which is a cross-section view through heavy body regions 326 of the structure in Fig. 3. The cross section view in Fig. 4 is, for the most part, similar to the cross section view along the face of the isometric view in Fig. 3 except that in Fig. 4 the two source regions between every two adjacent trenches are replaced with one contiguous heavy body region 326 extending through N- regions 320. Heavy body regions 326 provide ohmic contact between source metal 330 and body regions 318. Because heavy body regions 326 extend through N- regions 320, no Schottky diode is formed in these regions. No MOSFET current flows in these regions either, because of the absence of source regions.
- Fig. 5 is a simplified cross section view showing an alternate implementation of the heavy body region to that in Figs. 3 and 4, in accordance with another embodiment of the invention.
- heavy body regions 526 extend only along a bottom portion of each dimple 524 such that source regions 522 are kept intact. Thus, MOSFET current does flow in these regions, but heavy body regions 526 prevent Schottky barrier metal 430 from contacting N- regions 310 and thus no Schottky diode is formed in these regions.
- the intermittent placing of heavy body regions 326 differs from conventional implementations where heavy body regions extend along the entire length of the cell stripes between two adjacent source regions as in the prior art Fig. 2 structure.
- the placement frequency of heavy body regions 326 along the stripes is dictated by the device switching requirements. For faster switching devices, heavy body regions are placed more frequently along the stripes. For these devices, additional silicon area may need to be allocated to Schottky diode (e.g., by increasing the cell pitch). For slower switching devices, fewer heavy body regions are required along the stripes. For these devices, placing a heavy body region at each end of a stripe may suffice, thus maximizing the Schottky diode area.
- Figs. 6A-6F are simplified cross section views illustrating an exemplary process sequence for forming the integrated MOSFET-Schottky structure in Fig. 3, according to an embodiment of the present invention.
- two epitaxial layers 602 and 620 overlying a silicon substrate are formed using conventional techniques.
- Epitaxial layer 620 which is a lightly doped N-type layer (N-) extends over epitaxial layer 620 which is a highly doped N-type layer (N+).
- a hard mask e.g., comprising oxide
- openings 606, which define the trench width are about 0.3 ⁇ m each, and the width of each hard mask island 601 is in the range of 0.4-0.8 ⁇ m. These dimensions define the cell pitch within which the MOSFET and Schottky diode are formed. Factors impacting these dimensions include the capabilities of the photolithographic equipment and the design and performance goals.
- trenches 603 terminating within N- epi 620 are formed by etching silicon through openings 606 using conventional silicon etch techniques.
- trenches 603 have a depth of about 1 ⁇ m.
- a conventional selective epitaxial growth (SEG) process is then used to grow highly doped P-type (P+) silicon regions 618 A within each trench 603.
- P+ silicon region 618 A has a doping concentration of about 5xlO 17 cm "3 .
- a thin layer of high- quality silicon lining the sidewalls and bottom of trenches 608 is formed prior to forming P+ regions 618. The thin silicon layer serves as an undamaged silicon surface suitable for growth of the P+ silicon.
- a diffusion process is performed to diffuse the p-type dopants into P+ region 618 A into N- epi 620.
- Out-diffused P+ regions 618B extending laterally under hard mask islands 601 and downward into N- epi 620 are thus formed.
- Multiple thermal cycles may be carried out to achieve the desired out-diffusion.
- the dotted lines in Fig. 6C show the outline of trenches 603. This diffusion process, as well as other thermal cycles in the process, causes N+ epi 602 to diffuse upward. These upward diffusions of N+ epi 602 need to be accounted for in selecting the thickness of N- epi 620.
- trenches 604 are formed using hard mask islands 601 , using hard mask islands 601 , a deep trench etch process is performed to form trenches 604 extending through P+ regions 618B and N- epi 620, terminating in N+ epi 602. hi one embodiment, trenches 604 have a depth of about 2 ⁇ m. The trench etch process cuts through and removes a central portion of each P+ silicon region 618B, leaving vertically outer P+ strips 618C extending along trench sidewalls.
- P+ strips 618C are formed using a two- pass angled implant instead of the SEG technique depicted by Figs. 6B-6D, as described next.
- Fig. 6B after forming trenches 603 through mask openings 606, P-type dopants such as boron are implanted into opposing trench sidewalls using conventional two-pass angled implant techniques.
- Hard mask islands 604 serve as blocking structures during the implantation process to prevent the implant ions from entering the mesa regions and to confine the location of the implanted ions to the desired regions in N- epi 620. To arrive at the structure shown in Fig.
- a second trench etch is carried out to extend the depth of trenches 603 into N+ epi 602.
- only one trench etch (rather than two) is performed as follows.
- a trench etch is carried out to form trenches extending into N+ epi 602 to about the same depth as trenches 604 in Fig. 6D.
- a two-pass angled implant is then carried out to implant P-type dopants into opposing trench sidewalls. The implant angle and the thickness of hard mask islands 601 are adjusted to define upper trench sidewall regions that are to receive the implant ions.
- a shielded gate structure is formed in trenches 604 using known techniques.
- a shield dielectric 612 lining lower sidewalls and bottom of trenches 604 is formed.
- Shield electrodes 605 are then formed filling a lower portion of trenches 604.
- An inter-electrode dielectric layer 610 is then formed over shield electrode 605.
- a gate dielectric 616 lining upper trench sidewalls is then formed.
- gate dielectric 616 is formed in an earlier stage of the process.
- Recessed gate electrodes 608 are formed filling an upper portion of trenches 604.
- Dielectric cap regions 614 extend over gate electrodes 608 and fill the remainder of trenches 604.
- N-type dopants are implanted into all exposed silicon regions followed by a drive in process, thereby forming N+ regions 622A.
- No mask is used in the active region in forming N+ regions 622A.
- the various thermal cycles associated with forming the shielded gate structure and the N+ regions 622 A cause P-type regions 618C to out-diffuse thereby forming wider and taller body regions 618D.
- these thermal cycles also cause N+ epi 602 to diffuse upward as depicted in Fig. 6E. It is important to ensure that upon completion of the manufacturing process, the two body regions between every two adjacent trenches remain spaced apart and do not merge, otherwise the Schottky diode is eliminated.
- Another goal in designing the process is to ensure that N- epi 620 and body region 618D after completion of the process have substantially the same depth, although slightly different depths would not be fatal to the operation of the device.
- These goals can be achieved by adjusting a number of the process steps and parameters including the thermal cycles, the depth of the first trench recess (Fig. 6B), and doping concentration of various regions including the body regions, the N- epi region and the N+ epi region.
- a dimple etch process is performed to etch through N+ regions 622 A such that outer portions 622B of N+ regions 622A are preserved.
- the preserved outer portions 622A form the source region.
- a dimple 624 is thus formed between every two adjacent trench. Dimples 624 form contact openings extending below source regions 622B and into N- regions 620.
- "Dimple etch" as used in this disclosure refers to silicon etch techniques which result in formation of silicon regions with sloped, rounded outer profiles as do source regions 622B in Fig. 6F.
- the dimples extend to a depth within the bottom half of body regions 618D.
- a deeper dimple results in formation of a Schottky contact below the source regions. This helps divert reverse avalanche current away from the source, thus preventing the parasitic bipolar transistor from turning on.
- a mask is used to define a central portion of N+ regions 622 A that is etched through to the desired depth. Outer portions of N+ regions 622 A extending under such a mask are thus preserved. These outer regions form the source regions.
- a masking layer P-type dopants are implanted into the dimple region intermittently along each stripe. Islands of heavy body regions (not shown) are thus formed between every two adjacent trench. If the heavy body implementation of Fig. 4 is desired, a high enough dosage of P-type dopants need to be used during the heavy body implant in order to counter-dope those portions of the source regions where the heavy body regions are to be formed. If the heavy body implementation of Fig. 5 is desired, a lower dosage of P-type dopants needs to be used during the implant so that the source regions are not counter-doped and thus remain intact. [0047J In Fig. 6F, conventional techniques can be used to form a Schottky barrier metal 630 over the structure. Schottky barrier metal 630 fills dimples 624, and where metal 630 comes in electrical contact with N- regions 620, a Schottky diode is formed. Metal layer 630 also contacts source regions 622B and the heavy body regions.
- the integrated MOSFET-Schottky structure has many vertical and horizontal self-aligned features.
- the above-described process embodiments enable reduction of the channel length.
- Conventional processes utilize an implant and drive technique to form the body regions. This technique results in a tapered doping profile in the channel region requiring a longer channel length.
- the above- described alternate techniques of selective epitaxial growth and two-pass angled implant for forming the body regions provide a uniform doping profile in the channel region, thus allowing a shorter channel length to be used. The on-resistance of the device is thus improved.
- Vth MOSFET threshold voltage
- body regions 618 in N- epi 618 which compared to N+ epi 602 exhibits a far more consistent and predictable doping concentration. Forming body regions in a background region with a predictable doping concentration allows tighter control over the threshold voltage.
- shielded electrodes 605 extending into N+ epi 602 allows use of a higher doping concentration in N+ epi 602 for the same breakdown voltage. A lower on-resistance is thus obtained for the same breakdown voltage and without adversely impacting control over the MOSFET threshold voltage.
- Figs. 7A-7C show simulated avalanche current flow lines for three different dimple depths in an integrated trench MOSFET-Schottky diode structure.
- dimple 729A extends to a depth just below source region 722.
- dimple 729B extends deeper to about one half the height of body region 718.
- dimple 729C extends even deeper to just above the bottom of body region 718.
- a gap appears in the top metal 730. This gap was included only for simulation purposes, and in practice, no such gap would be present in the top metal as is evident from the other figures in this disclosure.
- avalanche current flow lines 732 A are in close proximity to source region 722. However, as the dimple depth is increased in Fig. 7B and yet deeper in Fig. 7C, avalanche current flow lines 732B and 732C are shifted further away from source region 722 toward the Schottky region. The diversion of avalanche current away from the source region helps prevent the parasitic bipolar transistor from turning on, and thus improves the ruggedness of the device. In essence, the Schottky region acts like a heavy body region in collecting the avalanche current, thus eliminating the need for heavy body region for this purpose.
- Heavy body regions would still be required to obtain a good contact to the body region, but the frequency and size of the heavy body regions can be significantly reduced compared to conventional MOSFET structures. This frees up a large silicon area which is allocated to the Schottky diode.
- dimples which extend to a depth within the bottom half of body region 718 provide optimum results.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE112007000700.1T DE112007000700B4 (de) | 2006-03-24 | 2007-03-08 | Trench-FET mit hoher Dichte und integrierter Schottky-Diode und Herstellungsverfahren |
JP2009501633A JP2009531836A (ja) | 2006-03-24 | 2007-03-08 | 集積化ショットキーダイオードに設けられた高密度トレンチとその製造方法 |
AT0914007A AT505583A2 (de) | 2006-03-24 | 2007-03-08 | Trench-fet mit hoher dichte und integrierter schottky-diode und herstellungsverfahren |
KR1020087024224A KR101361239B1 (ko) | 2006-03-24 | 2007-03-08 | 집적된 쇼트키 다이오드를 포함하는 고밀도 트랜치 전계 효과 트랜지스터 및 그 제조 방법 |
CN2007800190574A CN101454882B (zh) | 2006-03-24 | 2007-03-08 | 具有集成肖特基二极管的高密度沟槽fet及制造方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/388,790 US7446374B2 (en) | 2006-03-24 | 2006-03-24 | High density trench FET with integrated Schottky diode and method of manufacture |
US11/388,790 | 2006-03-24 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2007112187A2 true WO2007112187A2 (en) | 2007-10-04 |
WO2007112187A3 WO2007112187A3 (en) | 2008-04-17 |
Family
ID=38532425
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2007/063612 WO2007112187A2 (en) | 2006-03-24 | 2007-03-08 | High density trench fet with integrated schottky diode and method of manufacture |
Country Status (8)
Country | Link |
---|---|
US (2) | US7446374B2 (zh) |
JP (1) | JP2009531836A (zh) |
KR (1) | KR101361239B1 (zh) |
CN (1) | CN101454882B (zh) |
AT (1) | AT505583A2 (zh) |
DE (1) | DE112007000700B4 (zh) |
TW (1) | TWI443826B (zh) |
WO (1) | WO2007112187A2 (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009253139A (ja) * | 2008-04-09 | 2009-10-29 | Renesas Technology Corp | 半導体装置およびその製造方法 |
US7713822B2 (en) | 2006-03-24 | 2010-05-11 | Fairchild Semiconductor Corporation | Method of forming high density trench FET with integrated Schottky diode |
Families Citing this family (80)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6838722B2 (en) * | 2002-03-22 | 2005-01-04 | Siliconix Incorporated | Structures of and methods of fabricating trench-gated MIS devices |
US7948029B2 (en) | 2005-02-11 | 2011-05-24 | Alpha And Omega Semiconductor Incorporated | MOS device with varying trench depth |
US8283723B2 (en) * | 2005-02-11 | 2012-10-09 | Alpha & Omega Semiconductor Limited | MOS device with low injection diode |
US7285822B2 (en) * | 2005-02-11 | 2007-10-23 | Alpha & Omega Semiconductor, Inc. | Power MOS device |
US8362547B2 (en) | 2005-02-11 | 2013-01-29 | Alpha & Omega Semiconductor Limited | MOS device with Schottky barrier controlling layer |
US7952139B2 (en) * | 2005-02-11 | 2011-05-31 | Alpha & Omega Semiconductor Ltd. | Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout |
US8093651B2 (en) * | 2005-02-11 | 2012-01-10 | Alpha & Omega Semiconductor Limited | MOS device with integrated schottky diode in active region contact trench |
JP5222466B2 (ja) | 2006-08-09 | 2013-06-26 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US8008716B2 (en) * | 2006-09-17 | 2011-08-30 | Alpha & Omega Semiconductor, Ltd | Inverted-trench grounded-source FET structure with trenched source body short electrode |
US7544571B2 (en) * | 2006-09-20 | 2009-06-09 | Fairchild Semiconductor Corporation | Trench gate FET with self-aligned features |
US20080150013A1 (en) * | 2006-12-22 | 2008-06-26 | Alpha & Omega Semiconductor, Ltd | Split gate formation with high density plasma (HDP) oxide layer as inter-polysilicon insulation layer |
US8686493B2 (en) * | 2007-10-04 | 2014-04-01 | Fairchild Semiconductor Corporation | High density FET with integrated Schottky |
US7932556B2 (en) * | 2007-12-14 | 2011-04-26 | Fairchild Semiconductor Corporation | Structure and method for forming power devices with high aspect ratio contact openings |
US7772668B2 (en) * | 2007-12-26 | 2010-08-10 | Fairchild Semiconductor Corporation | Shielded gate trench FET with multiple channels |
US7965126B2 (en) | 2008-02-12 | 2011-06-21 | Transphorm Inc. | Bridge circuits and their components |
US9882049B2 (en) * | 2014-10-06 | 2018-01-30 | Alpha And Omega Semiconductor Incorporated | Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method |
US7977768B2 (en) * | 2008-04-01 | 2011-07-12 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
US9093521B2 (en) * | 2008-06-30 | 2015-07-28 | Alpha And Omega Semiconductor Incorporated | Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout |
US7936009B2 (en) * | 2008-07-09 | 2011-05-03 | Fairchild Semiconductor Corporation | Shielded gate trench FET with an inter-electrode dielectric having a low-k dielectric therein |
US8174067B2 (en) | 2008-12-08 | 2012-05-08 | Fairchild Semiconductor Corporation | Trench-based power semiconductor devices with increased breakdown voltage characteristics |
US8304829B2 (en) | 2008-12-08 | 2012-11-06 | Fairchild Semiconductor Corporation | Trench-based power semiconductor devices with increased breakdown voltage characteristics |
US8362552B2 (en) * | 2008-12-23 | 2013-01-29 | Alpha And Omega Semiconductor Incorporated | MOSFET device with reduced breakdown voltage |
US8227855B2 (en) | 2009-02-09 | 2012-07-24 | Fairchild Semiconductor Corporation | Semiconductor devices with stable and controlled avalanche characteristics and methods of fabricating the same |
US8148749B2 (en) | 2009-02-19 | 2012-04-03 | Fairchild Semiconductor Corporation | Trench-shielded semiconductor device |
TWI388059B (zh) * | 2009-05-01 | 2013-03-01 | Niko Semiconductor Co Ltd | The structure of gold-oxygen semiconductor and its manufacturing method |
US8049276B2 (en) | 2009-06-12 | 2011-11-01 | Fairchild Semiconductor Corporation | Reduced process sensitivity of electrode-semiconductor rectifiers |
CN101609801B (zh) * | 2009-07-03 | 2011-05-25 | 英属维京群岛商节能元件股份有限公司 | 沟槽式肖特基二极管及其制作方法 |
US7952141B2 (en) | 2009-07-24 | 2011-05-31 | Fairchild Semiconductor Corporation | Shield contacts in a shielded gate MOSFET |
US8252647B2 (en) * | 2009-08-31 | 2012-08-28 | Alpha & Omega Semiconductor Incorporated | Fabrication of trench DMOS device having thick bottom shielding oxide |
TWI380448B (en) * | 2009-09-16 | 2012-12-21 | Anpec Electronics Corp | Overlapping trench gate semiconductor device and manufacturing method thereof |
US9425305B2 (en) | 2009-10-20 | 2016-08-23 | Vishay-Siliconix | Structures of and methods of fabricating split gate MIS devices |
US20120220092A1 (en) * | 2009-10-21 | 2012-08-30 | Vishay-Siliconix | Method of forming a hybrid split gate simiconductor |
US9419129B2 (en) | 2009-10-21 | 2016-08-16 | Vishay-Siliconix | Split gate semiconductor device with curved gate oxide profile |
US8247296B2 (en) * | 2009-12-09 | 2012-08-21 | Semiconductor Components Industries, Llc | Method of forming an insulated gate field effect transistor device having a shield electrode structure |
JP5636254B2 (ja) * | 2009-12-15 | 2014-12-03 | 株式会社東芝 | 半導体装置 |
WO2011109559A2 (en) | 2010-03-02 | 2011-09-09 | Kyle Terrill | Structures and methods of fabricating dual gate devices |
CN101882617B (zh) * | 2010-06-12 | 2011-11-30 | 中国科学院上海微***与信息技术研究所 | 肖特基二极管、半导体存储器及其制造工艺 |
US8252648B2 (en) * | 2010-06-29 | 2012-08-28 | Alpha & Omega Semiconductor, Inc. | Power MOSFET device with self-aligned integrated Schottky and its manufacturing method |
JP5740108B2 (ja) * | 2010-07-16 | 2015-06-24 | 株式会社東芝 | 半導体装置 |
CN102347359B (zh) * | 2010-07-29 | 2014-03-26 | 万国半导体股份有限公司 | 一种功率mosfet器件及其制造方法 |
JP5674530B2 (ja) * | 2010-09-10 | 2015-02-25 | ルネサスエレクトロニクス株式会社 | 半導体装置の制御装置 |
US8461646B2 (en) * | 2011-02-04 | 2013-06-11 | Vishay General Semiconductor Llc | Trench MOS barrier schottky (TMBS) having multiple floating gates |
US8587059B2 (en) * | 2011-04-22 | 2013-11-19 | Infineon Technologies Austria Ag | Transistor arrangement with a MOSFET |
US8502302B2 (en) | 2011-05-02 | 2013-08-06 | Alpha And Omega Semiconductor Incorporated | Integrating Schottky diode into power MOSFET |
WO2012158977A2 (en) | 2011-05-18 | 2012-11-22 | Vishay-Siliconix | Semiconductor device |
JP6290526B2 (ja) | 2011-08-24 | 2018-03-07 | ローム株式会社 | 半導体装置およびその製造方法 |
DE112013002260B4 (de) * | 2012-04-30 | 2023-03-30 | Vishay-Siliconix | Herstellungsverfahren einer integrierten Schaltung |
US8921931B2 (en) * | 2012-06-04 | 2014-12-30 | Infineon Technologies Austria Ag | Semiconductor device with trench structures including a recombination structure and a fill structure |
KR101828495B1 (ko) | 2013-03-27 | 2018-02-12 | 삼성전자주식회사 | 평탄한 소스 전극을 가진 반도체 소자 |
KR101934893B1 (ko) | 2013-03-27 | 2019-01-03 | 삼성전자 주식회사 | 그루브 소스 컨택 영역을 가진 반도체 소자의 제조 방법 |
KR20150035198A (ko) * | 2013-09-27 | 2015-04-06 | 삼성전자주식회사 | 반도체 소자 및 그 제조방법 |
KR102046663B1 (ko) * | 2013-11-04 | 2019-11-20 | 매그나칩 반도체 유한회사 | 반도체 소자 및 그 제조방법 |
CN105531825B (zh) * | 2013-12-16 | 2019-01-01 | 富士电机株式会社 | 半导体装置及半导体装置的制造方法 |
US10234486B2 (en) | 2014-08-19 | 2019-03-19 | Vishay/Siliconix | Vertical sense devices in vertical trench MOSFET |
WO2016086381A1 (zh) * | 2014-12-04 | 2016-06-09 | 冯淑华 | 沟槽栅功率半导体场效应晶体管 |
US10008384B2 (en) | 2015-06-25 | 2018-06-26 | Varian Semiconductor Equipment Associates, Inc. | Techniques to engineer nanoscale patterned features using ions |
JP6217708B2 (ja) * | 2015-07-30 | 2017-10-25 | トヨタ自動車株式会社 | 半導体装置とその製造方法 |
US9780088B1 (en) | 2016-03-31 | 2017-10-03 | International Business Machines Corporation | Co-fabrication of vertical diodes and fin field effect transistors on the same substrate |
CN105957884A (zh) * | 2016-06-24 | 2016-09-21 | 上海格瑞宝电子有限公司 | 一种分栅栅极沟槽结构和沟槽肖特基二极管及其制备方法 |
KR101836258B1 (ko) | 2016-07-05 | 2018-03-08 | 현대자동차 주식회사 | 반도체 소자 및 그 제조 방법 |
US10304971B2 (en) | 2016-07-16 | 2019-05-28 | Champion Microelectronic Corp. | High speed Schottky rectifier |
US20190221664A1 (en) * | 2016-09-02 | 2019-07-18 | Shindengen Electric Manufacturing Co., Ltd. | Mosfet and power conversion circuit |
US10770599B2 (en) | 2016-09-03 | 2020-09-08 | Champion Microelectronic Corp. | Deep trench MOS barrier junction all around rectifier and MOSFET |
US10211333B2 (en) * | 2017-04-26 | 2019-02-19 | Alpha And Omega Semiconductor (Cayman) Ltd. | Scalable SGT structure with improved FOM |
JP2019046991A (ja) * | 2017-09-04 | 2019-03-22 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US11081554B2 (en) * | 2017-10-12 | 2021-08-03 | Semiconductor Components Industries, Llc | Insulated gate semiconductor device having trench termination structure and method |
CN108231900A (zh) * | 2017-12-28 | 2018-06-29 | 中山汉臣电子科技有限公司 | 一种功率半导体器件及其制备方法 |
JP6923457B2 (ja) * | 2018-01-19 | 2021-08-18 | 株式会社日立製作所 | 炭化ケイ素半導体装置およびその製造方法、電力変換装置、自動車並びに鉄道車両 |
DE102018103849B4 (de) * | 2018-02-21 | 2022-09-01 | Infineon Technologies Ag | Siliziumcarbid-Halbleiterbauelement mit einer in einer Grabenstruktur ausgebildeten Gateelektrode |
CN108346701B (zh) * | 2018-04-12 | 2020-05-26 | 电子科技大学 | 一种屏蔽栅功率dmos器件 |
US11031472B2 (en) * | 2018-12-28 | 2021-06-08 | General Electric Company | Systems and methods for integrated diode field-effect transistor semiconductor devices |
US11217541B2 (en) | 2019-05-08 | 2022-01-04 | Vishay-Siliconix, LLC | Transistors with electrically active chip seal ring and methods of manufacture |
CN110492761A (zh) * | 2019-07-12 | 2019-11-22 | 西安科锐盛创新科技有限公司 | 一种整流电路***、整流天线和微波无线能量传输*** |
JP7237772B2 (ja) * | 2019-08-20 | 2023-03-13 | 株式会社東芝 | 半導体装置 |
US11183514B2 (en) | 2019-09-05 | 2021-11-23 | Globalfoundries U.S. Inc. | Vertically stacked field effect transistors |
US11218144B2 (en) | 2019-09-12 | 2022-01-04 | Vishay-Siliconix, LLC | Semiconductor device with multiple independent gates |
US11114558B2 (en) * | 2019-10-18 | 2021-09-07 | Nami MOS CO., LTD. | Shielded gate trench MOSFET integrated with super barrier rectifier |
US11869967B2 (en) | 2021-08-12 | 2024-01-09 | Alpha And Omega Semiconductor International Lp | Bottom source trench MOSFET with shield electrode |
CN114664926A (zh) * | 2022-03-30 | 2022-06-24 | 电子科技大学 | 一种功率半导体器件结构 |
DE102022110998A1 (de) | 2022-05-04 | 2023-11-09 | Infineon Technologies Ag | Halbleitervorrichtung und verfahren zum herstellen einer halbleitervorrichtung |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6562634B2 (en) * | 1998-08-31 | 2003-05-13 | International Business Machines Corporation | Diode connected to a magnetic tunnel junction and self aligned with a metallic conductor and method of forming the same |
US6878994B2 (en) * | 2002-08-22 | 2005-04-12 | International Rectifier Corporation | MOSgated device with accumulated channel region and Schottky contact |
US20050167742A1 (en) * | 2001-01-30 | 2005-08-04 | Fairchild Semiconductor Corp. | Power semiconductor devices and methods of manufacture |
US20050218472A1 (en) * | 2004-03-29 | 2005-10-06 | Sanyo Electric Co., Ltd | Semiconductor device manufacturing method thereof |
US20050285238A1 (en) * | 2004-06-24 | 2005-12-29 | Joshi Rajeev D | Integrated transistor module and method of fabricating same |
Family Cites Families (313)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3257626A (en) | 1962-12-31 | 1966-06-21 | Ibm | Semiconductor laser structures |
US3404295A (en) | 1964-11-30 | 1968-10-01 | Motorola Inc | High frequency and voltage transistor with added region for punch-through protection |
US3412297A (en) | 1965-12-16 | 1968-11-19 | United Aircraft Corp | Mos field-effect transistor with a onemicron vertical channel |
US3497777A (en) | 1967-06-13 | 1970-02-24 | Stanislas Teszner | Multichannel field-effect semi-conductor device |
US3564356A (en) | 1968-10-24 | 1971-02-16 | Tektronix Inc | High voltage integrated circuit transistor |
US3660697A (en) | 1970-02-16 | 1972-05-02 | Bell Telephone Labor Inc | Monolithic semiconductor apparatus adapted for sequential charge transfer |
US4003072A (en) | 1972-04-20 | 1977-01-11 | Sony Corporation | Semiconductor device with high voltage breakdown resistance |
US4337474A (en) | 1978-08-31 | 1982-06-29 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
US4638344A (en) | 1979-10-09 | 1987-01-20 | Cardwell Jr Walter T | Junction field-effect transistor controlled by merged depletion regions |
US4698653A (en) | 1979-10-09 | 1987-10-06 | Cardwell Jr Walter T | Semiconductor devices controlled by depletion regions |
US4338616A (en) | 1980-02-19 | 1982-07-06 | Xerox Corporation | Self-aligned Schottky metal semi-conductor field effect transistor with buried source and drain |
US4868624A (en) | 1980-05-09 | 1989-09-19 | Regents Of The University Of Minnesota | Channel collector transistor |
US4300150A (en) | 1980-06-16 | 1981-11-10 | North American Philips Corporation | Lateral double-diffused MOS transistor device |
US4326332A (en) | 1980-07-28 | 1982-04-27 | International Business Machines Corp. | Method of making a high density V-MOS memory array |
EP0051693B1 (de) | 1980-11-12 | 1985-06-19 | Ibm Deutschland Gmbh | Elektrisch umschaltbarer Festwertspeicher |
US4324038A (en) | 1980-11-24 | 1982-04-13 | Bell Telephone Laboratories, Incorporated | Method of fabricating MOS field effect transistors |
GB2089119A (en) | 1980-12-10 | 1982-06-16 | Philips Electronic Associated | High voltage semiconductor devices |
US4974059A (en) | 1982-12-21 | 1990-11-27 | International Rectifier Corporation | Semiconductor high-power mosfet device |
JPS6016420A (ja) | 1983-07-08 | 1985-01-28 | Mitsubishi Electric Corp | 選択的エピタキシヤル成長方法 |
US4639761A (en) | 1983-12-16 | 1987-01-27 | North American Philips Corporation | Combined bipolar-field effect transistor resurf devices |
US4568958A (en) | 1984-01-03 | 1986-02-04 | General Electric Company | Inversion-mode insulated-gate gallium arsenide field-effect transistors |
FR2566179B1 (fr) | 1984-06-14 | 1986-08-22 | Commissariat Energie Atomique | Procede d'autopositionnement d'un oxyde de champ localise par rapport a une tranchee d'isolement |
US5208657A (en) | 1984-08-31 | 1993-05-04 | Texas Instruments Incorporated | DRAM Cell with trench capacitor and vertical channel in substrate |
US4824793A (en) | 1984-09-27 | 1989-04-25 | Texas Instruments Incorporated | Method of making DRAM cell with trench capacitor |
US4694313A (en) | 1985-02-19 | 1987-09-15 | Harris Corporation | Conductivity modulated semiconductor structure |
US4673962A (en) | 1985-03-21 | 1987-06-16 | Texas Instruments Incorporated | Vertical DRAM cell and method |
US4774556A (en) | 1985-07-25 | 1988-09-27 | Nippondenso Co., Ltd. | Non-volatile semiconductor memory device |
US4956308A (en) | 1987-01-20 | 1990-09-11 | Itt Corporation | Method of making self-aligned field-effect transistor |
US5262336A (en) | 1986-03-21 | 1993-11-16 | Advanced Power Technology, Inc. | IGBT process to produce platinum lifetime control |
US4767722A (en) | 1986-03-24 | 1988-08-30 | Siliconix Incorporated | Method for making planar vertical channel DMOS structures |
US5034785A (en) | 1986-03-24 | 1991-07-23 | Siliconix Incorporated | Planar vertical channel DMOS structure |
US4716126A (en) | 1986-06-05 | 1987-12-29 | Siliconix Incorporated | Fabrication of double diffused metal oxide semiconductor transistor |
JPH0693512B2 (ja) | 1986-06-17 | 1994-11-16 | 日産自動車株式会社 | 縦形mosfet |
US5607511A (en) | 1992-02-21 | 1997-03-04 | International Business Machines Corporation | Method and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers |
US4746630A (en) | 1986-09-17 | 1988-05-24 | Hewlett-Packard Company | Method for producing recessed field oxide with improved sidewall characteristics |
US4941026A (en) | 1986-12-05 | 1990-07-10 | General Electric Company | Semiconductor devices exhibiting minimum on-resistance |
JP2577330B2 (ja) | 1986-12-11 | 1997-01-29 | 新技術事業団 | 両面ゲ−ト静電誘導サイリスタの製造方法 |
JPS63171856A (ja) | 1987-01-09 | 1988-07-15 | Hitachi Ltd | 耐熱鋼 |
US5105243A (en) | 1987-02-26 | 1992-04-14 | Kabushiki Kaisha Toshiba | Conductivity-modulation metal oxide field effect transistor with single gate structure |
US4821095A (en) | 1987-03-12 | 1989-04-11 | General Electric Company | Insulated gate semiconductor device with extra short grid and method of fabrication |
US4745079A (en) | 1987-03-30 | 1988-05-17 | Motorola, Inc. | Method for fabricating MOS transistors having gates with different work functions |
US4801986A (en) | 1987-04-03 | 1989-01-31 | General Electric Company | Vertical double diffused metal oxide semiconductor VDMOS device with increased safe operating area and method |
US4823176A (en) | 1987-04-03 | 1989-04-18 | General Electric Company | Vertical double diffused metal oxide semiconductor (VDMOS) device including high voltage junction exhibiting increased safe operating area |
US4811065A (en) | 1987-06-11 | 1989-03-07 | Siliconix Incorporated | Power DMOS transistor with high speed body diode |
US5164325A (en) | 1987-10-08 | 1992-11-17 | Siliconix Incorporated | Method of making a vertical current flow field effect transistor |
US4893160A (en) | 1987-11-13 | 1990-01-09 | Siliconix Incorporated | Method for increasing the performance of trenched devices and the resulting structure |
US4914058A (en) | 1987-12-29 | 1990-04-03 | Siliconix Incorporated | Grooved DMOS process with varying gate dielectric thickness |
US4967245A (en) | 1988-03-14 | 1990-10-30 | Siliconix Incorporated | Trench power MOSFET device |
US4903189A (en) | 1988-04-27 | 1990-02-20 | General Electric Company | Low noise, high frequency synchronous rectifier |
US5283201A (en) | 1988-05-17 | 1994-02-01 | Advanced Power Technology, Inc. | High density power device fabrication process |
KR0173111B1 (ko) | 1988-06-02 | 1999-02-01 | 야마무라 가쯔미 | 트렌치 게이트 mos fet |
JPH0216763A (ja) | 1988-07-05 | 1990-01-19 | Toshiba Corp | 半導体装置の製造方法 |
US4853345A (en) | 1988-08-22 | 1989-08-01 | Delco Electronics Corporation | Process for manufacture of a vertical DMOS transistor |
US5268311A (en) | 1988-09-01 | 1993-12-07 | International Business Machines Corporation | Method for forming a thin dielectric layer on a substrate |
US5156989A (en) | 1988-11-08 | 1992-10-20 | Siliconix, Incorporated | Complementary, isolated DMOS IC technology |
US5346834A (en) | 1988-11-21 | 1994-09-13 | Hitachi, Ltd. | Method for manufacturing a semiconductor device and a semiconductor memory device |
US5072266A (en) | 1988-12-27 | 1991-12-10 | Siliconix Incorporated | Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry |
US5111253A (en) | 1989-05-09 | 1992-05-05 | General Electric Company | Multicellular FET having a Schottky diode merged therewith |
US4992390A (en) | 1989-07-06 | 1991-02-12 | General Electric Company | Trench gate structure with thick bottom oxide |
EP0450082B1 (en) | 1989-08-31 | 2004-04-28 | Denso Corporation | Insulated gate bipolar transistor |
US4982260A (en) | 1989-10-02 | 1991-01-01 | General Electric Company | Power rectifier with trenches |
US5248894A (en) | 1989-10-03 | 1993-09-28 | Harris Corporation | Self-aligned channel stop for trench-isolated island |
KR950006483B1 (ko) | 1990-06-13 | 1995-06-15 | 가부시끼가이샤 도시바 | 종형 mos트랜지스터와 그 제조방법 |
US5242845A (en) | 1990-06-13 | 1993-09-07 | Kabushiki Kaisha Toshiba | Method of production of vertical MOS transistor |
US5071782A (en) | 1990-06-28 | 1991-12-10 | Texas Instruments Incorporated | Vertical memory cell array and method of fabrication |
US5079608A (en) | 1990-11-06 | 1992-01-07 | Harris Corporation | Power MOSFET transistor circuit with active clamp |
US5065273A (en) | 1990-12-04 | 1991-11-12 | International Business Machines Corporation | High capacity DRAM trench capacitor and methods of fabricating same |
US5684320A (en) | 1991-01-09 | 1997-11-04 | Fujitsu Limited | Semiconductor device having transistor pair |
CN1019720B (zh) | 1991-03-19 | 1992-12-30 | 电子科技大学 | 半导体功率器件 |
US5164802A (en) | 1991-03-20 | 1992-11-17 | Harris Corporation | Power vdmosfet with schottky on lightly doped drain of lateral driver fet |
US5250450A (en) | 1991-04-08 | 1993-10-05 | Micron Technology, Inc. | Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance |
JP2603886B2 (ja) | 1991-05-09 | 1997-04-23 | 日本電信電話株式会社 | 薄層soi型絶縁ゲート型電界効果トランジスタの製造方法 |
KR940002400B1 (ko) | 1991-05-15 | 1994-03-24 | 금성일렉트론 주식회사 | 리세스 게이트를 갖는 반도체장치의 제조방법 |
US5219793A (en) | 1991-06-03 | 1993-06-15 | Motorola Inc. | Method for forming pitch independent contacts and a semiconductor device having the same |
KR940006702B1 (ko) | 1991-06-14 | 1994-07-25 | 금성일렉트론 주식회사 | 모스패트의 제조방법 |
JP2570022B2 (ja) | 1991-09-20 | 1997-01-08 | 株式会社日立製作所 | 定電圧ダイオード及びそれを用いた電力変換装置並びに定電圧ダイオードの製造方法 |
JPH0613627A (ja) | 1991-10-08 | 1994-01-21 | Semiconductor Energy Lab Co Ltd | 半導体装置およびその作製方法 |
JPH05304297A (ja) | 1992-01-29 | 1993-11-16 | Nec Corp | 電力用半導体装置およびその製造方法 |
US5283452A (en) | 1992-02-14 | 1994-02-01 | Hughes Aircraft Company | Distributed cell monolithic mircowave integrated circuit (MMIC) field-effect transistor (FET) amplifier |
US5315142A (en) | 1992-03-23 | 1994-05-24 | International Business Machines Corporation | High performance trench EEPROM cell |
US5554862A (en) | 1992-03-31 | 1996-09-10 | Kabushiki Kaisha Toshiba | Power semiconductor device |
JPH06196723A (ja) | 1992-04-28 | 1994-07-15 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
US5640034A (en) | 1992-05-18 | 1997-06-17 | Texas Instruments Incorporated | Top-drain trench based resurf DMOS transistor structure |
US5233215A (en) | 1992-06-08 | 1993-08-03 | North Carolina State University At Raleigh | Silicon carbide power MOSFET with floating field ring and floating field plate |
US5430324A (en) | 1992-07-23 | 1995-07-04 | Siliconix, Incorporated | High voltage transistor having edge termination utilizing trench technology |
US5558313A (en) | 1992-07-24 | 1996-09-24 | Siliconix Inorporated | Trench field effect transistor with reduced punch-through susceptibility and low RDSon |
US5910669A (en) | 1992-07-24 | 1999-06-08 | Siliconix Incorporated | Field effect Trench transistor having lightly doped epitaxial region on the surface portion thereof |
US5294824A (en) | 1992-07-31 | 1994-03-15 | Motorola, Inc. | High voltage transistor having reduced on-resistance |
GB9216599D0 (en) | 1992-08-05 | 1992-09-16 | Philips Electronics Uk Ltd | A semiconductor device comprising a vertical insulated gate field effect device and a method of manufacturing such a device |
US5300447A (en) | 1992-09-29 | 1994-04-05 | Texas Instruments Incorporated | Method of manufacturing a minimum scaled transistor |
JPH06163907A (ja) | 1992-11-20 | 1994-06-10 | Hitachi Ltd | 電圧駆動型半導体装置 |
US5275965A (en) | 1992-11-25 | 1994-01-04 | Micron Semiconductor, Inc. | Trench isolation using gated sidewalls |
US5326711A (en) | 1993-01-04 | 1994-07-05 | Texas Instruments Incorporated | High performance high voltage vertical transistor and method of fabrication |
DE4300806C1 (de) | 1993-01-14 | 1993-12-23 | Siemens Ag | Verfahren zur Herstellung von vertikalen MOS-Transistoren |
US5418376A (en) | 1993-03-02 | 1995-05-23 | Toyo Denki Seizo Kabushiki Kaisha | Static induction semiconductor device with a distributed main electrode structure and static induction semiconductor device with a static induction main electrode shorted structure |
US5341011A (en) | 1993-03-15 | 1994-08-23 | Siliconix Incorporated | Short channel trenched DMOS transistor |
DE4309764C2 (de) | 1993-03-25 | 1997-01-30 | Siemens Ag | Leistungs-MOSFET |
GB9306895D0 (en) | 1993-04-01 | 1993-05-26 | Philips Electronics Uk Ltd | A method of manufacturing a semiconductor device comprising an insulated gate field effect device |
KR960012585B1 (en) | 1993-06-25 | 1996-09-23 | Samsung Electronics Co Ltd | Transistor structure and the method for manufacturing the same |
US5349224A (en) | 1993-06-30 | 1994-09-20 | Purdue Research Foundation | Integrable MOS and IGBT devices having trench gate structure |
US5371396A (en) | 1993-07-02 | 1994-12-06 | Thunderbird Technologies, Inc. | Field effect transistor having polycrystalline silicon gate junction |
US5365102A (en) | 1993-07-06 | 1994-11-15 | North Carolina State University | Schottky barrier rectifier with MOS trench |
BE1007283A3 (nl) | 1993-07-12 | 1995-05-09 | Philips Electronics Nv | Halfgeleiderinrichting met een most voorzien van een extended draingebied voor hoge spanningen. |
US5420061A (en) | 1993-08-13 | 1995-05-30 | Micron Semiconductor, Inc. | Method for improving latchup immunity in a dual-polysilicon gate process |
JPH07122749A (ja) | 1993-09-01 | 1995-05-12 | Toshiba Corp | 半導体装置及びその製造方法 |
JP3400846B2 (ja) | 1994-01-20 | 2003-04-28 | 三菱電機株式会社 | トレンチ構造を有する半導体装置およびその製造方法 |
US5429977A (en) | 1994-03-11 | 1995-07-04 | Industrial Technology Research Institute | Method for forming a vertical transistor with a stacked capacitor DRAM cell |
US5449925A (en) | 1994-05-04 | 1995-09-12 | North Carolina State University | Voltage breakdown resistant monocrystalline silicon carbide semiconductor devices |
US5434435A (en) | 1994-05-04 | 1995-07-18 | North Carolina State University | Trench gate lateral MOSFET |
DE4417150C2 (de) | 1994-05-17 | 1996-03-14 | Siemens Ag | Verfahren zur Herstellung einer Anordnung mit selbstverstärkenden dynamischen MOS-Transistorspeicherzellen |
US5454435A (en) * | 1994-05-25 | 1995-10-03 | Reinhardt; Lisa | Device for facilitating insertion of a beach umbrella in sand |
US5405794A (en) | 1994-06-14 | 1995-04-11 | Philips Electronics North America Corporation | Method of producing VDMOS device of increased power density |
US5424231A (en) | 1994-08-09 | 1995-06-13 | United Microelectronics Corp. | Method for manufacturing a VDMOS transistor |
US5583368A (en) | 1994-08-11 | 1996-12-10 | International Business Machines Corporation | Stacked devices |
EP0698919B1 (en) | 1994-08-15 | 2002-01-16 | Siliconix Incorporated | Trenched DMOS transistor fabrication using seven masks |
US5581100A (en) | 1994-08-30 | 1996-12-03 | International Rectifier Corporation | Trench depletion MOSFET |
US5508542A (en) | 1994-10-28 | 1996-04-16 | International Business Machines Corporation | Porous silicon trench and capacitor structures |
JP3708998B2 (ja) | 1994-11-04 | 2005-10-19 | シーメンス アクチエンゲゼルシヤフト | 電界効果により制御可能の半導体デバイスの製造方法 |
US5583065A (en) | 1994-11-23 | 1996-12-10 | Sony Corporation | Method of making a MOS semiconductor device |
US5674766A (en) | 1994-12-30 | 1997-10-07 | Siliconix Incorporated | Method of making a trench MOSFET with multi-resistivity drain to provide low on-resistance by varying dopant concentration in epitaxial layer |
US6008520A (en) | 1994-12-30 | 1999-12-28 | Siliconix Incorporated | Trench MOSFET with heavily doped delta layer to provide low on- resistance |
US5597765A (en) | 1995-01-10 | 1997-01-28 | Siliconix Incorporated | Method for making termination structure for power MOSFET |
JPH08204179A (ja) | 1995-01-26 | 1996-08-09 | Fuji Electric Co Ltd | 炭化ケイ素トレンチmosfet |
US5670803A (en) | 1995-02-08 | 1997-09-23 | International Business Machines Corporation | Three-dimensional SRAM trench structure and fabrication method therefor |
JP3325736B2 (ja) | 1995-02-09 | 2002-09-17 | 三菱電機株式会社 | 絶縁ゲート型半導体装置 |
DE69602114T2 (de) | 1995-02-10 | 1999-08-19 | Siliconix Inc. | Graben-Feldeffekttransistor mit PN-Verarmungsschicht-Barriere |
JP3291957B2 (ja) | 1995-02-17 | 2002-06-17 | 富士電機株式会社 | 縦型トレンチmisfetおよびその製造方法 |
US5595927A (en) | 1995-03-17 | 1997-01-21 | Taiwan Semiconductor Manufacturing Company Ltd. | Method for making self-aligned source/drain mask ROM memory cell using trench etched channel |
US5592005A (en) | 1995-03-31 | 1997-01-07 | Siliconix Incorporated | Punch-through field effect transistor |
US5554552A (en) | 1995-04-03 | 1996-09-10 | Taiwan Semiconductor Manufacturing Company | PN junction floating gate EEPROM, flash EPROM device and method of manufacture thereof |
US5744372A (en) | 1995-04-12 | 1998-04-28 | National Semiconductor Corporation | Fabrication of complementary field-effect transistors each having multi-part channel |
JPH08306914A (ja) | 1995-04-27 | 1996-11-22 | Nippondenso Co Ltd | 半導体装置およびその製造方法 |
US5567634A (en) | 1995-05-01 | 1996-10-22 | National Semiconductor Corporation | Method of fabricating self-aligned contact trench DMOS transistors |
KR0143459B1 (ko) | 1995-05-22 | 1998-07-01 | 한민구 | 모오스 게이트형 전력 트랜지스터 |
US6140678A (en) | 1995-06-02 | 2000-10-31 | Siliconix Incorporated | Trench-gated power MOSFET with protective diode |
US6049108A (en) | 1995-06-02 | 2000-04-11 | Siliconix Incorporated | Trench-gated MOSFET with bidirectional voltage clamping |
US5648670A (en) | 1995-06-07 | 1997-07-15 | Sgs-Thomson Microelectronics, Inc. | Trench MOS-gated device with a minimum number of masks |
GB9512089D0 (en) | 1995-06-14 | 1995-08-09 | Evans Jonathan L | Semiconductor device fabrication |
US5629543A (en) | 1995-08-21 | 1997-05-13 | Siliconix Incorporated | Trenched DMOS transistor with buried layer for reduced on-resistance and ruggedness |
US5689128A (en) * | 1995-08-21 | 1997-11-18 | Siliconix Incorporated | High density trenched DMOS transistor |
US5847464A (en) | 1995-09-27 | 1998-12-08 | Sgs-Thomson Microelectronics, Inc. | Method for forming controlled voids in interlevel dielectric |
US5705409A (en) | 1995-09-28 | 1998-01-06 | Motorola Inc. | Method for forming trench transistor structure |
JPH09102602A (ja) * | 1995-10-05 | 1997-04-15 | Nippon Telegr & Teleph Corp <Ntt> | Mosfet |
US5616945A (en) | 1995-10-13 | 1997-04-01 | Siliconix Incorporated | Multiple gated MOSFET for use in DC-DC converter |
US5692569A (en) * | 1995-10-17 | 1997-12-02 | Mustad, Incorporated | Horseshoe system |
US5949124A (en) | 1995-10-31 | 1999-09-07 | Motorola, Inc. | Edge termination structure |
US6037632A (en) | 1995-11-06 | 2000-03-14 | Kabushiki Kaisha Toshiba | Semiconductor device |
US5780343A (en) | 1995-12-20 | 1998-07-14 | National Semiconductor Corporation | Method of producing high quality silicon surface for selective epitaxial growth of silicon |
US5637898A (en) | 1995-12-22 | 1997-06-10 | North Carolina State University | Vertical field effect transistors having improved breakdown voltage capability and low on-state resistance |
US6097063A (en) | 1996-01-22 | 2000-08-01 | Fuji Electric Co., Ltd. | Semiconductor device having a plurality of parallel drift regions |
DE59707158D1 (de) | 1996-02-05 | 2002-06-06 | Infineon Technologies Ag | Durch feldeffekt steuerbares halbleiterbauelement |
US6084268A (en) | 1996-03-05 | 2000-07-04 | Semiconductor Components Industries, Llc | Power MOSFET device having low on-resistance and method |
US5821583A (en) | 1996-03-06 | 1998-10-13 | Siliconix Incorporated | Trenched DMOS transistor with lightly doped tub |
DE19611045C1 (de) | 1996-03-20 | 1997-05-22 | Siemens Ag | Durch Feldeffekt steuerbares Halbleiterbauelement |
EP0798785B1 (en) | 1996-03-29 | 2003-12-03 | STMicroelectronics S.r.l. | High-voltage-resistant MOS transistor, and corresponding manufacturing process |
US5895951A (en) * | 1996-04-05 | 1999-04-20 | Megamos Corporation | MOSFET structure and fabrication process implemented by forming deep and narrow doping regions through doping trenches |
US5770878A (en) | 1996-04-10 | 1998-06-23 | Harris Corporation | Trench MOS gate device |
US5767004A (en) | 1996-04-22 | 1998-06-16 | Chartered Semiconductor Manufacturing, Ltd. | Method for forming a low impurity diffusion polysilicon layer |
US5818084A (en) | 1996-05-15 | 1998-10-06 | Siliconix Incorporated | Pseudo-Schottky diode |
EP2043158B1 (en) | 1996-07-19 | 2013-05-15 | SILICONIX Incorporated | Trench DMOS transistor with trench bottom implant |
US5808340A (en) | 1996-09-18 | 1998-09-15 | Advanced Micro Devices, Inc. | Short channel self aligned VMOS field effect transistor |
DE19638438A1 (de) | 1996-09-19 | 1998-04-02 | Siemens Ag | Durch Feldeffekt steuerbares, vertikales Halbleiterbauelement |
JP2891205B2 (ja) | 1996-10-21 | 1999-05-17 | 日本電気株式会社 | 半導体集積回路の製造方法 |
JP3397057B2 (ja) | 1996-11-01 | 2003-04-14 | 日産自動車株式会社 | 半導体装置 |
US6168983B1 (en) | 1996-11-05 | 2001-01-02 | Power Integrations, Inc. | Method of making a high-voltage transistor with multiple lateral conduction layers |
US6207994B1 (en) | 1996-11-05 | 2001-03-27 | Power Integrations, Inc. | High-voltage transistor with multi-layer conduction region |
KR100233832B1 (ko) | 1996-12-14 | 1999-12-01 | 정선종 | 반도체 소자의 트랜지스터 및 그 제조방법 |
US6011298A (en) | 1996-12-31 | 2000-01-04 | Stmicroelectronics, Inc. | High voltage termination with buried field-shaping region |
JPH10256550A (ja) | 1997-01-09 | 1998-09-25 | Toshiba Corp | 半導体装置 |
KR100218260B1 (ko) | 1997-01-14 | 1999-09-01 | 김덕중 | 트랜치 게이트형 모스트랜지스터의 제조방법 |
SE9700141D0 (sv) | 1997-01-20 | 1997-01-20 | Abb Research Ltd | A schottky diode of SiC and a method for production thereof |
JP3938964B2 (ja) | 1997-02-10 | 2007-06-27 | 三菱電機株式会社 | 高耐圧半導体装置およびその製造方法 |
US5877528A (en) | 1997-03-03 | 1999-03-02 | Megamos Corporation | Structure to provide effective channel-stop in termination areas for trenched power transistors |
US6057558A (en) | 1997-03-05 | 2000-05-02 | Denson Corporation | Silicon carbide semiconductor device and manufacturing method thereof |
US5981354A (en) | 1997-03-12 | 1999-11-09 | Advanced Micro Devices, Inc. | Semiconductor fabrication employing a flowable oxide to enhance planarization in a shallow trench isolation process |
KR100225409B1 (ko) | 1997-03-27 | 1999-10-15 | 김덕중 | 트렌치 디-모오스 및 그의 제조 방법 |
US6163052A (en) | 1997-04-04 | 2000-12-19 | Advanced Micro Devices, Inc. | Trench-gated vertical combination JFET and MOSFET devices |
US6281547B1 (en) | 1997-05-08 | 2001-08-28 | Megamos Corporation | Power transistor cells provided with reliable trenched source contacts connected to narrower source manufactured without a source mask |
JPH113936A (ja) | 1997-06-13 | 1999-01-06 | Nec Corp | 半導体装置の製造方法 |
US6096608A (en) | 1997-06-30 | 2000-08-01 | Siliconix Incorporated | Bidirectional trench gated power mosfet with submerged body bus extending underneath gate trench |
US5907776A (en) | 1997-07-11 | 1999-05-25 | Magepower Semiconductor Corp. | Method of forming a semiconductor structure having reduced threshold voltage and high punch-through tolerance |
TW393777B (en) | 1997-09-02 | 2000-06-11 | Nikon Corp | Photoelectric conversion devices and photoelectric conversion apparatus employing the same |
DE19740195C2 (de) | 1997-09-12 | 1999-12-02 | Siemens Ag | Halbleiterbauelement mit Metall-Halbleiterübergang mit niedrigem Sperrstrom |
DE19743342C2 (de) | 1997-09-30 | 2002-02-28 | Infineon Technologies Ag | Feldeffekttransistor hoher Packungsdichte und Verfahren zu seiner Herstellung |
KR100249505B1 (ko) | 1997-10-28 | 2000-03-15 | 정선종 | 수평형 이중 확산 전력 소자의 제조 방법 |
US6337499B1 (en) | 1997-11-03 | 2002-01-08 | Infineon Technologies Ag | Semiconductor component |
US5943581A (en) | 1997-11-05 | 1999-08-24 | Vanguard International Semiconductor Corporation | Method of fabricating a buried reservoir capacitor structure for high-density dynamic random access memory (DRAM) circuits |
GB9723468D0 (en) | 1997-11-07 | 1998-01-07 | Zetex Plc | Method of semiconductor device fabrication |
US6081009A (en) | 1997-11-10 | 2000-06-27 | Intersil Corporation | High voltage mosfet structure |
US6429481B1 (en) | 1997-11-14 | 2002-08-06 | Fairchild Semiconductor Corporation | Field effect transistor and method of its manufacture |
US6426260B1 (en) | 1997-12-02 | 2002-07-30 | Magepower Semiconductor Corp. | Switching speed improvement in DMO by implanting lightly doped region under gate |
US5949104A (en) | 1998-02-07 | 1999-09-07 | Xemod, Inc. | Source connection structure for lateral RF MOS devices |
JP3641547B2 (ja) | 1998-03-25 | 2005-04-20 | 株式会社豊田中央研究所 | 横型mos素子を含む半導体装置 |
US5897343A (en) | 1998-03-30 | 1999-04-27 | Motorola, Inc. | Method of making a power switching trench MOSFET having aligned source regions |
US5945724A (en) | 1998-04-09 | 1999-08-31 | Micron Technology, Inc. | Trench isolation region for semiconductor device |
US6150697A (en) | 1998-04-30 | 2000-11-21 | Denso Corporation | Semiconductor apparatus having high withstand voltage |
US6303969B1 (en) | 1998-05-01 | 2001-10-16 | Allen Tan | Schottky diode with dielectric trench |
US6063678A (en) | 1998-05-04 | 2000-05-16 | Xemod, Inc. | Fabrication of lateral RF MOS devices with enhanced RF properties |
DE19820223C1 (de) | 1998-05-06 | 1999-11-04 | Siemens Ag | Verfahren zum Herstellen einer Epitaxieschicht mit lateral veränderlicher Dotierung |
US6104054A (en) | 1998-05-13 | 2000-08-15 | Texas Instruments Incorporated | Space-efficient layout method to reduce the effect of substrate capacitance in dielectrically isolated process technologies |
US6015727A (en) | 1998-06-08 | 2000-01-18 | Wanlass; Frank M. | Damascene formation of borderless contact MOS transistors |
DE19828191C1 (de) | 1998-06-24 | 1999-07-29 | Siemens Ag | Lateral-Hochspannungstransistor |
KR100372103B1 (ko) | 1998-06-30 | 2003-03-31 | 주식회사 하이닉스반도체 | 반도체소자의소자분리방법 |
US6054365A (en) | 1998-07-13 | 2000-04-25 | International Rectifier Corp. | Process for filling deep trenches with polysilicon and oxide |
US6156611A (en) | 1998-07-20 | 2000-12-05 | Motorola, Inc. | Method of fabricating vertical FET with sidewall gate electrode |
JP4090518B2 (ja) | 1998-07-23 | 2008-05-28 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
JP4253374B2 (ja) | 1998-07-24 | 2009-04-08 | 千住金属工業株式会社 | プリント基板のはんだ付け方法および噴流はんだ槽 |
JP2000056281A (ja) | 1998-08-07 | 2000-02-25 | Mitsubishi Electric Corp | 光変調器とその製造方法 |
DE19839970C2 (de) | 1998-09-02 | 2000-11-02 | Siemens Ag | Randstruktur und Driftbereich für ein Halbleiterbauelement sowie Verfahren zu ihrer Herstellung |
US6316280B1 (en) | 1998-09-07 | 2001-11-13 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing semiconductor devices separated from a wafer |
JP3382163B2 (ja) | 1998-10-07 | 2003-03-04 | 株式会社東芝 | 電力用半導体装置 |
US7462910B1 (en) | 1998-10-14 | 2008-12-09 | International Rectifier Corporation | P-channel trench MOSFET structure |
DE19848828C2 (de) | 1998-10-22 | 2001-09-13 | Infineon Technologies Ag | Halbleiterbauelement mit kleiner Durchlaßspannung und hoher Sperrfähigkeit |
US5998833A (en) | 1998-10-26 | 1999-12-07 | North Carolina State University | Power semiconductor devices having improved high frequency switching and breakdown characteristics |
US6194741B1 (en) | 1998-11-03 | 2001-02-27 | International Rectifier Corp. | MOSgated trench type power semiconductor with silicon carbide substrate and increased gate breakdown voltage and reduced on-resistance |
US6096629A (en) | 1998-11-05 | 2000-08-01 | Taiwan Semiconductor Manufacturing Company | Uniform sidewall profile etch method for forming low contact leakage schottky diode contact |
JP3951522B2 (ja) | 1998-11-11 | 2007-08-01 | 富士電機デバイステクノロジー株式会社 | 超接合半導体素子 |
JP3799888B2 (ja) | 1998-11-12 | 2006-07-19 | 富士電機デバイステクノロジー株式会社 | 超接合半導体素子およびその製造方法 |
US6291856B1 (en) | 1998-11-12 | 2001-09-18 | Fuji Electric Co., Ltd. | Semiconductor device with alternating conductivity type layer and method of manufacturing the same |
JP2000156978A (ja) | 1998-11-17 | 2000-06-06 | Fuji Electric Co Ltd | ソフトスイッチング回路 |
US6156606A (en) | 1998-11-17 | 2000-12-05 | Siemens Aktiengesellschaft | Method of forming a trench capacitor using a rutile dielectric material |
US6084264A (en) | 1998-11-25 | 2000-07-04 | Siliconix Incorporated | Trench MOSFET having improved breakdown and on-resistance characteristics |
DE19854915C2 (de) | 1998-11-27 | 2002-09-05 | Infineon Technologies Ag | MOS-Feldeffekttransistor mit Hilfselektrode |
US6222229B1 (en) | 1999-02-18 | 2001-04-24 | Cree, Inc. | Self-aligned shield structure for realizing high frequency power MOSFET devices with improved reliability |
JP3751463B2 (ja) | 1999-03-23 | 2006-03-01 | 株式会社東芝 | 高耐圧半導体素子 |
DE19913375B4 (de) | 1999-03-24 | 2009-03-26 | Infineon Technologies Ag | Verfahren zur Herstellung einer MOS-Transistorstruktur |
JP3417336B2 (ja) | 1999-03-25 | 2003-06-16 | 関西日本電気株式会社 | 絶縁ゲート型半導体装置およびその製造方法 |
US6316806B1 (en) | 1999-03-31 | 2001-11-13 | Fairfield Semiconductor Corporation | Trench transistor with a self-aligned source |
US6188105B1 (en) | 1999-04-01 | 2001-02-13 | Intersil Corporation | High density MOS-gated power device and process for forming same |
TW425701B (en) | 1999-04-27 | 2001-03-11 | Taiwan Semiconductor Mfg | Manufacturing method of stack-type capacitor |
US6198127B1 (en) | 1999-05-19 | 2001-03-06 | Intersil Corporation | MOS-gated power device having extended trench and doping zone and process for forming same |
US6433385B1 (en) | 1999-05-19 | 2002-08-13 | Fairchild Semiconductor Corporation | MOS-gated power device having segmented trench and extended doping zone and process for forming same |
US6373098B1 (en) | 1999-05-25 | 2002-04-16 | Fairchild Semiconductor Corporation | Trench-gated device having trench walls formed by selective epitaxial growth and process for forming device |
US6291298B1 (en) | 1999-05-25 | 2001-09-18 | Advanced Analogic Technologies, Inc. | Process of manufacturing Trench gate semiconductor device having gate oxide layer with multiple thicknesses |
US6191447B1 (en) | 1999-05-28 | 2001-02-20 | Micro-Ohm Corporation | Power semiconductor devices that utilize tapered trench-based insulating regions to improve electric field profiles in highly doped drift region mesas and methods of forming same |
DE69938541D1 (de) | 1999-06-03 | 2008-05-29 | St Microelectronics Srl | Leistungshalbleiteranordnung mit einer Randabschlussstruktur mit einem Spannungsteiler |
KR100773380B1 (ko) | 1999-06-03 | 2007-11-06 | 제네럴 세미컨덕터, 인코포레이티드 | 전력 mosfet, 이를 형성하는 방법, 및 이 방법에 의해 형성되는 다른 전력 mosfet |
JP3851744B2 (ja) | 1999-06-28 | 2006-11-29 | 株式会社東芝 | 半導体装置の製造方法 |
GB9917099D0 (en) | 1999-07-22 | 1999-09-22 | Koninkl Philips Electronics Nv | Cellular trench-gate field-effect transistors |
JP3971062B2 (ja) | 1999-07-29 | 2007-09-05 | 株式会社東芝 | 高耐圧半導体装置 |
TW411553B (en) | 1999-08-04 | 2000-11-11 | Mosel Vitelic Inc | Method for forming curved oxide on bottom of trench |
JP4774580B2 (ja) | 1999-08-23 | 2011-09-14 | 富士電機株式会社 | 超接合半導体素子 |
US6077733A (en) | 1999-09-03 | 2000-06-20 | Taiwan Semiconductor Manufacturing Company | Method of manufacturing self-aligned T-shaped gate through dual damascene |
US6566804B1 (en) | 1999-09-07 | 2003-05-20 | Motorola, Inc. | Field emission device and method of operation |
JP3507732B2 (ja) | 1999-09-30 | 2004-03-15 | 株式会社東芝 | 半導体装置 |
US6222233B1 (en) | 1999-10-04 | 2001-04-24 | Xemod, Inc. | Lateral RF MOS device with improved drain structure |
US6103619A (en) | 1999-10-08 | 2000-08-15 | United Microelectronics Corp. | Method of forming a dual damascene structure on a semiconductor wafer |
JP4450122B2 (ja) | 1999-11-17 | 2010-04-14 | 株式会社デンソー | 炭化珪素半導体装置 |
US6184092B1 (en) | 1999-11-23 | 2001-02-06 | Mosel Vitelic Inc. | Self-aligned contact for trench DMOS transistors |
US6461918B1 (en) | 1999-12-20 | 2002-10-08 | Fairchild Semiconductor Corporation | Power MOS device with improved gate charge performance |
US6285060B1 (en) | 1999-12-30 | 2001-09-04 | Siliconix Incorporated | Barrier accumulation-mode MOSFET |
US6346469B1 (en) | 2000-01-03 | 2002-02-12 | Motorola, Inc. | Semiconductor device and a process for forming the semiconductor device |
JP2001192174A (ja) | 2000-01-12 | 2001-07-17 | Occ Corp | 誘導巻取り装置 |
JP4765012B2 (ja) | 2000-02-09 | 2011-09-07 | 富士電機株式会社 | 半導体装置及びその製造方法 |
US6376878B1 (en) | 2000-02-11 | 2002-04-23 | Fairchild Semiconductor Corporation | MOS-gated devices with alternating zones of conductivity |
GB0003184D0 (en) | 2000-02-12 | 2000-04-05 | Koninkl Philips Electronics Nv | A semiconductor device and a method of fabricating material for a semiconductor device |
US6274420B1 (en) | 2000-02-23 | 2001-08-14 | Advanced Micro Devices, Inc. | Sti (shallow trench isolation) structures for minimizing leakage current through drain and source silicides |
US6271100B1 (en) | 2000-02-24 | 2001-08-07 | International Business Machines Corporation | Chemically enhanced anneal for removing trench stress resulting in improved bipolar yield |
JP2001244461A (ja) | 2000-02-28 | 2001-09-07 | Toyota Central Res & Dev Lab Inc | 縦型半導体装置 |
GB0005650D0 (en) | 2000-03-10 | 2000-05-03 | Koninkl Philips Electronics Nv | Field-effect semiconductor devices |
US6246090B1 (en) | 2000-03-14 | 2001-06-12 | Intersil Corporation | Power trench transistor device source region formation using silicon spacer |
AU5172001A (en) | 2000-03-17 | 2001-10-03 | Gen Semiconductor Inc | Trench dmos transistor having a double gate structure |
JP3636345B2 (ja) | 2000-03-17 | 2005-04-06 | 富士電機デバイステクノロジー株式会社 | 半導体素子および半導体素子の製造方法 |
TW439176B (en) | 2000-03-17 | 2001-06-07 | United Microelectronics Corp | Manufacturing method of capacitors |
US6376315B1 (en) | 2000-03-31 | 2002-04-23 | General Semiconductor, Inc. | Method of forming a trench DMOS having reduced threshold voltage |
US6392290B1 (en) | 2000-04-07 | 2002-05-21 | Siliconix Incorporated | Vertical structure for semiconductor wafer-level chip scale packages |
JP4534303B2 (ja) | 2000-04-27 | 2010-09-01 | 富士電機システムズ株式会社 | 横型超接合半導体素子 |
JP4240752B2 (ja) | 2000-05-01 | 2009-03-18 | 富士電機デバイステクノロジー株式会社 | 半導体装置 |
US6509240B2 (en) | 2000-05-15 | 2003-01-21 | International Rectifier Corporation | Angle implant process for cellular deep trench sidewall doping |
DE10026924A1 (de) | 2000-05-30 | 2001-12-20 | Infineon Technologies Ag | Kompensationsbauelement |
US6479352B2 (en) | 2000-06-02 | 2002-11-12 | General Semiconductor, Inc. | Method of fabricating high voltage power MOSFET having low on-resistance |
JP3798951B2 (ja) | 2000-06-07 | 2006-07-19 | シャープ株式会社 | 回路内蔵受光素子、その製造方法および該受光素子を用いた光学装置 |
EP1170803A3 (en) | 2000-06-08 | 2002-10-09 | Siliconix Incorporated | Trench gate MOSFET and method of making the same |
US6472678B1 (en) | 2000-06-16 | 2002-10-29 | General Semiconductor, Inc. | Trench MOSFET with double-diffused body profile |
JP3833903B2 (ja) | 2000-07-11 | 2006-10-18 | 株式会社東芝 | 半導体装置の製造方法 |
US6555895B1 (en) | 2000-07-17 | 2003-04-29 | General Semiconductor, Inc. | Devices and methods for addressing optical edge effects in connection with etched trenches |
US6921939B2 (en) | 2000-07-20 | 2005-07-26 | Fairchild Semiconductor Corporation | Power MOSFET and method for forming same using a self-aligned body implant |
JP2002043571A (ja) | 2000-07-28 | 2002-02-08 | Nec Kansai Ltd | 半導体装置 |
US6437386B1 (en) | 2000-08-16 | 2002-08-20 | Fairchild Semiconductor Corporation | Method for creating thick oxide on the bottom surface of a trench structure in silicon |
US6472708B1 (en) | 2000-08-31 | 2002-10-29 | General Semiconductor, Inc. | Trench MOSFET with structure having low gate charge |
US6355501B1 (en) | 2000-09-21 | 2002-03-12 | International Business Machines Corporation | Three-dimensional chip stacking assembly |
FR2816113A1 (fr) | 2000-10-31 | 2002-05-03 | St Microelectronics Sa | Procede de realisation d'une zone dopee dans du carbure de silicium et application a une diode schottky |
EP1205980A1 (en) | 2000-11-07 | 2002-05-15 | Infineon Technologies AG | A method for forming a field effect transistor in a semiconductor substrate |
US6362112B1 (en) | 2000-11-08 | 2002-03-26 | Fabtech, Inc. | Single step etched moat |
US6608350B2 (en) | 2000-12-07 | 2003-08-19 | International Rectifier Corporation | High voltage vertical conduction superjunction semiconductor device |
US6677641B2 (en) * | 2001-10-17 | 2004-01-13 | Fairchild Semiconductor Corporation | Semiconductor structure with improved smaller forward voltage loss and higher blocking capability |
US6713813B2 (en) | 2001-01-30 | 2004-03-30 | Fairchild Semiconductor Corporation | Field effect transistor having a lateral depletion structure |
US6821824B2 (en) | 2001-02-21 | 2004-11-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
TW543146B (en) | 2001-03-09 | 2003-07-21 | Fairchild Semiconductor | Ultra dense trench-gated power device with the reduced drain-source feedback capacitance and miller charge |
KR100393201B1 (ko) | 2001-04-16 | 2003-07-31 | 페어차일드코리아반도체 주식회사 | 낮은 온 저항과 높은 브레이크다운 전압을 갖는 고전압수평형 디모스 트랜지스터 |
DE10214160B4 (de) * | 2002-03-28 | 2014-10-09 | Infineon Technologies Ag | Halbleiteranordnung mit Schottky-Kontakt |
JP3312905B2 (ja) | 2001-06-25 | 2002-08-12 | 株式会社リコー | 画像形成装置 |
JP2003017701A (ja) * | 2001-07-04 | 2003-01-17 | Denso Corp | 半導体装置 |
US20030015756A1 (en) | 2001-07-23 | 2003-01-23 | Motorola, Inc. | Semiconductor structure for integrated control of an active subcircuit and process for fabrication |
US6875671B2 (en) | 2001-09-12 | 2005-04-05 | Reveo, Inc. | Method of fabricating vertical integrated circuits |
US6465304B1 (en) | 2001-10-04 | 2002-10-15 | General Semiconductor, Inc. | Method for fabricating a power semiconductor device having a floating island voltage sustaining layer |
AU2003228073A1 (en) | 2002-05-31 | 2003-12-19 | Koninklijke Philips Electronics N.V. | Trench-gate semiconductor device,corresponding module and apparatus ,and method of operating the device |
JP4158453B2 (ja) | 2002-08-22 | 2008-10-01 | 株式会社デンソー | 半導体装置及びその製造方法 |
GB0229212D0 (en) * | 2002-12-14 | 2003-01-22 | Koninkl Philips Electronics Nv | Method of manufacture of a trench semiconductor device |
DE10259373B4 (de) | 2002-12-18 | 2012-03-22 | Infineon Technologies Ag | Überstromfeste Schottkydiode mit niedrigem Sperrstrom |
JP4166102B2 (ja) * | 2003-02-26 | 2008-10-15 | トヨタ自動車株式会社 | 高耐圧電界効果型半導体装置 |
GB0312512D0 (en) * | 2003-05-31 | 2003-07-09 | Koninkl Philips Electronics Nv | Termination structures for semiconductor devices and the manufacture thereof |
JP4799829B2 (ja) * | 2003-08-27 | 2011-10-26 | 三菱電機株式会社 | 絶縁ゲート型トランジスタ及びインバータ回路 |
CN103199017B (zh) * | 2003-12-30 | 2016-08-03 | 飞兆半导体公司 | 形成掩埋导电层方法、材料厚度控制法、形成晶体管方法 |
US7405452B2 (en) | 2004-02-02 | 2008-07-29 | Hamza Yilmaz | Semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics |
US6951112B2 (en) | 2004-02-10 | 2005-10-04 | General Electric Company | Methods and apparatus for assembling gas turbine engines |
US20050199918A1 (en) | 2004-03-15 | 2005-09-15 | Daniel Calafut | Optimized trench power MOSFET with integrated schottky diode |
JP4176734B2 (ja) * | 2004-05-14 | 2008-11-05 | 株式会社東芝 | トレンチmosfet |
DE102004057235B4 (de) | 2004-11-26 | 2007-12-27 | Infineon Technologies Ag | Vertikaler Trenchtransistor und Verfahren zu dessen Herstellung |
CN101882583A (zh) | 2005-04-06 | 2010-11-10 | 飞兆半导体公司 | 沟栅场效应晶体管及其形成方法 |
CN101542731B (zh) | 2005-05-26 | 2012-07-11 | 飞兆半导体公司 | 沟槽栅场效应晶体管及其制造方法 |
US7446374B2 (en) | 2006-03-24 | 2008-11-04 | Fairchild Semiconductor Corporation | High density trench FET with integrated Schottky diode and method of manufacture |
US7768075B2 (en) | 2006-04-06 | 2010-08-03 | Fairchild Semiconductor Corporation | Semiconductor die packages using thin dies and metal substrates |
-
2006
- 2006-03-24 US US11/388,790 patent/US7446374B2/en active Active
-
2007
- 2007-03-08 WO PCT/US2007/063612 patent/WO2007112187A2/en active Application Filing
- 2007-03-08 AT AT0914007A patent/AT505583A2/de not_active Application Discontinuation
- 2007-03-08 JP JP2009501633A patent/JP2009531836A/ja active Pending
- 2007-03-08 DE DE112007000700.1T patent/DE112007000700B4/de active Active
- 2007-03-08 KR KR1020087024224A patent/KR101361239B1/ko active IP Right Grant
- 2007-03-08 CN CN2007800190574A patent/CN101454882B/zh active Active
- 2007-03-19 TW TW096109324A patent/TWI443826B/zh active
-
2008
- 2008-10-10 US US12/249,889 patent/US7713822B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6562634B2 (en) * | 1998-08-31 | 2003-05-13 | International Business Machines Corporation | Diode connected to a magnetic tunnel junction and self aligned with a metallic conductor and method of forming the same |
US20050167742A1 (en) * | 2001-01-30 | 2005-08-04 | Fairchild Semiconductor Corp. | Power semiconductor devices and methods of manufacture |
US6878994B2 (en) * | 2002-08-22 | 2005-04-12 | International Rectifier Corporation | MOSgated device with accumulated channel region and Schottky contact |
US20050218472A1 (en) * | 2004-03-29 | 2005-10-06 | Sanyo Electric Co., Ltd | Semiconductor device manufacturing method thereof |
US20050285238A1 (en) * | 2004-06-24 | 2005-12-29 | Joshi Rajeev D | Integrated transistor module and method of fabricating same |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7713822B2 (en) | 2006-03-24 | 2010-05-11 | Fairchild Semiconductor Corporation | Method of forming high density trench FET with integrated Schottky diode |
JP2009253139A (ja) * | 2008-04-09 | 2009-10-29 | Renesas Technology Corp | 半導体装置およびその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US7713822B2 (en) | 2010-05-11 |
AT505583A2 (de) | 2009-02-15 |
CN101454882B (zh) | 2011-08-31 |
TW200742079A (en) | 2007-11-01 |
CN101454882A (zh) | 2009-06-10 |
US20090035900A1 (en) | 2009-02-05 |
US20070221952A1 (en) | 2007-09-27 |
DE112007000700T5 (de) | 2009-01-29 |
KR20090003306A (ko) | 2009-01-09 |
US7446374B2 (en) | 2008-11-04 |
WO2007112187A3 (en) | 2008-04-17 |
TWI443826B (zh) | 2014-07-01 |
KR101361239B1 (ko) | 2014-02-11 |
JP2009531836A (ja) | 2009-09-03 |
DE112007000700B4 (de) | 2018-01-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7446374B2 (en) | High density trench FET with integrated Schottky diode and method of manufacture | |
US8686493B2 (en) | High density FET with integrated Schottky | |
US11888047B2 (en) | Lateral transistors and methods with low-voltage-drop shunt to body diode | |
CN209087847U (zh) | 半导体器件结构 | |
US9461127B2 (en) | Vertical power MOSFET having planar channel and its method of fabrication | |
US8742401B2 (en) | Field effect transistor with gated and non-gated trenches | |
US20180261666A1 (en) | Vertical power mos-gated device with high dopant concentration n-well below p-well and with floating p-islands | |
US8324053B2 (en) | High voltage MOSFET diode reverse recovery by minimizing P-body charges | |
US7436022B2 (en) | Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout | |
US8110869B2 (en) | Planar SRFET using no additional masks and layout method | |
US6593620B1 (en) | Trench DMOS transistor with embedded trench schottky rectifier | |
US8836015B2 (en) | Planar SRFET using no additional masks and layout method | |
WO2004107448A1 (en) | Semiconductor device having an edge termination structure and method of manufacture thereof | |
EP2602829A1 (en) | Trench-gate resurf semiconductor device and manufacturing method | |
US11004839B1 (en) | Trench power MOSFET with integrated-schottky in non-active area |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 200780019057.4 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 07758188 Country of ref document: EP Kind code of ref document: A2 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2009501633 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1020087024224 Country of ref document: KR |
|
ENP | Entry into the national phase |
Ref document number: 91122007 Country of ref document: AT Kind code of ref document: A |
|
RET | De translation (de og part 6b) |
Ref document number: 112007000700 Country of ref document: DE Date of ref document: 20090129 Kind code of ref document: P |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 07758188 Country of ref document: EP Kind code of ref document: A2 |