DE69525003T2 - Verfahren zum Herstellen eines DMOS-Transistors mit Grabenstruktur unter Verwendung von sieben Masken - Google Patents

Verfahren zum Herstellen eines DMOS-Transistors mit Grabenstruktur unter Verwendung von sieben Masken

Info

Publication number
DE69525003T2
DE69525003T2 DE69525003T DE69525003T DE69525003T2 DE 69525003 T2 DE69525003 T2 DE 69525003T2 DE 69525003 T DE69525003 T DE 69525003T DE 69525003 T DE69525003 T DE 69525003T DE 69525003 T2 DE69525003 T2 DE 69525003T2
Authority
DE
Germany
Prior art keywords
masks
trench
manufacturing
dmos transistor
dmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69525003T
Other languages
English (en)
Other versions
DE69525003D1 (de
Inventor
Fwu-Iuan Hshieh
Mike F Chang
Yueh-Se Ho
King Owyang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vishay Siliconix Inc
Original Assignee
Siliconix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconix Inc filed Critical Siliconix Inc
Publication of DE69525003D1 publication Critical patent/DE69525003D1/de
Application granted granted Critical
Publication of DE69525003T2 publication Critical patent/DE69525003T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402Field plates
    • H01L29/404Multiple field plate structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402Field plates
    • H01L29/407Recessed field plates, e.g. trench field plates, buried field plates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Local Oxidation Of Silicon (AREA)
DE69525003T 1994-08-15 1995-08-10 Verfahren zum Herstellen eines DMOS-Transistors mit Grabenstruktur unter Verwendung von sieben Masken Expired - Lifetime DE69525003T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US29032394A 1994-08-15 1994-08-15

Publications (2)

Publication Number Publication Date
DE69525003D1 DE69525003D1 (de) 2002-02-21
DE69525003T2 true DE69525003T2 (de) 2003-10-09

Family

ID=23115485

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69525003T Expired - Lifetime DE69525003T2 (de) 1994-08-15 1995-08-10 Verfahren zum Herstellen eines DMOS-Transistors mit Grabenstruktur unter Verwendung von sieben Masken

Country Status (4)

Country Link
US (2) US5639676A (de)
EP (1) EP0698919B1 (de)
JP (2) JPH08204194A (de)
DE (1) DE69525003T2 (de)

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US7745289B2 (en) 2000-08-16 2010-06-29 Fairchild Semiconductor Corporation Method of forming a FET having ultra-low on-resistance and low gate charge
JP4614522B2 (ja) * 2000-10-25 2011-01-19 富士通セミコンダクター株式会社 半導体装置及びその製造方法
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US6468870B1 (en) 2000-12-26 2002-10-22 Taiwan Semiconductor Manufacturing Company Method of fabricating a LDMOS transistor
US6710403B2 (en) * 2002-07-30 2004-03-23 Fairchild Semiconductor Corporation Dual trench power MOSFET
US6916745B2 (en) 2003-05-20 2005-07-12 Fairchild Semiconductor Corporation Structure and method for forming a trench MOSFET having self-aligned features
US7132712B2 (en) 2002-11-05 2006-11-07 Fairchild Semiconductor Corporation Trench structure having one or more diodes embedded therein adjacent a PN junction
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US6818947B2 (en) 2002-09-19 2004-11-16 Fairchild Semiconductor Corporation Buried gate-field termination structure
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US7576388B1 (en) 2002-10-03 2009-08-18 Fairchild Semiconductor Corporation Trench-gate LDMOS structures
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US6710418B1 (en) 2002-10-11 2004-03-23 Fairchild Semiconductor Corporation Schottky rectifier with insulation-filled trenches and method of forming the same
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US6992352B2 (en) 2003-05-15 2006-01-31 Analog Power Limited Trenched DMOS devices and methods and processes for making same
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JP4860102B2 (ja) * 2003-06-26 2012-01-25 ルネサスエレクトロニクス株式会社 半導体装置
US20050259368A1 (en) * 2003-11-12 2005-11-24 Ted Letavic Method and apparatus of terminating a high voltage solid state device
KR100994719B1 (ko) 2003-11-28 2010-11-16 페어차일드코리아반도체 주식회사 슈퍼정션 반도체장치
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US7045857B2 (en) * 2004-03-26 2006-05-16 Siliconix Incorporated Termination for trench MIS device having implanted drain-drift region
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US7504306B2 (en) 2005-04-06 2009-03-17 Fairchild Semiconductor Corporation Method of forming trench gate field effect transistor with recessed mesas
JP2006013556A (ja) * 2005-09-26 2006-01-12 Renesas Technology Corp 半導体装置
US7446374B2 (en) 2006-03-24 2008-11-04 Fairchild Semiconductor Corporation High density trench FET with integrated Schottky diode and method of manufacture
US7319256B1 (en) 2006-06-19 2008-01-15 Fairchild Semiconductor Corporation Shielded gate trench FET with the shield and gate electrodes being connected together
US20080206944A1 (en) * 2007-02-23 2008-08-28 Pan-Jit International Inc. Method for fabricating trench DMOS transistors and schottky elements
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US7772668B2 (en) 2007-12-26 2010-08-10 Fairchild Semiconductor Corporation Shielded gate trench FET with multiple channels
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US8174067B2 (en) * 2008-12-08 2012-05-08 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
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US8673700B2 (en) 2011-04-27 2014-03-18 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
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KR20180097510A (ko) 2015-10-01 2018-08-31 디3 세미컨덕터 엘엘씨 수직 전력 반도체 디바이스 내의 소스-게이트 영역 구조물
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Also Published As

Publication number Publication date
US5639676A (en) 1997-06-17
JPH08204194A (ja) 1996-08-09
DE69525003D1 (de) 2002-02-21
EP0698919B1 (de) 2002-01-16
EP0698919A2 (de) 1996-02-28
US5578851A (en) 1996-11-26
EP0698919A3 (de) 1996-05-01
JP2007281515A (ja) 2007-10-25

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