KR940006702B1 - 모스패트의 제조방법 - Google Patents

모스패트의 제조방법 Download PDF

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KR940006702B1
KR940006702B1 KR1019910009872A KR910009872A KR940006702B1 KR 940006702 B1 KR940006702 B1 KR 940006702B1 KR 1019910009872 A KR1019910009872 A KR 1019910009872A KR 910009872 A KR910009872 A KR 910009872A KR 940006702 B1 KR940006702 B1 KR 940006702B1
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oxide film
gate electrode
source
gate
film
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KR1019910009872A
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KR930001477A (ko
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강대관
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금성일렉트론 주식회사
문정환
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Priority to KR1019910009872A priority Critical patent/KR940006702B1/ko
Priority to TW081104392A priority patent/TW363228B/zh
Priority to JP17602692A priority patent/JP3223329B2/ja
Priority to US07/897,460 priority patent/US5219777A/en
Priority to DE4219319A priority patent/DE4219319B4/de
Publication of KR930001477A publication Critical patent/KR930001477A/ko
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/66583—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Ceramic Engineering (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

내용 없음.

Description

모스패트의 제조방법
제 1 도는 종래 모스패트의 이온주입방법을 나타낸 단면도.
제 2 도는 본 발명 모스패트의 공정단면도.
제 3 도는 본 발명에 따른 이온주입시의 도핑농도를 나타낸 도면.
* 도면의 주요부분에 대한 부호의 설명
1 : 기판 2 : 필드산화막
3 : 패드산화막 4 : 질화막
5 : 산화막 6 : P/R
7,9 : 폴리실리콘 8 : 게이트산화막
10 : 측벽 11 : 메탈
본 발명은 모스패트의 제조방법에 관한 것으로, 특히 서브 미크론급 모스패트에 적당하도록 한 것이다. 종래의 모스패트 제조공정중 임계전압조절이나 펀치쓰로우(Punch Through)방지를 위한 이온주입방법은 제1(a)도에 도시된 바와 같이 기판(l)의 액티브영역 전면에 저농도 P형 불순물이온을 주입하는 것이 있고, 제1(b)도에 도시된 바와 같이 게이트(12)에치 후 펀치쓰로우방지를 위한 이온주입을 실시하여 LDD(Lightly Dopes Drain)구조를 이루는 고농도 n형과 저농도 n형 불순물확산영역 밑부분에만 저농도 p형 불순물이온이 형성되게 하는 것이 있으며, 제1(c)도와 같이 채널이 형성되는 게이트의 아래에만 저농도 p형 불순물이온을 주입하는 것이 있다.
그러나 상기에서 제1(a)도와 같은 경우는 저농도 p형 불순물이온이 주입되는 영역이 넓어 정션 커폐시턴스가 크며 모빌리티(Mobility)도 감소하게 된다.
그리고 제1(b)도와 같은 경우 또한 정션 커폐시터가 크고 벌크(Bulk) 펀치쓰로우 방지가 어려운 결점이 있으며, 제1(c)도와 같은 경우는 모빌리티의 감소가 큰 결점이 있다.
본 발명은 이와 같은 종래의 결점을 해결하기 위한 것으로 벌크 펀치쓰로우(Bulk Punch Through)를 방지하고 정션 커패시턴스를 줄임과 아울러 모빌리티를 증가시킬 수 있는 모스패트의 제조방법을 제공하는데 그 목적이 있다.
이하에서 이와 같은 목적을 달성하기 위한 본 발명의 실시예를 첨부된 도면 제2도에 의해 상세히 설명하면 다음과 같다.
먼저 (a)와 같이 P형 기판(1)에 필드산화막(2)을 형성하여 액티브영역과 필드영역을 정의하고, (b)와 같이 패드산화막(3)과 질화막(4) 그리고 산화막(5)을 차례로 형성한 후 P/R(6)을 사용하여 게이트 전극 형성영역의 상기 산화막(5)을 식각하고 P/R(6)을 제거한다.
그리고 (c)와 같이 폴리실리콘(7)을 증착한 후 에치하여 산화막(5) 측면에 폴리실리콘(7) 측벽을 형성하고, (d)와 같이 상기 측벽을 이용하여 질화막(4)을 에치하고 폴리실리콘(7) 측벽을 제거한 후 펀치쓰로우(Punch Through) 이온을 주입한다.
다음에 (e)와 같이 산호막(5)이 덮히지 않은 부분의 질화막(4)을 식각하여 제거하는 데 이때 패드산화막(3)도 동시에 제거한다.
이어서 패드산화막(3)이 제거된 부분에 게이트 산화막(8)을 형성하고 폴리실리콘(9)을 증착한 후 산화막(5) 부분까지 상기 폴리실리콘(9)을 에치백하여, 게이트전극을 형성하고, 다음에 상기 산화막(5)과 질화막(4)을 제거하여 (f)와 같이 폴리실리콘(9)이 남게 한다.
또한, 이후 공정은 (g)와 같이 통상의 공정에 의해 게이트 전극을 마스크로 하여 저농도 n형 이온주입한후, 측멱(10)을 형성하고, 고농도 n형 이온주입하여 LDD구조를 갖는 소오스 및 드레인영역을 형성한 다음 메탈(11)을 증착하므로 소자를 완성시킨다.
제3도 (a),(b)는 제2(d)도의 구조에서 펀치쓰로우 이온주입시의 도핑농도를 나타낸 것으로, 소오스/드레인이 가까운 게이트쪽은 농도피크가 표면에 있게 되고 중앙부분은 피크가 표면에서 안쪽에 존재하게 된다.
따라서, 제3(b)도에서 a부분이 임계전압조절 및 펀치쓰로우방지를 하게 되며, b부분이 벌크 펀치쓰로우를 방지하게 된다.
이상에서 설명한 바와 같은 본 발명은 채널이온주입부분을 측벽을 이용하여 마스킹층을 남기는 부분과 제거하는 부분으로 구분하여 게이트 에치쪽의 P형 농도는 표면이 피크가 되도록 함과 아울러 중앙부분은 농도의 피크가 벌크쪽에서 존재하도록 하므로 벌크 펀치쓰로우를 방지하면서 정션 커패시턴스를 줄이고 모빌리티를 증가시킬 수 있는 장점이 있다.

Claims (2)

  1. P형 기판(1)에 액티브영역과 필드영역을 한정하는 공정과, 상기 전표면에 패드산화막(3), 질화막(4), 산화막(5)을 차례로 증착하고 게이트 전극이 형성될 부분의 상기 산화막(5)을 선택적으로 제거하는 공정과, 폴리실리콘(7)을 증착한 후 에치하여 산화막(5) 측면에 폴리실리콘 측벽을 형성하고 상기 측벽을 이용하여 질화막(4)을 선택적으로 제거한 다음 상기 폴리실리콘 측벽을 제거하고 이온주입하는 공정과, 상기 산화막(5)이 덮지 않은 부분의 질화막(4)과 패드산화막(3)을 제거하고 게이트 산화막(8)을 형성하는 공정과, 폴리실리콘(9)을 증착하고 산화막(5) 윗면까지 에치백하여 게이트 전극을 형성한 뒤 질화막(4)과 산화막(5)을 제거하며 이어 LDD 구조의 소오스 및 드레인 영역을 형성하는 공정을 차례로 실시하여서 이루어짐을 특징으로 하는 모스패트의 제조방법.
  2. 제1도전형 반도체기판, 제1도전형 반도체기판상에 게이트 절연막을 사이에 두고 형성되는 게이트 전극, 상기 게이트 전극의 양측 반도체기판상에 LDD구조로 형성되는 제2도전형 소오스 및 드레인영역, 소오스 및 드레인영역에 가까운 게이트전극의 기판표면에 소오스 및 드레인 사이의 기판 중앙부분에 형셩되는 펀치쓰로우 방지용 저농도 제1도전형 불순물영역을 포함하여 이루어짐을 특징으로 하는 모스패트의 제조방법.
KR1019910009872A 1991-06-14 1991-06-14 모스패트의 제조방법 KR940006702B1 (ko)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1019910009872A KR940006702B1 (ko) 1991-06-14 1991-06-14 모스패트의 제조방법
TW081104392A TW363228B (en) 1991-06-14 1992-06-03 Metal oxide semiconductor field effect transistor and method of making the same
JP17602692A JP3223329B2 (ja) 1991-06-14 1992-06-11 Ｍｏｓｆｅｔの製造方法
US07/897,460 US5219777A (en) 1991-06-14 1992-06-11 Metal oxide semiconductor field effect transistor and method of making the same
DE4219319A DE4219319B4 (de) 1991-06-14 1992-06-12 MOS-FET und Herstellungsverfahren dafür

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Application Number Priority Date Filing Date Title
KR1019910009872A KR940006702B1 (ko) 1991-06-14 1991-06-14 모스패트의 제조방법

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KR930001477A KR930001477A (ko) 1993-01-16
KR940006702B1 true KR940006702B1 (ko) 1994-07-25

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