NL8602047A - Isolatiestructuur in een mos-inrichting en een werkwijze om dit te bereiden. - Google Patents
Isolatiestructuur in een mos-inrichting en een werkwijze om dit te bereiden. Download PDFInfo
- Publication number
- NL8602047A NL8602047A NL8602047A NL8602047A NL8602047A NL 8602047 A NL8602047 A NL 8602047A NL 8602047 A NL8602047 A NL 8602047A NL 8602047 A NL8602047 A NL 8602047A NL 8602047 A NL8602047 A NL 8602047A
- Authority
- NL
- Netherlands
- Prior art keywords
- silicon
- layer
- substrate
- oxide
- silicon oxide
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 55
- 238000009413 insulation Methods 0.000 title description 4
- 239000010410 layer Substances 0.000 claims description 92
- 229910052710 silicon Inorganic materials 0.000 claims description 53
- 239000010703 silicon Substances 0.000 claims description 53
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 51
- 239000000758 substrate Substances 0.000 claims description 42
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 34
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 30
- 230000008569 process Effects 0.000 claims description 29
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 20
- 230000000873 masking effect Effects 0.000 claims description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 20
- 230000007704 transition Effects 0.000 claims description 18
- 239000002344 surface layer Substances 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 239000013078 crystal Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 7
- 230000002441 reversible effect Effects 0.000 claims description 5
- 238000002360 preparation method Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 230000008030 elimination Effects 0.000 claims description 2
- 238000003379 elimination reaction Methods 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 238000000206 photolithography Methods 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 description 24
- 238000005755 formation reaction Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 210000003323 beak Anatomy 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 238000009388 chemical precipitation Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 239000012808 vapor phase Substances 0.000 description 4
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 230000036039 immunity Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000036961 partial effect Effects 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 230000002829 reductive effect Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000002485 combustion reaction Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000010849 ion bombardment Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 235000011007 phosphoric acid Nutrition 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 238000001556 precipitation Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 101100138673 Arabidopsis thaliana NPF3.1 gene Proteins 0.000 description 1
- 229910003818 SiH2Cl2 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000009933 burial Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76221—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO with a plurality of successive local oxidation steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/975—Substrate or mask aligning feature
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT2199485 | 1985-08-28 | ||
IT21994/85A IT1200725B (it) | 1985-08-28 | 1985-08-28 | Struttura di isolamento in dispositivi mos e procedimento di preparazione della stessa |
Publications (1)
Publication Number | Publication Date |
---|---|
NL8602047A true NL8602047A (nl) | 1987-03-16 |
Family
ID=11189929
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
NL8602047A NL8602047A (nl) | 1985-08-28 | 1986-08-11 | Isolatiestructuur in een mos-inrichting en een werkwijze om dit te bereiden. |
Country Status (7)
Country | Link |
---|---|
US (1) | US4868136A (fr) |
JP (1) | JPH0821613B2 (fr) |
DE (1) | DE3628488C2 (fr) |
FR (1) | FR2586860B1 (fr) |
GB (1) | GB2179788B (fr) |
IT (1) | IT1200725B (fr) |
NL (1) | NL8602047A (fr) |
Families Citing this family (43)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4968640A (en) * | 1987-02-10 | 1990-11-06 | Industrial Technology Research Institute | Isolation structures for integrated circuits |
US4981813A (en) * | 1987-02-24 | 1991-01-01 | Sgs-Thomson Microelectronics, Inc. | Pad oxide protect sealed interface isolation process |
JPS6430248A (en) * | 1987-07-27 | 1989-02-01 | Hitachi Ltd | Formation of on-the-trench insulation film |
US4906585A (en) * | 1987-08-04 | 1990-03-06 | Siemens Aktiengesellschaft | Method for manufacturing wells for CMOS transistor circuits separated by insulating trenches |
JPH02151050A (ja) * | 1988-12-01 | 1990-06-11 | Nec Corp | 半導体装置 |
US5256592A (en) * | 1989-10-20 | 1993-10-26 | Oki Electric Industry Co., Ltd. | Method for fabricating a semiconductor integrated circuit device |
US5120675A (en) * | 1990-06-01 | 1992-06-09 | Texas Instruments Incorporated | Method for forming a trench within a semiconductor layer of material |
JP3134344B2 (ja) * | 1991-05-17 | 2001-02-13 | 日本電気株式会社 | 半導体装置 |
US5236853A (en) * | 1992-02-21 | 1993-08-17 | United Microelectronics Corporation | Self-aligned double density polysilicon lines for ROM and EPROM |
US5439842A (en) * | 1992-09-21 | 1995-08-08 | Siliconix Incorporated | Low temperature oxide layer over field implant mask |
US5358892A (en) * | 1993-02-11 | 1994-10-25 | Micron Semiconductor, Inc. | Etch stop useful in avoiding substrate pitting with poly buffered locos |
DE69434736D1 (de) * | 1993-08-31 | 2006-06-22 | St Microelectronics Inc | Isolationsstruktur und Verfahren zur Herstellung |
US5372968A (en) * | 1993-09-27 | 1994-12-13 | United Microelectronics Corporation | Planarized local oxidation by trench-around technology |
US5366925A (en) * | 1993-09-27 | 1994-11-22 | United Microelectronics Corporation | Local oxidation of silicon by using aluminum spiking technology |
US5308786A (en) * | 1993-09-27 | 1994-05-03 | United Microelectronics Corporation | Trench isolation for both large and small areas by means of silicon nodules after metal etching |
US5294562A (en) * | 1993-09-27 | 1994-03-15 | United Microelectronics Corporation | Trench isolation with global planarization using flood exposure |
US5330924A (en) * | 1993-11-19 | 1994-07-19 | United Microelectronics Corporation | Method of making 0.6 micrometer word line pitch ROM cell by 0.6 micrometer technology |
US5543343A (en) * | 1993-12-22 | 1996-08-06 | Sgs-Thomson Microelectronics, Inc. | Method fabricating an integrated circuit |
KR960014455B1 (ko) * | 1994-01-12 | 1996-10-15 | 금성일렉트론 주식회사 | 반도체장치의 및 그 제조방법 |
US5438016A (en) * | 1994-03-02 | 1995-08-01 | Micron Semiconductor, Inc. | Method of semiconductor device isolation employing polysilicon layer for field oxide formation |
US5472904A (en) * | 1994-03-02 | 1995-12-05 | Micron Technology, Inc. | Thermal trench isolation |
KR0156115B1 (ko) * | 1994-06-16 | 1998-12-01 | 문정환 | 반도체 소자의 격리막 구조 및 형성방법 |
KR0148602B1 (ko) * | 1994-11-23 | 1998-12-01 | 양승택 | 반도체 장치의 소자 격리방법 |
US5733794A (en) * | 1995-02-06 | 1998-03-31 | Motorola, Inc. | Process for forming a semiconductor device with ESD protection |
JP2715972B2 (ja) * | 1995-03-04 | 1998-02-18 | 日本電気株式会社 | 半導体装置の製造方法 |
KR0151049B1 (ko) * | 1995-05-29 | 1998-12-01 | 김광호 | 반도체장치의 소자분리방법 |
US5861339A (en) * | 1995-10-27 | 1999-01-19 | Integrated Device Technology, Inc. | Recessed isolation with double oxidation |
KR100190010B1 (ko) * | 1995-12-30 | 1999-06-01 | 윤종용 | 반도체 소자의 소자분리막 형성방법 |
US5904539A (en) * | 1996-03-21 | 1999-05-18 | Advanced Micro Devices, Inc. | Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties |
JP2000508474A (ja) * | 1996-04-10 | 2000-07-04 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | 改善された平坦化方法を伴う半導体トレンチアイソレーション |
US5926713A (en) * | 1996-04-17 | 1999-07-20 | Advanced Micro Devices, Inc. | Method for achieving global planarization by forming minimum mesas in large field areas |
US5899727A (en) | 1996-05-02 | 1999-05-04 | Advanced Micro Devices, Inc. | Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization |
US5753962A (en) * | 1996-09-16 | 1998-05-19 | Micron Technology, Inc. | Texturized polycrystalline silicon to aid field oxide formation |
US5977638A (en) * | 1996-11-21 | 1999-11-02 | Cypress Semiconductor Corp. | Edge metal for interconnect layers |
US5897354A (en) * | 1996-12-17 | 1999-04-27 | Cypress Semiconductor Corporation | Method of forming a non-volatile memory device with ramped tunnel dielectric layer |
US6083809A (en) * | 1997-10-01 | 2000-07-04 | Texas Instruments Incorporated | Oxide profile modification by reactant shunting |
US5981358A (en) * | 1997-11-06 | 1999-11-09 | Advanced Micro Devices | Encroachless LOCOS isolation |
US5952707A (en) * | 1997-12-05 | 1999-09-14 | Stmicroelectronics, Inc. | Shallow trench isolation with thin nitride as gate dielectric |
US6022788A (en) * | 1997-12-23 | 2000-02-08 | Stmicroelectronics, Inc. | Method of forming an integrated circuit having spacer after shallow trench fill and integrated circuit formed thereby |
US6124171A (en) * | 1998-09-24 | 2000-09-26 | Intel Corporation | Method of forming gate oxide having dual thickness by oxidation process |
US6127215A (en) | 1998-10-29 | 2000-10-03 | International Business Machines Corp. | Deep pivot mask for enhanced buried-channel PFET performance and reliability |
DE10131917A1 (de) * | 2001-07-02 | 2003-01-23 | Infineon Technologies Ag | Verfahren zur Erzeugung einer stufenförmigen Struktur auf einem Substrat |
DE10238590B4 (de) | 2002-08-22 | 2007-02-15 | Infineon Technologies Ag | Verfahren zur Erzeugung einer Struktur auf einem Substrat |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5146083A (en) * | 1974-10-18 | 1976-04-20 | Hitachi Ltd | Handotaisochino seizohoho |
US4131910A (en) * | 1977-11-09 | 1978-12-26 | Bell Telephone Laboratories, Incorporated | High voltage semiconductor devices |
JPS55154748A (en) * | 1979-05-23 | 1980-12-02 | Toshiba Corp | Complementary mos semiconductor device |
JPS5658259A (en) * | 1979-10-18 | 1981-05-21 | Toshiba Corp | Semiconductor device and production thereof |
US4271583A (en) * | 1980-03-10 | 1981-06-09 | Bell Telephone Laboratories, Incorporated | Fabrication of semiconductor devices having planar recessed oxide isolation region |
US4334348A (en) * | 1980-07-21 | 1982-06-15 | Data General Corporation | Retro-etch process for forming gate electrodes of MOS integrated circuits |
US4390393A (en) * | 1981-11-12 | 1983-06-28 | General Electric Company | Method of forming an isolation trench in a semiconductor substrate |
EP0104765B1 (fr) * | 1982-08-24 | 1989-06-21 | Nippon Telegraph And Telephone Corporation | Structure de substrat pour dispositif semi-conducteur et procédé pour la fabrication du substrat |
JPS6045037A (ja) * | 1983-08-23 | 1985-03-11 | Nippon Telegr & Teleph Corp <Ntt> | 半導体装置の基板構造およびその製造方法 |
NL187373C (nl) * | 1982-10-08 | 1991-09-02 | Philips Nv | Werkwijze voor vervaardiging van een halfgeleiderinrichting. |
JPS59119848A (ja) * | 1982-12-27 | 1984-07-11 | Fujitsu Ltd | 半導体装置の製造方法 |
JPS60171761A (ja) * | 1984-02-17 | 1985-09-05 | Hitachi Ltd | 半導体集積回路装置及びその製造方法 |
GB2156149A (en) * | 1984-03-14 | 1985-10-02 | Philips Electronic Associated | Dielectrically-isolated integrated circuit manufacture |
JPS60241231A (ja) * | 1984-05-15 | 1985-11-30 | Nippon Telegr & Teleph Corp <Ntt> | 半導体集積回路装置の製法 |
US4561172A (en) * | 1984-06-15 | 1985-12-31 | Texas Instruments Incorporated | Integrated circuit fabrication method utilizing selective etching and oxidation to form isolation regions |
JPS6185838A (ja) * | 1984-10-04 | 1986-05-01 | Nec Corp | 半導体装置の製造方法 |
US4593459A (en) * | 1984-12-28 | 1986-06-10 | Gte Laboratories Incorporated | Monolithic integrated circuit structure and method of fabrication |
-
1985
- 1985-08-28 IT IT21994/85A patent/IT1200725B/it active
-
1986
- 1986-05-21 GB GB8612409A patent/GB2179788B/en not_active Expired
- 1986-08-11 NL NL8602047A patent/NL8602047A/nl not_active Application Discontinuation
- 1986-08-22 DE DE3628488A patent/DE3628488C2/de not_active Expired - Fee Related
- 1986-08-22 JP JP61196978A patent/JPH0821613B2/ja not_active Expired - Lifetime
- 1986-08-27 FR FR868612138A patent/FR2586860B1/fr not_active Expired - Lifetime
-
1988
- 1988-03-24 US US07/178,822 patent/US4868136A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE3628488C2 (de) | 1995-07-06 |
US4868136A (en) | 1989-09-19 |
GB2179788A (en) | 1987-03-11 |
DE3628488A1 (de) | 1987-03-05 |
GB2179788B (en) | 1989-08-09 |
IT1200725B (it) | 1989-01-27 |
FR2586860B1 (fr) | 1991-07-05 |
JPH0821613B2 (ja) | 1996-03-04 |
FR2586860A1 (fr) | 1987-03-06 |
JPS6254936A (ja) | 1987-03-10 |
IT8521994A0 (it) | 1985-08-28 |
GB8612409D0 (en) | 1986-06-25 |
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BA | A request for search or an international-type search has been filed | ||
BB | A search report has been drawn up | ||
BC | A request for examination has been filed | ||
BV | The patent application has lapsed |