DE69434736D1 - Isolationsstruktur und Verfahren zur Herstellung - Google Patents
Isolationsstruktur und Verfahren zur HerstellungInfo
- Publication number
- DE69434736D1 DE69434736D1 DE69434736T DE69434736T DE69434736D1 DE 69434736 D1 DE69434736 D1 DE 69434736D1 DE 69434736 T DE69434736 T DE 69434736T DE 69434736 T DE69434736 T DE 69434736T DE 69434736 D1 DE69434736 D1 DE 69434736D1
- Authority
- DE
- Germany
- Prior art keywords
- manufacture
- isolation structure
- isolation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000002955 isolation Methods 0.000 title 1
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76221—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO with a plurality of successive local oxidation steps
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11467193A | 1993-08-31 | 1993-08-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE69434736D1 true DE69434736D1 (de) | 2006-06-22 |
Family
ID=22356714
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69434736T Expired - Lifetime DE69434736D1 (de) | 1993-08-31 | 1994-08-26 | Isolationsstruktur und Verfahren zur Herstellung |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5696021A (de) |
| EP (1) | EP0641022B1 (de) |
| JP (1) | JPH07153829A (de) |
| DE (1) | DE69434736D1 (de) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE69434736D1 (de) * | 1993-08-31 | 2006-06-22 | St Microelectronics Inc | Isolationsstruktur und Verfahren zur Herstellung |
| KR0168196B1 (ko) * | 1995-12-14 | 1999-02-01 | 김광호 | 반도체장치의 소자분리 영역 형성방법 |
| US5899727A (en) * | 1996-05-02 | 1999-05-04 | Advanced Micro Devices, Inc. | Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization |
| KR100418300B1 (ko) * | 1996-12-04 | 2004-04-17 | 주식회사 하이닉스반도체 | 반도체소자의소자분리막형성방법 |
| US6090685A (en) * | 1997-08-22 | 2000-07-18 | Micron Technology Inc. | Method of forming a LOCOS trench isolation structure |
| TW351849B (en) * | 1997-09-11 | 1999-02-01 | United Microelectronics Corp | Method for fabricating shadow trench insulation structure |
| TW432715B (en) * | 1998-10-19 | 2001-05-01 | United Microelectronics Corp | Fabrication method of metal oxide semiconductor element |
| US6060348A (en) * | 1998-11-02 | 2000-05-09 | Vanguard International Semiconducter Corporation | Method to fabricate isolation by combining locos and shallow trench isolation for ULSI technology |
| US6140206A (en) * | 1999-06-14 | 2000-10-31 | Chartered Semiconductor Manufacturing Ltd. | Method to form shallow trench isolation structures |
| US7019348B2 (en) * | 2004-02-26 | 2006-03-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Embedded semiconductor product with dual depth isolation regions |
| FR2879020B1 (fr) * | 2004-12-08 | 2007-05-04 | Commissariat Energie Atomique | Procede d'isolation de motifs formes dans un film mince en materiau semi-conducteur oxydable |
| US20200135898A1 (en) * | 2018-10-30 | 2020-04-30 | International Business Machines Corporation | Hard mask replenishment for etching processes |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58127344A (ja) * | 1982-01-26 | 1983-07-29 | Seiko Epson Corp | 半導体装置の製造方法 |
| JPS58220444A (ja) * | 1982-06-16 | 1983-12-22 | Toshiba Corp | 半導体装置の製造方法 |
| US4508757A (en) * | 1982-12-20 | 1985-04-02 | International Business Machines Corporation | Method of manufacturing a minimum bird's beak recessed oxide isolation structure |
| JPS59119848A (ja) * | 1982-12-27 | 1984-07-11 | Fujitsu Ltd | 半導体装置の製造方法 |
| JPS6038832A (ja) * | 1983-08-12 | 1985-02-28 | Hitachi Ltd | 半導体装置とその製造方法 |
| JPS6088468A (ja) * | 1983-10-13 | 1985-05-18 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | 半導体集積装置の製造方法 |
| JPS6185838A (ja) * | 1984-10-04 | 1986-05-01 | Nec Corp | 半導体装置の製造方法 |
| IT1200725B (it) * | 1985-08-28 | 1989-01-27 | Sgs Microelettronica Spa | Struttura di isolamento in dispositivi mos e procedimento di preparazione della stessa |
| JPS6430248A (en) * | 1987-07-27 | 1989-02-01 | Hitachi Ltd | Formation of on-the-trench insulation film |
| US4835115A (en) * | 1987-12-07 | 1989-05-30 | Texas Instruments Incorporated | Method for forming oxide-capped trench isolation |
| EP0377871A3 (de) * | 1989-01-09 | 1991-03-27 | Texas Instruments Incorporated | Selbstjustierendes Fenster aus einem zurückgesetzten Kreuzungspunkt von isolierenden Bereichen |
| US5028559A (en) * | 1989-03-23 | 1991-07-02 | Motorola Inc. | Fabrication of devices having laterally isolated semiconductor regions |
| JP2765965B2 (ja) * | 1989-07-12 | 1998-06-18 | 沖電気工業株式会社 | 半導体集積回路装置の製造方法 |
| JPH03110856A (ja) * | 1989-09-26 | 1991-05-10 | Fujitsu Ltd | 半導体装置の製造方法 |
| US5106777A (en) * | 1989-09-27 | 1992-04-21 | Texas Instruments Incorporated | Trench isolation process with reduced topography |
| JP2641781B2 (ja) * | 1990-02-23 | 1997-08-20 | シャープ株式会社 | 半導体素子分離領域の形成方法 |
| JP2597022B2 (ja) * | 1990-02-23 | 1997-04-02 | シャープ株式会社 | 素子分離領域の形成方法 |
| JP2680923B2 (ja) * | 1990-10-16 | 1997-11-19 | 山口日本電気株式会社 | 半導体装置の製造方法 |
| DE69434736D1 (de) * | 1993-08-31 | 2006-06-22 | St Microelectronics Inc | Isolationsstruktur und Verfahren zur Herstellung |
-
1994
- 1994-08-26 DE DE69434736T patent/DE69434736D1/de not_active Expired - Lifetime
- 1994-08-26 EP EP94306317A patent/EP0641022B1/de not_active Expired - Lifetime
- 1994-08-30 JP JP6205735A patent/JPH07153829A/ja active Pending
-
1995
- 1995-06-07 US US08/474,537 patent/US5696021A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US5696021A (en) | 1997-12-09 |
| EP0641022A2 (de) | 1995-03-01 |
| EP0641022A3 (de) | 1997-12-29 |
| EP0641022B1 (de) | 2006-05-17 |
| JPH07153829A (ja) | 1995-06-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8332 | No legal effect for de |