JPWO2018029951A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JPWO2018029951A1 JPWO2018029951A1 JP2018513900A JP2018513900A JPWO2018029951A1 JP WO2018029951 A1 JPWO2018029951 A1 JP WO2018029951A1 JP 2018513900 A JP2018513900 A JP 2018513900A JP 2018513900 A JP2018513900 A JP 2018513900A JP WO2018029951 A1 JPWO2018029951 A1 JP WO2018029951A1
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Abstract
Description
実施の形態の説明に先立って、スーパージャンクション構造(SJ構造)について説明する。
以下、図3〜図13を用いて、本発明に係る実施の形態1の半導体装置について説明する。
図3は半導体基板に炭化珪素(シリコンカーバイド)を用いた炭化珪素半導体装置である縦型MOSFET100の構成を示す斜視図である。なお、本発明の適用は炭化珪素半導体装置に限定されず、シリコン(Si)、窒化ガリウム(GaN)、ダイヤモンド(C)などの半導体を用い、スーパージャンクション構造を有する半導体装置に適用できる。
次に、図4〜図13を用いて、縦型MOSFET100の製造工程について説明する。まず、図4に示すように、炭化珪素で構成されたn型の半導体基板3の一方の主面上に、エピタキシャル結晶成長法によりn型のエピタキシャル結晶成長層4を形成する。
図3に示した縦型MOSFET100においては、ソース電極15側から見てソース電極15の端部は、コンタクト領域10bに端部と同じ位置となるように設けられているが、ソース電極15の端部は、コンタクト領域10bの内側に位置するように設けても良く、また、リサーフ領域9の内側に設けても良く、また、リサーフ領域9の端部より外側に設けても良い。また、ソース電極15の外方のフィールド絶縁膜11上に、ソース電極15を囲むように、単数または複数のフィールドプレートを設けても良い。フィールドプレートの電位を調整することで空乏層のコーナー部の曲率を制御して、終端領域TRでの耐圧をさらに高めることができる。
以上説明した実施の形態1の縦型MOSFET100においては、終端領域TRのピラーピッチW2は、リサーフ領域9およびコンタクト領域10bの下方の領域において、全て同一とすることで半導体装置のdV/dt耐量を高めたが、これに限定されるものではない。
実施の形態1の縦型MOSFET100においては、ピラー層が終端領域TRの最外周を取り囲む構成を示したが、これに限定されるものではない。
リサーフ領域9を設けることで終端領域TRにおける耐圧をさらに高めることができるが、終端領域2の最外周にはリサーフ領域9の代わりに、ガードリング構造、JTE(Junction Termination Extension)構造、FLR(Field Limiting Ring)構造、VLD(Variation of Lateral Doping)構造などの終端構造を設けても良い。
実施の形態1の縦型MOSFET100においては、チャネルが基板に対して水平な方向に形成されるプレーナチャネル型のMOSFETを示したが、本実施の形態4においては、チャネルが基板に対して垂直な方向に形成されるトレンチチャネル型のMOSFETに本発明を適用した構成を示す。
次に、図17〜図20を用いて、縦型MOSFET400の製造工程について説明する。なお、エピタキシャル結晶成長層4の主面にn型ピラー層5aおよび5b、p型ピラー層6aおよび6bの上部が露出させるまでの工程は、図4〜図7を用いて説明した実施の形態1と同様であるので説明は省略する。
実施の形態1〜4において説明した縦型MOSFET100〜400では、ピラー層はエピタキシャル結晶成長層4に設けたトレンチを埋め込むように、p型半導体を充填して形成する、いわゆるトレンチ埋め込み方式で形成されていたが、p型不純物のイオン注入と、n型のエピタキシャル結晶成長を複数回繰り返すマルチエピタキシャル方式により、ピラー層を形成しても良い。
以上説明した実施の形態1〜5においては、本発明をエピタキシャル結晶成長層4と半導体基板3とが同じ導電型を有するMOSFETに適用した例を示したが、本発明はエピタキシャル結晶成長層4と半導体基板3とが異なる導電型を有するIGBT(Insulated Gate Bipolar Transistor)に対しても適用可能である。
Claims (8)
- 半導体基板と、
半導体基板上に配設された第1導電型の半導体層と、
前記半導体層の活性領域の上層部に選択的に配設された第2導電型の第1の不純物領域と、
前記第1の不純物領域の上層部に選択的に配設された第1導電型の第2の不純物領域と、
前記第2の不純物領域に接続された第1の主電極と、
前記第2の不純物領域、前記第1の不純物領域および前記半導体層に連続して接するように配設されたゲート絶縁膜と、
前記ゲート絶縁膜を介して前記第2の不純物領域、前記第1の不純物領域および前記半導体層に対向するように配設されたゲート電極と、
前記半導体基板の前記半導体層と反対側に配設された第2の主電極と、を備え、
前記半導体層は、
前記半導体基板とは反対側の主面から、前記半導体基板に向けて予め定めた深さまで延在するように設けられた第1導電型の第1のピラー層および第2導電型の第2のピラー層を有し、
前記第1および第2のピラー層は、
前記半導体層の前記活性領域および前記活性領域の周囲の領域である終端領域において、前記主面に対して平行な方向に交互に設けられ、
前記第1の不純物領域は、前記第2のピラー層の上層部に設けられ、
前記ゲート絶縁膜が接する前記半導体層は前記第1のピラー層であって、
前記活性領域における前記第1および第2のピラー層の1組の合計幅で規定されるピラーピッチに比べ、前記終端領域における前記第1および第2のピラー層の1組の合計幅で規定されるピラーピッチが大きく設定され、
前記活性領域および前記終端領域のいずれにおいてもピラーピッチ内における第1および第2導電型の不純物の実効的な不純物濃度が等しい、半導体装置。 - 前記活性領域における前記第1のピラー層と、前記終端領域における前記第1のピラー層の不純物濃度が等しく設定され、
前記活性領域における前記第2のピラー層と、前記終端領域における前記第2のピラー層の不純物濃度が等しく設定される、請求項1記載の半導体装置。 - 前記第1および第2のピラー層は、前記半導体層中に間隔を開けて前記第2のピラー層を形成することで設けられ、
前記第1および第2のピラー層の下方には前記半導体層がバッファ層として存在し、
前記バッファ層を含めて、ピラーピッチ内における第1および第2導電型の不純物の実効的な不純物濃度が等しい、請求項1または請求項2に記載の半導体装置。 - 前記半導体層は、
前記終端領域の前記第1および第2のピラー層の上層部に渡るように設けられた第2導電型のリサーフ領域をさらに有し、
前記リサーフ領域は、前記第1の主電極に電気的に接続され、
前記終端領域の前記第2のピラー層は、
前記リサーフ領域を介して前記第1の主電極と電気的に接続される、請求項1から請求項3の何れか1項に記載の半導体装置。 - 前記リサーフ領域は、
前記終端領域の最外周にまで延在するように設けられ、
前記終端領域の前記最外周の前記リサーフ領域の下方には、前記第1および第2のピラー層を有さない、請求項4記載の半導体装置。 - 前記終端領域における前記第1および第2のピラー層は、
前記終端領域の全域で前記第1および第2のピラー層のピラーピッチが同じ値に設定される、請求項1から請求項5の何れか1項に記載の半導体装置。 - 前記終端領域における前記第1および第2のピラー層は、
前記活性領域に近接する領域に設けられた前記第1および第2のピラー層の1組の合計幅で規定されるピラーピッチと、他の前記第1および第2のピラー層のピラーピッチとが異なった値に設定される、請求項1から請求項5の何れか1項に記載の半導体装置。 - 前記半導体基板は、半導体として炭化珪素を用いる、請求項1から請求項7の何れか1項に記載の半導体装置。
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