JP7190144B2 - 超接合炭化珪素半導体装置および超接合炭化珪素半導体装置の製造方法 - Google Patents
超接合炭化珪素半導体装置および超接合炭化珪素半導体装置の製造方法 Download PDFInfo
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Description
本発明にかかる半導体装置について、SJ-MOSFETを例に説明する。図1は、実施の形態1にかかる炭化珪素SJ-MOSFETの構造を示す断面図である。図1に示す炭化珪素SJ-MOSFET300は、炭化珪素(SiC)からなる半導体基体(炭化珪素基体:半導体チップ)のおもて面(p-型ベース領域16側の面)側にMOS(Metal Oxide Semiconductor)ゲートを備えたSJ-MOSFETである。図1では、2つの単位セル(素子の機能単位)のみを示し、これらに隣接する他の単位セルを図示省略する。
次に、実施の形態1にかかる炭化珪素半導体装置の製造方法について説明する。図6~図8は、実施の形態1にかかる炭化珪素SJ-MOSFETの製造途中の状態を示す断面図である。実施の形態1では、1.2kV耐圧クラスのトレンチ構造を有する炭化珪素SJ-MOSFETを例に製造方法を説明する。
次に、実施の形態2にかかる半導体装置の構造について説明する。図9は、実施の形態2にかかる炭化珪素SJ-MOSFETの構造を示す断面図である。図9に示すように、実施の形態2にかかる炭化珪素SJ-MOSFET301が実施の形態1にかかる炭化珪素SJ-MOSFET300と異なる点は、並列pn領域33の表面にn型高濃度領域(第1導電型の第3半導体層)5が設けられ、n型高濃度領域5の内部にp+型領域(第2導電型の第2半導体領域)3が選択的に設けられていることである。
次に、実施の形態2にかかる炭化珪素半導体装置の製造方法について説明する。まず、実施の形態1と同様にn型の炭化珪素でできたn+型炭化珪素基板1を用意して、第8n型カラム領域31-8および第9p型カラム領域30-9まで形成する工程まで行う(図8参照)。
次に、実施の形態3にかかる半導体装置の構造について説明する。図14は、実施の形態3にかかる炭化珪素SJ-MOSFETの構造を示す断面図である。図14に示すように、実施の形態3にかかる炭化珪素SJ-MOSFET302が実施の形態2にかかる炭化珪素SJ-MOSFET301と異なる点は、p型カラム領域30がトレンチ23の直下(トレンチ23の底のp+型領域3とn-型ドリフト層2との間の領域)に設けられていることである。
次に、実施の形態4にかかる半導体装置の構造について説明する。図15は、実施の形態4にかかる炭化珪素SJ-MOSFETの構造を示す断面図である。図15に示すように、実施の形態4にかかる炭化珪素SJ-MOSFET303が実施の形態3にかかる炭化珪素SJ-MOSFET302と異なる点は、p型カラム領域30がトレンチ23の直下だけ第1p型カラム領域30-1を設けず、トレンチ23とトレンチ23との間のp型カラム領域30だけに第1p型カラム領域30-1を設けていることである。
2、102 n-型ドリフト層
3 p+型領域
5 n型高濃度領域
16、116 p-型ベース領域
17、117 n+型ソース領域
18、118 p++型コンタクト領域
19、119 ゲート絶縁膜
20、120 ゲート電極
21、121 層間絶縁膜
22、122 ソース電極
23、123 トレンチ
30、130 p型カラム領域
30-1~30-9 第1p型カラム領域~第9p型カラム領域
31、131 n型カラム領域
31-1~31-8 第1n型カラム領域~第8p型カラム領域
32 n型エピタキシャル層
33、133 並列pn領域
200 SJ-MOSFET
300、301、302、303 炭化珪素SJ-MOSFET
Claims (10)
- 第1導電型の炭化珪素半導体基板と、
前記炭化珪素半導体基板のおもて面に設けられた第1導電型の第1半導体層と、
前記第1半導体層の、前記炭化珪素半導体基板側に対して反対側の表面に設けられた、第1導電型の第1カラム領域と第2導電型の第2カラム領域とが前記おもて面に平行な面において繰り返し交互に配置された並列pn領域と、
前記並列pn領域の、前記炭化珪素半導体基板側に対して反対側の表面に設けられた第2導電型の第2半導体層と、
前記第2半導体層の内部に選択的に設けられた前記第1半導体層よりも不純物濃度の高い第1導電型の第1半導体領域と、
前記並列pn領域と前記第2半導体層との間に設けられた、前記第1カラム領域より不純物濃度が高い第1導電型の第3半導体層と、
前記第1半導体領域および前記第2半導体層を貫通して前記第3半導体層に達するトレンチと、
前記トレンチの内部にゲート絶縁膜を介して設けられたゲート電極と、
前記第1半導体領域および前記第2半導体層に接する第1電極と、
を備え、
前記第1カラム領域の不純物濃度が1.1×1016/cm3以上5.0×1016/cm3以下であり、
前記第1カラム領域よりも前記第2カラム領域の結晶欠陥が多いことを特徴とする超接合炭化珪素半導体装置。 - 第1導電型の炭化珪素半導体基板と、
前記炭化珪素半導体基板のおもて面に設けられた第1導電型の第1半導体層と、
前記第1半導体層の、前記炭化珪素半導体基板側に対して反対側の表面に設けられた、第1導電型の第1カラム領域と第2導電型の第2カラム領域とが前記おもて面に平行な面において繰り返し交互に配置された並列pn領域と、
前記並列pn領域の、前記炭化珪素半導体基板側に対して反対側の表面に設けられた第2導電型の第2半導体層と、
前記第2半導体層の内部に選択的に設けられた前記第1半導体層よりも不純物濃度の高い第1導電型の第1半導体領域と、
前記並列pn領域と前記第2半導体層との間に設けられた、前記第1カラム領域より不純物濃度が高い第1導電型の第3半導体層と、
前記第1半導体領域および前記第2半導体層を貫通して前記第3半導体層に達するトレンチと、
前記トレンチの内部にゲート絶縁膜を介して設けられたゲート電極と、
前記第1半導体領域および前記第2半導体層に接する第1電極と、
を備え、
前記第1カラム領域の不純物濃度が1.1×1016/cm3以上5.0×1016/cm3以下であり、
前記第2カラム領域はその導電型を決定する不純物濃度が深さ方向に周期的分布を有することを特徴とする超接合炭化珪素半導体装置。 - 前記第3半導体層内に設けられた、前記トレンチの底部と接する第2導電型の第2半導体領域と、
前記第3半導体層内の前記トレンチの間に設けられた、第2導電型の第3半導体領域と、
をさらに備えることを特徴とする請求項1または2に記載の超接合炭化珪素半導体装置。 - 前記第1半導体層は、前記第1カラム領域より不純物濃度が低く、かつ、不純物濃度が1.1×1016/cm3以上5.0×1016/cm3以下であることを特徴とする請求項1~3のいずれか一つに記載の超接合炭化珪素半導体装置。
- 前記第2カラム領域の少数キャリアライフタイムは0.5ns~500nsであることを特徴とする請求項1~4のいずれか一つに記載の超接合炭化珪素半導体装置。
- 前記第2カラム領域は、深さ0.4μm~3.0μmの周期であることを特徴とする請求項1~5のいずれか一つに記載の超接合炭化珪素半導体装置。
- 前記第2カラム領域は、前記トレンチと前記トレンチの間の領域のみに設けられていることを特徴とする請求項1~6のいずれか一つに記載の超接合炭化珪素半導体装置。
- 前記第2カラム領域は、前記トレンチと前記トレンチの間の領域、ならびに前記トレンチ直下の領域に設けられていることを特徴とする請求項1~6のいずれか一つに記載の超接合炭化珪素半導体装置。
- 前記トレンチの直下の領域の第2カラム領域は、前記トレンチと前記トレンチの間の領域の第2カラム領域よりも浅いことを特徴とする請求項8に記載の超接合炭化珪素半導体装置。
- 第1導電型の炭化珪素半導体基板のおもて面に第1導電型の第1半導体層を形成する第1工程と、
前記第1半導体層の、前記炭化珪素半導体基板側に対して反対側の表面に、第1導電型の第1カラム領域と第2導電型の第2カラム領域とが前記おもて面に平行な面において繰り返し交互に配置された並列pn領域を形成する第2工程と、
前記並列pn領域の、前記炭化珪素半導体基板側に対して反対側の表面に第2導電型の第2半導体層を形成する第3工程と、
前記第2半導体層の内部に選択的に前記第1半導体層よりも不純物濃度の高い第1導電型の第1半導体領域を形成する第4工程と、
前記第2工程と前記第3工程との間において、前記並列pn領域の上で、前記並列pn領域と前記第2半導体層との間に、前記第1カラム領域より不純物濃度が高い第1導電型の第3半導体層を形成する工程と、
前記第1半導体領域および前記第2半導体層を貫通して前記第3半導体層に達するトレンチを形成する第5工程と、
前記トレンチの内部にゲート絶縁膜を介してゲート電極を形成する第6工程と、
前記第1半導体領域および前記第2半導体層に接する第1電極を形成する第7工程と、
を含み、
前記第2工程では、エピタキシャル成長で前記第1カラム領域の不純物濃度を1.1×1016/cm3以上5.0×1016/cm3以下とし、
前記第2カラム領域をイオン注入で形成し、前記エピタキシャル成長と前記イオン注入を繰り返すことで、前記第1カラム領域よりも前記第2カラム領域の結晶欠陥を多くすることを特徴とする超接合炭化珪素半導体装置の製造方法。
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