JP2018110164A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2018110164A JP2018110164A JP2016256895A JP2016256895A JP2018110164A JP 2018110164 A JP2018110164 A JP 2018110164A JP 2016256895 A JP2016256895 A JP 2016256895A JP 2016256895 A JP2016256895 A JP 2016256895A JP 2018110164 A JP2018110164 A JP 2018110164A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 217
- 239000010410 layer Substances 0.000 claims description 134
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 105
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 105
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- 238000005468 ion implantation Methods 0.000 description 7
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- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- UMVBXBACMIOFDO-UHFFFAOYSA-N [N].[Si] Chemical compound [N].[Si] UMVBXBACMIOFDO-UHFFFAOYSA-N 0.000 description 1
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Abstract
Description
本発明にかかる半導体装置は、シリコン(Si)よりもバンドギャップが広い半導体(ワイドバンドギャップ半導体)を用いて構成される。ここでは、ワイドバンドギャップ半導体として例えば炭化珪素(SiC)を用いたMOSFETを例に説明する。図1は、実施の形態1にかかる半導体装置の活性領域の構造を示す断面図である。図1には、2つの単位セル(素子の機能単位)のみを示し、これらに隣接する他の単位セルを図示省略する。図2は、実施の形態1にかかる半導体装置のエッジ終端領域の構造を示す断面図である。
次に、実施の形態2にかかる半導体装置の構造について説明する。図9は、実施の形態2にかかる半導体装置のエッジ終端領域の構造を示す断面図である。実施の形態2にかかる半導体装置の活性領域10の構成は、実施の形態1と同様である(図1参照)。実施の形態2にかかる半導体装置が実施の形態1にかかる半導体装置と異なる点は、次の2点である。1つ目の相違点は、完成後のn型CS領域5と同じ不純物濃度でエピタキシャル成長させたn型炭化珪素層でn型CS領域5が構成されている。
エッジ終端領域20の耐圧について検証した。図13は、実施例にかかる半導体装置の耐圧特性を示す特性図である。図13の横軸は第1JTE領域の不純物濃度(JTE1濃度)であり、縦軸はエッジ終端領域の耐圧である。上述した実施の形態1を適用したMOSFETにおいて(以下、実施例とする)、第1JTE領域21の不純物濃度を種々変更して得られたエッジ終端領域20の耐圧特性を図13に示す。実施例においては、n型CS領域5が活性領域10のみに設けられ、最外p++型コンタクト領域8’がエッジ終端領域20に延在している。
2 n-型ドリフト領域
3,3’ 第1p+型領域
3a,3a',3b,3b' p+型部分領域
4 第2p+型領域
5 n型CS領域
5a,5b n型部分領域
6 p型ベース領域
7 n+型ソース領域
8,8' p++型コンタクト領域
9 トレンチ
10 活性領域
11 ゲート絶縁膜
12 ゲート電極
13 層間絶縁膜
14 ソース電極
15 ソースパッド
16 ドレイン電極
17 ドレインパッド
20 エッジ終端領域
21,22 JTE領域
23 活性領域とエッジ終端領域との段差
23a 活性領域とエッジ終端領域との段差のステア
24 n-型領域
30 炭化珪素基体
31,31a〜31e,32 エピタキシャル成長による炭化珪素層
Claims (9)
- 電流が流れる活性領域よりも外側に耐圧構造を備えた半導体装置において、
シリコンよりもバンドギャップが広い半導体からなる半導体基板と、
前記半導体基板のおもて面に設けられた、シリコンよりもバンドギャップが広い半導体からなる第1導電型の第1半導体層と、
前記活性領域において、前記第1半導体層の、前記半導体基板側に対して反対側の表面に設けられた、シリコンよりもバンドギャップが広い半導体からなる第2導電型の第2半導体層と、
前記第1半導体層の、前記半導体基板側に対して反対側の表面層に、前記第2半導体層に接して選択的に設けられた、前記第2半導体層よりも不純物濃度の高い第2導電型の第1半導体領域と、
前記第1半導体層の内部に、前記第2半導体層および前記第1半導体領域と離して選択的に設けられた、前記第2半導体層よりも不純物濃度の高い第2導電型の第2半導体領域と、
前記第1半導体層の、前記半導体基板側に対して反対側の表面層に、前記第1半導体領域および前記第2半導体領域に接して選択的に設けられた、前記第1半導体層よりも不純物濃度の高い第1導電型の第3半導体領域と、
前記第2半導体層の内部に選択的に設けられた第1導電型の第4半導体領域と、
前記第2半導体層の内部に選択的に設けられた、前記第2半導体層よりも不純物濃度の高い第2導電型の第5半導体領域と、
前記第4半導体領域および前記第2半導体層を貫通して前記第3半導体領域に達し、深さ方向に前記第2半導体領域に対向するトレンチと、
前記トレンチの内部にゲート絶縁膜を介して設けられたゲート電極と、
前記第2半導体層および前記第4半導体領域に接する第1電極と、
前記半導体基板の裏面に設けられた第2電極と、
を備え、
前記第3半導体領域は、前記活性領域に設けられ、
前記第5半導体領域は、前記第3半導体領域と面一又は当該第3半導体領域よりも内側に延在することを特徴とする半導体装置。 - 前記第3半導体領域は、前記第1半導体領域よりも外側で終端していることを特徴とする請求項1に記載の半導体装置。
- 前記第3半導体領域は、前記活性領域のみに設けられていることを特徴とする請求項1または2に記載の半導体装置。
- 前記第3半導体領域は、前記耐圧構造に接することを特徴とする請求項1〜3のいずれか一つに記載の半導体装置。
- 前記活性領域よりも外側において、前記第1半導体層の、前記半導体基板側に対して反対側の表面層に、前記第3半導体領域に接して設けられた、前記第3半導体領域よりも不純物濃度の低い第1導電型の第6半導体領域をさらに備え、
前記第6半導体領域の内部に前記耐圧構造が設けられていることを特徴とする請求項1〜4のいずれか一つに記載の半導体装置。 - 前記第6半導体領域の不純物濃度は、前記第1半導体層の不純物濃度以下であることを特徴とする請求項5に記載の半導体装置。
- 前記第3半導体領域は、前記第1半導体層と前記第2半導体層との間に設けられたエピタキシャル成長層であり、
前記第6半導体領域は、前記エピタキシャル成長層の、前記活性領域よりも外側の部分に設けられ、深さ方向に前記エピタキシャル成長層を貫通することを特徴とする請求項5または6に記載の半導体装置。 - 前記耐圧構造は、前記第1半導体層の、前記半導体基板側に対して反対側の表面層に、前記活性領域の周囲を囲む同心円状に設けられた、前記活性領域から離れるほど不純物濃度が低く、かつ前記第2半導体層よりも不純物濃度の低い第2導電型の複数の第7半導体領域で構成されることを特徴とする請求項1〜7のいずれか一つに記載の半導体装置。
- シリコンよりもバンドギャップが広い半導体は、炭化珪素であることを特徴とする請求項1〜8のいずれか一つに記載の半導体装置。
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