CN103681780B - 一种高压超结终端结构 - Google Patents
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- 238000005452 bending Methods 0.000 description 1
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- 238000002156 mixing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000009897 systematic effect Effects 0.000 description 1
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Abstract
本发明提供了一种高压超结终端结构,包括由间隔分布的P+,N‑,N+柱构成的超结区和拥有金属场板和SIPOS场板的终端表面结构,所述超结区和终端表面结构之间有一层P‑层,所述终端表面结构由下到上依次淀积有高阻SIPOS层、SiO2层、低阻SIPOS层、金属场板和掺氮SIPOS层,所述终端表面结构也可以由下到上依次淀积高阻SIPOS层、SiO2层、金属场板和掺氮SIPOS层,并在末端采用沟槽截止。本发明提供的一种高压超结终端结构能够耐高压,提高终端可靠性,减小漏电流,可以应用于大功率器件(IGBT,VDMOS等)的终端制造。
Description
技术领域
本发明涉及压控型功率器件制作领域,特别涉及一种高压超结终端结构。
背景技术
器件阻断高压的能力主要取决于器件结构中特定PN结的反偏击穿电压。在功率器件中,受PN结弯曲或PN结终止处表面非理想因素的影响,PN结反偏击穿电压又受限于发生在表面附近或结弯曲处局部区域相对于体内平行平面结提前出现的击穿现象。结终端就是为了减小局部电场、提高表面击穿电压及可靠性、使器件实际击穿电压更接***行平面结理想值而专门设计的特殊结构。在纵向导电器件中它通常分布在器件有源区的周边。
结终端作为功率半导体器件的重要组成部分,对***性能的实现和改善起到至关重要的作用。对结终端结构的要求包括面积效率高和可靠性好等多个方面。其中功率器件的面积效率对结终端结构非常依赖,当结终端所占的面积减小时,在同样的芯片面积上,有源区的面积增大,这样就能够提高电流的处理能力
超结结构由于其独特的耐压原理使得它在器件的特性参数折中方面有着优异的表现,超结的结构特点是N,P柱间隔交错排布的格局。通过这种结构来引入横向电场,利用横向电场对纵向电场的影响来实现耐高压的目的。普通超结横向电场分布为三角形,纵向电场分布为梯形。理论上精确电荷平衡的超结结构性能较好,否则参数会有所退化,但实际工艺很难做到绝对的平衡。
在专利US20100032791-A1中,提出了一种超结终端结构。如图1所示,在该专利中,终端表面结构的高掺杂柱的宽度和高度是渐变的,使得电压在终端表面结构分布较为均匀,终端的最***采用深槽截止,保证耐压的同时提高终端可靠性。但这种超结终端结构具有以下缺点:
1)现有工艺较难保证超结P,N柱的电荷达到精确平衡,这就会导致器件的参数退化,例如BV就随着电荷不平衡程度的加强下降的很厉害。
2)终端表面结构半导体表面的电场均匀性不佳,容易在结附近或场板的末端出现击穿现象。
3)工艺中无法防止界面的离子污染和电荷积累,大大影响了功率器件的可靠性。
4)现有终端技术由于耐压结构的原因,耐高压需要的终端表面结构域的宽度较大。增大了芯片面积,增加了芯片的生产成本。
发明内容
本发明所要解决的技术问题是提供一种能够耐高压、可靠性高、漏电流小的高压超结终端结构。
为解决上述技术问题,本发明提供了一种高压超结终端结构,包括由间隔分布的P+,N-,N+柱构成的超结区和拥有金属场板和SIPOS场板的终端表面结构,所述超结区和终端表面结构之间有一层P-层,所述终端表面结构由下到上依次淀积有高阻SIPOS层、SiO2层、低阻SIPOS层、金属场板和掺氮SIPOS层。
进一步地,所述高阻SIPOS层中的含氧量为20%-35%。
进一步地,所述低阻SIPOS层中的含氧量为5%-20%。
进一步地,所述终端表面结构可以是SIPOS钝化、沟槽截止的终端表面结构,所述终端表面结构由下到上依次淀积有高阻SIPOS层、SiO2层、金属场板和掺氮SIPOS层。
进一步地,所述高阻SIPOS层中的含氧量为20%-35%。
进一步地,所述高阻SIPOS层、低阻SIPOS层和掺氮SIPOS层都是在650℃条件下,用LPCVD方法淀积成的。
本发明提供的一种高压超结终端结构具有以下优点:
1.采用间隔分布的P+,N-,N+柱构成改进型的超结结构,提高终端区耐压。
2.终端末端采用深槽截止,槽中填充高阻SIPOS\SiO2\掺氮SIPOS,且与上表面的该结构相连,防止表面和拐角击穿,提高终端可靠性,减小漏电流;
3.终端区表面和截止槽表面Si和SiO2之间增加高阻SIPOS层,可有效减少离子污染和电荷积累,提高终端可靠性。
4.采用金属场板降低PN结处的电场峰值,采用低阻SIPOS电阻型场板使终端表面电场平坦化,避免了金属场板边缘的电场集中效应。
5.终端区上表面通过离子注入浅P层,可有效防止超结结构由于杂质分凝引起的电荷不平衡。
6.掺氮SIPOS作为最外层的钝化,可以有效阻挡水汽和Na+离子这样的可动离子。
附图说明
图1是专利US20100032791-A1提供的一种超结终端结构示意图。
图2为本发明实施例提供的拥有金属场板和SIPOS场板的超结终端结构图。
图3为本发明实施例提供的SIPOS钝化、沟槽截止型超结终端结构图。
具体实施方式
参见图2,本发明提供了一种高压超结终端结构,包括由间隔分布的P+,N-,N+柱构成的超结区1和拥有金属场板和SIPOS场板的终端表面结构2,超结区1和终端表面结构2之间有一层P-层3,终端表面结构2硅片表面由下到上依次淀积有高阻SIPOS层201、SiO2层202、低阻SIPOS层203、金属场板204和掺氮SIPOS层205。
参见图3,本发明实施例提供的一种高压超结终端结构,包括由间隔分布的P+,N-,N+柱构成的超结区1和拥有金属场板和SIPOS场板的终端表面结构2,超结区1和终端表面结构2之间有一层P-层3,终端表面结构2硅片表面由下到上依次淀积有高阻SIPOS层201、SiO2层202、金属场板204和掺氮SIPOS层205。
本发明实施例提供的拥有金属场板和SIPOS场板的超结终端结构的超结区1由间隔分布的P+,N-,N+柱构成,掺杂柱的宽度和掺杂浓度需保证P,N型材料总体的电荷平衡(P+柱中电荷等于N-柱与N+柱中电荷之和),和终端表面结构2表面的浅注入一层P-来提高超结区的电荷平衡度,这样的结构在横向上引入了一个梯形电场,可以有效提高终端区的耐压。和终端表面结构2由下到上依次淀积高阻SIPOS层201(含氧量20%-35%),SiO2层202,低阻SIPOS层203(含氧量5%-20%),金属场板204,掺氮SIPOS层205作为最外层的钝化。低阻SIPOS层203作为SIPOS场板,金属场板204位于SIPOS场板之上。两种场板综合使用可以使终端表面电场均匀。高阻SIPOS层201和低阻SIPOS层203之间的SiO2层202可以减小漏电流,掺氮SIPOS层205作为最外层的钝化可以有效阻挡水汽和Na+离子这样的可动离子
本发明实施例提供的SIPOS钝化、沟槽截止的超结终端结构的超结区1由间隔分布的P+,N-,N+柱构成,掺杂柱的宽度和掺杂浓度需保证P,N型材料总体的电荷平衡,终端表面结构2的表面浅注入一层P-来提高超结区的电荷平衡度,终端表面结构2由下到上依次淀积高阻SIPOS层201(含氧量20%-35%),SiO2层202,金属场板204,掺氮SIPOS层205作为最外层的钝化。远端的截止槽内填充物与硅片表面的淀积物同时形成,连在一起,结构与表面相同,保证表面电场和拐角处趋于均匀,防止表面或拐角击穿。
上述结构中涉及到的高阻SIPOS层、低阻SIPOS层和掺氮SIPOS层都是在650℃下,用LPCVD的方法淀积成的。
本发明提供的一种高压超结终端结构,间隔排布的N,P柱形成超结结构。其耐压原理就是通过横向PN结来引入横向电场,利用横向电场对纵向电场的影响来实现耐高压的目的。普通超结横向电场分布为三角形,纵向电场分布为梯形。本发明中提到的横向变掺杂超结则是通过引入横向的P+N-N+结来实现横向的梯形电场分布,而纵向电场分布依然为梯形,从而在相同面积的情况下提高终端区的耐压。
终端区上表面通过离子注入浅P层,可以补偿部分在退火中由于杂质分凝引起的P柱变窄,可有效降低电荷不平衡的程度,防止参数退化。
终端末端采用沟槽截止,填充SIPOS,SiO2组合层且与上表面的钝化结构相连,这种结构可以使表面和拐角处电场趋于均匀,防止表面击穿。
另外SIPOS薄膜是半绝缘的,几乎是电中性的,当硅器件表面直接以掺氧的高阻SIP0S接触时,界面上的离子沾污在硅表面附近所感应的相反极性的电荷将漂移到SIPOS层里面,而感应的电荷将中和外表面的电荷。另一方面,由于热载流子不会长时间留在SIPOS层内,所以由于PN结雪崩击穿而注入到钝化层的热载流子不会发生储存效应。另外,SIPOS薄膜的半绝缘性还使得其可以释放表面电场。而在高阻SIPOS层上加一层SiO2则可以减小漏电流,因此,各层综合应用,有利于提高器件的耐压和可靠性。掺氮SIPOS作为最外层的钝化,可以有效阻挡水汽和Na+离子这样的可动离子。
金属场板提高了结的曲率半径,降低了结附近的电场峰值;SIPOS电阻场板使硅表面电场平坦化,避免了金属场板边缘的电场集中效应。这都有助于提高终端耐压。
最后所应说明的是,以上具体实施方式仅用以说明本发明的技术方案而非限制,尽管参照实例对本发明进行了详细说明,本领域的普通技术人员应当理解,可以对本发明的技术方案进行修改或者等同替换,而不脱离本发明技术方案的精神和范围,其均应涵盖在本发明的权利要求范围当中。
Claims (4)
1.一种超结终端结构,包括由间隔分布的P+,N-,N+柱构成的超结区和拥有金属场板和SIPOS场板的终端表面结构,所述超结区和终端表面结构之间有一层P-层,其特征在于:所述终端表面结构由下到上依次淀积有高阻SIPOS层、SiO2层、低阻SIPOS层、金属场板和掺氮SIPOS层,所述高阻SIPOS层中的含氧量为20%-35%,所述低阻SIPOS层中的含氧量为5%-20%。
2.根据权利要求1所述的超结终端结构,其特征在于:所述终端表面结构是SIPOS钝化、沟槽截止的终端表面结构,所述终端表面结构由下到上依次淀积有高阻SIPOS层、SiO2层、金属场板和掺氮SIPOS层。
3.根据权利要求2所述的超结终端结构,其特征在于:所述高阻SIPOS层的含氧量为20%-35%。
4.根据权利要求1-3任一项所述的超结终端结构,其特征在于:所述高阻SIPOS层、低阻SIPOS层和掺氮SIPOS层都是在650℃条件下,用LPCVD方法淀积成的。
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