WO2014112239A1 - 半導体素子 - Google Patents
半導体素子 Download PDFInfo
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- WO2014112239A1 WO2014112239A1 PCT/JP2013/082747 JP2013082747W WO2014112239A1 WO 2014112239 A1 WO2014112239 A1 WO 2014112239A1 JP 2013082747 W JP2013082747 W JP 2013082747W WO 2014112239 A1 WO2014112239 A1 WO 2014112239A1
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Definitions
- the present invention relates to a semiconductor element.
- semiconductor elements are classified into a horizontal semiconductor element having electrodes on one side and a vertical semiconductor element having electrodes on both sides.
- the direction in which the drift current flows in the on state is the same as the direction in which the depletion layer due to the reverse bias voltage extends in the off state.
- MOSFET Metal Oxide Field Effect Transistor: MOS type field effect transistor
- the portion of the high resistance n ⁇ drift layer is in the vertical direction when in the on state. It acts as a region where drift current flows. Therefore, if the current path of the n ⁇ drift layer is shortened, the drift resistance is lowered, so that the substantial on-resistance of the MOSFET can be lowered.
- the portion of the high resistance n ⁇ drift layer is depleted in the off state to increase the breakdown voltage. Therefore, when the n ⁇ drift layer is thinned, the width of the drain-base depletion layer extending from the pn junction between the p base region and the n ⁇ drift layer becomes narrower, and the critical electric field strength of silicon is reached quickly. The withstand voltage will decrease. On the other hand, in a semiconductor device with a high breakdown voltage, since the n ⁇ drift layer is thick, the on-resistance increases and the loss increases. Thus, there is a trade-off relationship between on-resistance and breakdown voltage.
- a superjunction semiconductor element having a parallel pn structure in which a drift layer is formed by alternately and repeatedly joining n-type drift regions and p-type partition regions having a high impurity concentration is known.
- a high breakdown voltage can be achieved.
- FIG. 5 is a cross-sectional view showing the structure of a conventional vertical MOSFET.
- FIG. 5 is FIG. 12 of Patent Document 5 below.
- a drain / drift portion 102 having a first parallel pn structure is provided on a low-resistance n + drain layer 101 with which a drain electrode 113 on the back side is in conductive contact.
- a high impurity concentration p base region 103 to be the element active portion 121 is selectively provided.
- the drain / drift portion 102 substantially corresponds to a portion immediately below the p-type base region 103 of the plurality of wells to be the element active portion 121, and is a layered vertical first n-type region 102a oriented in the thickness direction of the substrate and the thickness of the substrate.
- This is a first parallel pn structure in which layered vertical first p-type regions 102b oriented in the direction are alternately and repeatedly joined in the creeping direction of the substrate at a pitch P101.
- a MOS gate metal-oxidation
- a MOS gate metal-oxidation
- a p base region 103 a p + contact region 105, an n + source region 106, a gate insulating film 107 and a gate electrode layer 108 is formed.
- a film-semiconductor insulating gate) structure and a source electrode 110 are provided.
- Reference numeral 109 denotes an interlayer insulating film.
- the periphery of the drain / drift portion 102 is an element peripheral edge portion 122 having a second parallel pn structure.
- the element peripheral edge portion 122 is continuous with the first parallel pn structure of the drain / drift portion 102 and is repeatedly formed in a layered vertical second n-type region 112a oriented in the thickness direction of the substrate at a pitch P101 and in the thickness direction of the substrate.
- the layered vertical second p-type regions 112b to be aligned are joined alternately and repeatedly in the creeping direction of the substrate.
- the first parallel pn structure and the second parallel pn structure have substantially the same repetition pitch P101 and substantially the same impurity concentration.
- An oxide film 115 is provided on the surface of the second parallel pn structure.
- a field plate electrode FP extended from the source electrode 110 is formed on the oxide film 115 and covers the second parallel pn structure.
- An n-type channel stopper region 114 connected to the n + drain layer 101 is formed outside the device peripheral portion 122, and a stopper electrode 116 is in conductive contact with the n-type channel stopper region 114.
- the second parallel pn structure and the n-type channel stopper region 114 are regions having a shorter carrier lifetime than the first parallel pn structure (portion indicated by hatching).
- the element peripheral edge 122 is made shorter by making the carrier lifetime of the second parallel pn structure of the element peripheral part 122 shorter than the carrier lifetime of the first parallel pn structure of the element active part 121.
- the amount of carriers accumulated in the portion 122 is reduced, and the breakdown tolerance against local concentration of the reverse recovery current in the reverse recovery process of the built-in diode composed of the first p-type region 102b and the first n-type region 102a is improved.
- the carrier lifetime of the second parallel pn structure of the element peripheral portion 122 there is a problem that the leakage current in the off state increases, and as a result, the loss increases.
- the leakage current in the off state becomes too large, there is a problem that the element is destroyed due to thermal runaway.
- the present invention provides a semiconductor device capable of improving the breakdown resistance in a super junction semiconductor device capable of greatly improving the trade-off relationship between on-resistance and breakdown voltage.
- the purpose is to provide.
- a semiconductor device has the following characteristics.
- An element active portion that is present on the first main surface side of the substrate and allows an active or passive current to flow, a first conductivity type low resistance layer that is present on a surface layer on the second main surface side of the substrate, and the element active portion And the first conductivity type low resistance layer, and a vertical drift portion in which the drift current flows in the vertical direction in the on state and is depleted in the off state.
- first vertical first conductivity type regions oriented in the thickness direction of the substrate and first vertical second conductivity type regions oriented in the thickness direction of the substrate are alternately and repeatedly joined. Thus, a first parallel pn structure is formed.
- the first conductivity type layer having a higher resistance than the first conductivity type low resistance layer from the element active portion to the device peripheral portion. Is provided.
- a second conductivity type low resistance layer is selectively provided on the surface layer on the second main surface side in the peripheral portion of the element. An output electrode in contact with the first conductivity type low resistance layer and the second conductivity type low resistance layer is provided.
- the semiconductor element according to the present invention is characterized in that, in the above-described invention, the impurity concentration of the second conductivity type low resistance layer is higher than the impurity concentration of the first conductivity type layer.
- the semiconductor element according to the present invention is characterized in that, in the above-described invention, the impurity concentration of the second conductivity type low resistance layer is higher than the impurity concentration of the first conductivity type low resistance layer.
- the semiconductor element according to the present invention further includes a plurality of second conductivity type base regions provided on the first main surface side in the above-described invention.
- An inner end of the second conductivity type low resistance layer is located at a boundary between the element active part and the element peripheral part.
- the outer end portion of the second conductivity type low resistance layer extends from the outer end portion of the second conductivity type base region provided on the outermost side among the plurality of second conductivity type base regions. It is characterized in that it is located outside by more than the thickness of the part.
- the second conductivity type low resistance layer is provided from a boundary between the element active part and the element peripheral part to an outer periphery of the element peripheral part. It is characterized by.
- the second conductivity type low resistance layer is provided on a surface layer on the second main surface side of the first conductivity type low resistance layer.
- the first conductivity type low resistance layer is interposed between the second conductivity type low resistance layer and the first conductivity type layer.
- the peripheral edge portion of the element is a second vertical first conductivity type region oriented in the thickness direction of the substrate and a second orientation oriented in the thickness direction of the substrate.
- a second parallel pn structure in which the vertical second conductivity type regions are alternately and repeatedly joined is characterized.
- the element periphery Since the volume of the n + drain layer in the portion is reduced, the injection of electrons from the n + drain layer on the back side of the substrate to the second parallel pn structure is suppressed, and accordingly, the outermost periphery on the front surface side of the substrate Hole injection from the p base region into the second parallel pn structure is suppressed. Thereby, the amount of accumulated carriers in the peripheral portion of the element can be reduced, and current concentration in the outermost peripheral p base region in the reverse recovery process of the built-in diode can be reduced.
- the semiconductor device according to the present invention has an effect that the breakdown tolerance can be improved.
- FIG. 1 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.
- FIG. 2 is a cross-sectional view illustrating the structure of the semiconductor device according to the second embodiment.
- FIG. 3 is a cross-sectional view illustrating the structure of the semiconductor device according to the third embodiment.
- FIG. 4 is a cross-sectional view showing the structure of the semiconductor device according to the fourth embodiment.
- FIG. 5 is a cross-sectional view showing the structure of a conventional vertical MOSFET.
- FIG. 1 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.
- the semiconductor element according to the first embodiment shown in FIG. 1 is a superjunction MOSFET provided with a drain / drift part (vertical drift part) 2 having a first parallel pn structure.
- a drain / drift part vertical drift part
- a p-type base region 3a having a high impurity concentration to be the element active portion 21 is selectively provided.
- the substrate is an epitaxial substrate described later.
- a high impurity concentration p + contact region 5 and n + source region 6 are selectively provided on the front side of the substrate inside the p base region 3a.
- the n + source region 6 is formed shallower than the p + contact region 5 in the well-shaped p base region 3a and constitutes a double diffused MOS section.
- a gate electrode layer 8 such as polysilicon is provided via a gate insulating film 7.
- Source electrode 10 is in conductive contact across p base region 3 a and n + source region 6 through a contact hole formed in interlayer insulating film 9.
- the drain / drift portion 2 substantially corresponds to a portion directly below the p base region 3a of a plurality of wells to be the element active portion 21, and is a layered vertical first n-type region (first vertical orientation oriented in the thickness direction of the substrate).
- any of the first n-type regions 2a has an upper end (end on the front side of the substrate) reaching the surface n-type drift region 4 which is a gap region of the p base region 3a, and a lower end (on the back side of the substrate) Of the n buffer layer 11 is in contact with the n buffer layer 11.
- the first n-type region 2a reaching the surface n-type drift region 4 is an electric circuit region in the on state, but the remaining first n-type region 2a is generally a non-electric circuit region.
- the first p-type region 2 b has an upper end in contact with the well bottom surface of the p base region 3 a and a lower end in contact with the n buffer layer 11.
- the periphery of the drain / drift portion 2 is an element peripheral portion 22 having a second parallel pn structure.
- the element peripheral portion 22 is a layered vertical second n-type region (second vertical type second region) oriented in the thickness direction of the substrate at a repeated pitch P2 continuously to the first parallel pn structure of the drain / drift portion 2.
- (1 conductivity type region) 12a and layered vertical second p type region (second vertical type 2 conductivity type region) 12b oriented in the thickness direction of the substrate are alternately and repeatedly joined in the creeping direction of the substrate. It becomes.
- the second parallel pn structure is provided in order to easily achieve a high breakdown voltage (in order to easily spread the depletion layer in the off state).
- the impurity concentration of the second parallel pn structure is lower than the impurity concentration of the first parallel pn structure.
- the repetition pitch P2 of the second parallel pn structure is narrower than the repetition pitch P1 of the first parallel pn structure.
- An oxide film 15 is provided on the surface (substrate front side) of the second parallel pn structure.
- the oxide film 15 is formed so that its film thickness gradually increases from the drain / drift part 2 to the element peripheral part 22.
- a field plate electrode FP extended from the source electrode 10 is formed on the oxide film 15 and covers the second parallel pn structure.
- An n-type channel stopper region 14 is formed outside the device peripheral portion 22, and a stopper electrode 16 is in conductive contact with the substrate front surface side of the n-type channel stopper region 14.
- n buffer layer 11 is provided on the other surface (substrate back side) of the drain / drift portion 2.
- the n buffer layer 11 extends to the outer periphery (side surface of the substrate) of the element peripheral portion 22 and is connected to the n-type channel stopper region 14.
- the built-in diode composed of the first p-type region 2b and the first n-type region 2a is reversely recovered (the built-in diode is reversed from the forward direction to the reverse direction with the gate and the source short-circuited). The carrier accumulation layer when applied).
- the impurity concentration of the n buffer layer 11 is such that when the drain-base depletion layer is in the OFF state, the n + drain layer (first conductivity type low resistance layer) 1 and the p + drain region (second conductivity type low resistance layer) which will be described later. ) Set not to reach 17.
- the drain-base depletion layer does not reach the p + drain region 17 in the off state, the outermost peripheral p base region 3b, the second parallel pn structure, the n buffer layer 11 and the p + drain region 17 Since the parasitic pnp transistor made of is not operated, the amount of accumulated carriers in the element peripheral portion 22 can be reduced.
- An n + drain layer 1 is provided on the surface layer on the back side of the substrate of the n buffer layer 11 in the element active portion 21.
- a p + drain region 17 is selectively provided in the surface layer on the substrate rear surface side of the n buffer layer 11 in the element peripheral portion 22.
- An n + drain layer 1 is provided in a portion other than the p + drain region 17 on the surface layer of the n buffer layer 11 on the back side of the substrate.
- the p + drain region 17 has a function of suppressing the injection of electrons from the n + drain layer 1 on the back surface side of the substrate to the second parallel pn structure when the built-in diode is forward conducting.
- the n + drain layer 1 and the p + drain region 17 are in conductive contact with the drain electrode (output electrode) 13.
- the outer end of the p + drain region 17 is a vertical line AO perpendicular to the back surface of the substrate passing through the outer end of the bottom surface of the outermost p base region (hereinafter referred to as the outermost peripheral p base region) 3b. It is preferable that the distance between the front surface of the substrate and the n buffer layer 11 from the position (that is, the thickness of the second parallel pn structure) is more than t1. The reason is as follows.
- the outward spread (diffusion) ⁇ of holes injected from the outermost peripheral p base region 3b into the second parallel pn structure is the boundary between the outermost peripheral p base region 3b and the second parallel pn structure. 45 degrees with respect to the normal.
- holes injected from the outermost peripheral p base region 3b into the second parallel pn structure pass through the intersection point O between the vertical line AO and the substrate front surface, and are 45 degrees outward from the vertical line AO. Many injections are made in the range up to the inclined oblique line BO. Carriers are accumulated in the element peripheral portion 22 because the n + drain layer on the back surface side of the substrate with respect to the holes injected from the outermost peripheral p base region 3b on the front surface side of the substrate into the second parallel pn structure. This is because electrons are injected from the first to the second parallel pn structure.
- the inner end of the p + drain region 17 is preferably located at the boundary between the element active part 21 and the element peripheral part 22.
- the reason is that it is possible to reduce the volume of the n + drain layer 1 on the substrate rear surface side near to opposite sides of the high outermost p base region 3b and the second parallel pn structure of the electric field, the n + drain layer 1 This is because electrons injected into the second parallel pn structure can be further reduced. Therefore, the p + drain region 17 is preferably provided at least from the boundary between the element active portion 21 and the element peripheral portion 22 to the vertical line CO ′.
- the boundary between the element active part 21 and the element peripheral part 22 is a half of the width of the substrate front surface side of the p base region 3a from the end of the substrate front surface side inside the outermost peripheral p base region 3b.
- the position D is spaced outward by the width t2.
- the drain / drift portion 2 has a thickness (depth direction) of 35.0 ⁇ m, the widths of the first n-type region 2a and the first p-type region 2b are 7.0 ⁇ m (repetitive pitch P1 is 14.0 ⁇ m), The impurity concentration of one n-type region 2a and the first p-type region 2b is 3.0 ⁇ 10 15 cm ⁇ 3 .
- the width of second n-type region 12a and second p-type region 12b is 3.5 ⁇ m (repetitive pitch P2 is 7.0 ⁇ m), and the impurity concentration of second n-type region 12a and second p-type region 12b is 1.0 ⁇ 10 15 cm ⁇ 3 .
- the p base regions 3a and 3b have a diffusion depth of 3.0 ⁇ m and a surface impurity concentration of 3.0 ⁇ 10 17 cm ⁇ 3 .
- the n + source region 6 has a diffusion depth of 0.2 ⁇ m and a surface impurity concentration of 3.0 ⁇ 10 20 cm ⁇ 3 .
- the p + contact region 5 has a diffusion depth of 0.6 ⁇ m and a surface impurity concentration of 1.0 ⁇ 10 19 cm ⁇ 3 .
- the surface n-type drift region 4 has a diffusion depth of 2.5 ⁇ m and a surface impurity concentration of 2.0 ⁇ 10 16 cm ⁇ 3 .
- the n + drain layer 1 has a thickness of 0.5 ⁇ m and an impurity concentration of 1.0 ⁇ 10 19 cm ⁇ 3 .
- the p + drain region 17 has a thickness of 0.5 ⁇ m and an impurity concentration of 1.0 ⁇ 10 18 cm ⁇ 3 .
- the n buffer layer 11 has a thickness of 7 ⁇ m and an impurity concentration of 1.0 ⁇ 10 15 cm ⁇ 3 .
- the n-type channel stopper region 14 has a width of 30.0 ⁇ m and an impurity concentration of 6.0 ⁇ 10 15 cm ⁇ 3 .
- the impurity concentration (impurity amount) of the parallel pn structure means the carrier concentration (carrier amount).
- the impurity concentration and the carrier concentration can be regarded as equivalent in a region where sufficient activation has been performed.
- the impurity amount and the carrier amount can be regarded as being equal in a region where sufficient activation has been performed. Therefore, in this specification, for convenience, the impurity concentration includes the carrier concentration, and the impurity amount includes the carrier amount.
- the electrical characteristics of the superjunction semiconductor device according to the first embodiment will be described.
- a superjunction MOSFET when a built-in diode composed of a first p-type region and a first n-type region reversely recovers, the first parallel pn structure is pinched off, and at the same time, the accumulated carriers are in the p base region and n + Exhaled to the drain layer. For this reason, at the time of reverse recovery of the built-in diode, carriers are depleted in the element active portion. On the other hand, at the periphery of the element, the depletion layer gradually spreads as the applied voltage increases, so that carriers (accumulated carriers) remain in the neutral region.
- the accumulated carriers remaining in the neutral region concentrate and flow into the outermost p base region (hereinafter referred to as the outermost peripheral p base region) having a high electric field.
- the reverse recovery tolerance is limited.
- the super-junction MOSFET according to the first embodiment by reducing the volume of the n + drain layer 1 and a part of the n + drain layer 1 in the peripheral region 22 to the p + drain region 17, p + Electron injection from the drain region 17 to the second parallel pn structure is suppressed, and the amount of accumulated carriers in the element peripheral portion 22 is reduced.
- the carrier lifetime of the second parallel pn structure of the element peripheral portion 22 is made shorter than the carrier lifetime of the first parallel pn structure of the element active portion 21. Therefore, the leakage current in the off state is small and low loss can be achieved.
- the conventional superjunction in which the carrier lifetime of the second parallel pn structure at the periphery of the element is shortened by applying the local lifetime technique Since it is not necessary to shorten the carrier lifetime of the second parallel pn structure of the element peripheral portion 22 as the MOSFET, it is possible to suppress a significant increase in leakage current in the off state.
- the first and second parallel pn are formed on the front surface of the n-type semiconductor substrate composed of the n buffer layer 11 or the low resistance and the n buffer layer 11 with a thickness of, for example, about 600 ⁇ m by a general multi-stage epitaxial growth method.
- a structure and an n-type channel stopper region 14 are formed.
- an n epitaxial layer is grown on the n buffer layer 11.
- n-type impurities such as phosphorus (P) are ion-implanted from the screen oxide film over the entire surface of the n epitaxial layer.
- a resist mask (a portion corresponding to the formation region of the first and second p-type regions 2b and 12b is opened on the n epitaxial layer based on the repetition pitches P1 and P2 of the first and second parallel pn structures) (Not shown).
- a p-type impurity such as boron is ion-implanted from the screen oxide film into the n epitaxial layer exposed in the opening of the resist mask to selectively form a p-type impurity region inside the n epitaxial layer.
- the n epitaxial layer for sealing is further formed on the outermost surface. Laminate the layers (cap deposition process).
- each p-type impurity region formed inside the n epitaxial layer is activated by heat treatment.
- the p-type impurity regions facing each other in the depth direction are connected between the n epitaxial layers stacked by the multistage epitaxial process, and the first and second p-type regions 2b and 12b are formed.
- the n epitaxial layers remaining between the first and second p-type regions 2b and 12b become the first and second n-type regions 2a and 12a.
- first and second parallel pn structures are formed.
- an epitaxial substrate in which the first and second parallel pn structures and the n-type channel stopper region 14 are stacked on the n semiconductor substrate to be the n buffer layer 11 is manufactured.
- a MOS gate structure of the element active portion 21 and a front surface electrode (source electrode 10 or the like) are formed on the front surface side of the epitaxial substrate by a general method.
- the back surface of the epitaxial substrate (the surface on the n buffer layer 11 side) is ground to reduce the thickness of the epitaxial substrate to about 50 ⁇ m, for example.
- a resist mask having an opening corresponding to a region where the n + drain layer 1 is formed is formed on the back surface of the epitaxial substrate (the surface of the n buffer layer 11).
- n-type impurities are ion-implanted using this resist mask as a mask to form an n + drain layer 1 on the front surface layer of the epitaxial substrate.
- the resist mask used for forming the n + drain layer 1 is removed.
- a resist mask is formed on the back surface of the epitaxial substrate so as to cover the n + drain layer 1 and open a portion corresponding to the formation region of the p + drain region 17.
- p-type impurities are ion-implanted to form a p + drain region 17 in the front surface layer of the epitaxial substrate. Then, the resist mask used for forming the p + drain region 17 is removed. The order of ion implantation for forming the n + drain layer 1 and ion implantation for forming the p + drain region 17 may be reversed. Thereafter, the n + drain layer 1 and the p + drain region 17 are activated by heat treatment, whereby the super junction MOSFET shown in FIG. 1 is completed.
- the volume of the n + drain layer in the device peripheral portion is reduced. Therefore, injection of electrons from the n + drain layer on the back surface side of the substrate into the second parallel pn structure is suppressed, and accordingly, the second parallel pn structure starts from the outermost peripheral p base region on the front surface side of the substrate. Hole injection into the substrate is suppressed. Thereby, the amount of accumulated carriers in the peripheral portion of the element can be reduced, and current concentration in the outermost peripheral p base region in the reverse recovery process of the built-in diode can be reduced. Therefore, reverse recovery tolerance (breakdown tolerance) can be improved.
- the off state is lower than in the prior art.
- the leakage current becomes small, the loss can be reduced.
- FIG. 2 is a cross-sectional view illustrating the structure of the semiconductor device according to the second embodiment.
- the superjunction semiconductor device according to the second embodiment is different from the superjunction semiconductor device according to the first embodiment in that an n-type bulk region 31 continuous with the first parallel pn structure is used instead of the second parallel pn structure.
- the p-type RESURF region 32 is provided in the surface layer on the front surface side of the substrate in the n-type bulk region 31.
- the n-type bulk region 31 is a region between the first parallel pn structure provided from the element active part 21 to the element peripheral part 22 and the n-type channel stopper region 14 provided on the outermost part of the element peripheral part 22. It is.
- the p-type RESURF region 32 is selectively provided in the surface layer on the substrate front surface side of the n-type bulk region 31 so as to be in contact with the outermost peripheral p base region 3b.
- the oxide film 15 is provided on the surfaces of the n-type bulk region 31 and the p-type RESURF region 32 (surface on the substrate front side).
- Other configurations of the superjunction semiconductor element according to the second embodiment are the same as those of the superjunction semiconductor element according to the first embodiment.
- an epitaxial substrate is manufactured by a general multistage epitaxial growth method.
- an n-type bulk region 31 is formed in the element peripheral portion 22 of the epitaxial substrate instead of the second parallel pn structure.
- an element structure similar to that of the first embodiment and the p-type RESURF region 32 are formed on the front surface side and the back surface side of the epitaxial substrate, thereby completing the super junction MOSFET shown in FIG.
- the p + drain region is provided in a part of the n + drain layer even if the peripheral portion of the element has an n-type bulk region. In this case, the same effect as in the first embodiment can be obtained.
- FIG. 3 is a cross-sectional view illustrating the structure of the semiconductor device according to the third embodiment.
- the superjunction semiconductor device according to the third embodiment is different from the superjunction semiconductor device according to the first embodiment in that the outer end portion of the p + drain region 41 extends to the outer periphery (side surface of the substrate) of the device peripheral portion 22. It is a point that has been.
- Other configurations of the superjunction semiconductor element according to the third embodiment are the same as those of the superjunction semiconductor element according to the first embodiment.
- the super junction semiconductor device manufacturing method according to the third embodiment is the same as the super junction semiconductor device manufacturing method according to the first embodiment except that the formation range of the p + drain region 41 is different.
- the same effect as in the first embodiment can be obtained. Further, according to the third embodiment, electrons are injected from the n + drain layer into the second parallel pn structure, compared to the case where the p + drain region is provided in a part of the n + drain layer at the periphery of the element. This greatly reduces the amount of accumulated carriers.
- FIG. 4 is a cross-sectional view showing the structure of the semiconductor device according to the fourth embodiment.
- the superjunction semiconductor device according to the fourth embodiment is different from the superjunction semiconductor device according to the third embodiment in that the n + drain layer 1 is interposed between the p ++ drain region 51 and the n buffer layer 11. It is a point.
- the p ++ drain region 51 is provided in the surface layer on the back side of the substrate of the n + drain layer 1 and is not in contact with the n buffer layer 11.
- a p-type RESURF region 52 in contact with the outermost peripheral p base region 3b may be selectively provided in the surface layer on the front surface side of the second parallel pn structure substrate.
- Other configurations of the superjunction semiconductor element according to the fourth embodiment are the same as those of the superjunction semiconductor element according to the third embodiment.
- the dimensions and impurity concentration of each part take the following values.
- the n + drain layer 1 has a thickness of 0.5 ⁇ m and an impurity concentration of 1.0 ⁇ 10 18 cm ⁇ 3 .
- the p ++ drain region 51 has a thickness of 0.3 ⁇ m and an impurity concentration of 2.0 ⁇ 10 18 cm ⁇ 3 .
- the dimensions and impurity concentrations of other parts of the superjunction MOSFET according to the fourth embodiment are the same as those of the superjunction MOSFET according to the first embodiment.
- a process for producing an epitaxial substrate by a general multi-stage epitaxial growth method a process for forming a surface element structure on the front surface of the epitaxial substrate, and an epitaxial process by grinding the back surface of the epitaxial substrate. Steps for reducing the thickness of the substrate are sequentially performed.
- the MOS gate structure and front surface electrode of the element active portion 21 are formed as in the first embodiment, and the element A p-type RESURF region 52 is formed in the peripheral portion 22.
- first ion implantation of n-type impurities is performed on the entire back surface of the epitaxial substrate (the surface of the n buffer layer 11), and the n + drain layer 1 is formed on the surface layer on the back surface of the epitaxial substrate.
- a resist mask having an opening corresponding to the formation region of the p ++ drain region 51 is formed on the back surface of the epitaxial substrate.
- the resist mask p-type impurities are second ion implantation as a mask, the inside of the n + drain layer 1, forming a p ++ drain region 51 with depth less than the depth of the n + drain layer 1 .
- the p ++ drain region 51 is formed by inverting the n + drain layer 1 exposed in the opening of the resist mask to p-type. For this reason, the impurity concentration of the p ++ drain region 51 is set higher than the impurity concentration of the n + drain layer 1.
- the resist mask used to form the p ++ drain region 51 is removed. Thereafter, the n + drain layer 1 and the p ++ drain region 51 are activated by heat treatment, thereby completing the super junction MOSFET shown in FIG.
- the same effect as in the third embodiment can be obtained.
- the n + drain layer is interposed between the p ++ drain region and the n buffer layer, also the injection of holes from the p ++ drain region to the n buffer layer suppressed can do.
- the operation of the parasitic pnp transistor including the outermost peripheral p base region, the second parallel pn structure, the n buffer layer, and the p ++ drain region is suppressed, and the carrier accumulation amount in the element peripheral portion 22 is further reduced. Thereby, reverse recovery tolerance can further be improved.
- the element active portion formed on the first main surface side of the substrate is a switching including a channel diffusion layer and a source region forming an inversion layer on the first main surface side in the case of a vertical MOSFET, for example.
- This is an active part or passive part having a selection function of conduction and non-conduction on the first main surface side of the drift part. Therefore, the present invention can be applied not only to MOSFET but also to FWD or Schottky diode.
- the first conductivity type is n-type and the second conductivity type is p-type.
- the first conductivity type is p-type and the second conductivity type is n-type. It holds.
- the semiconductor element according to the present invention is useful for a high-power semiconductor device, and in particular, it is possible to achieve both a high breakdown voltage and a large current capacity, such as a MOSFET having a parallel pn structure in a drift portion. Useful for power semiconductor devices.
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Abstract
Description
実施の形態1にかかる半導体素子の構造について、プレーナゲート構造のnチャネル縦型MOSFETを例に説明する。図1は、実施の形態1にかかる半導体素子の構造を示す断面図である。図1に示す実施の形態1にかかる半導体素子は、第1の並列pn構造のドレイン・ドリフト部(縦型ドリフト部)2を備えた超接合MOSFETである。ドレイン・ドリフト部2の一方の表面側(以下、基板おもて面側とする)の表面層には、素子活性部21となる高不純物濃度のpベース領域3aが選択的に設けられている。基板とは、後述するエピタキシャル基板である。
実施の形態2にかかる超接合半導体素子の構造について説明する。図2は、実施の形態2にかかる半導体素子の構造を示す断面図である。実施の形態2にかかる超接合半導体素子が実施の形態1にかかる超接合半導体素子と異なる点は、第2の並列pn構造に代えて、第1の並列pn構造に連続するn型バルク領域31を設け、n型バルク領域31の基板おもて面側の表面層にp型リサーフ領域32を設けた点である。
実施の形態3にかかる超接合半導体素子の構造について説明する。図3は、実施の形態3にかかる半導体素子の構造を示す断面図である。実施の形態3にかかる超接合半導体素子が実施の形態1にかかる超接合半導体素子と異なる点は、p+ドレイン領域41の外側の端部が素子周縁部22の外周(基板側面)まで延在されている点である。実施の形態3にかかる超接合半導体素子のそれ以外の構成は、実施の形態1にかかる超接合半導体素子と同様である。実施の形態3にかかる超接合MOSFETの製造方法のp+ドレイン領域41の形成範囲が異なる以外は、実施の形態1にかかる超接合半導体素子の製造方法と同様である。
実施の形態4にかかる超接合半導体素子の構造について説明する。図4は、実施の形態4にかかる半導体素子の構造を示す断面図である。実施の形態4にかかる超接合半導体素子が実施の形態3にかかる超接合半導体素子と異なる点は、p++ドレイン領域51とnバッファ層11との間に、n+ドレイン層1が介在している点である。具体的には、p++ドレイン領域51は、n+ドレイン層1の基板裏面側の表面層に設けられており、nバッファ層11に接していない。第2の並列pn構造の基板おもて面側の表面層に、最外周pベース領域3bに接するp型リサーフ領域52を選択的に設けてもよい。実施の形態4にかかる超接合半導体素子のそれ以外の構成は、実施の形態3にかかる超接合半導体素子と同様である。
2 ドレイン・ドリフト部
2a 第1のn型領域
2b 第1のp型領域
3a pベース領域
3b 最外周pベース領域
4 表面n型ドリフト領域
5 p+コンタクト領域
6 n+ソース領域
7 ゲート絶縁膜
8 ゲート電極層
9 層間絶縁膜
10 ソース電極
11 nバッファ層
12a 第2のn型領域
12b 第2のp型領域
13 ドレイン電極
14 n型チャネルストッパー領域
15 酸化膜
16 ストッパー電極
17,41 p+ドレイン領域
21 素子活性部
22 素子周縁部
31 n型バルク領域
32,52 p型リサーフ領域
51 p++ドレイン領域
D 素子活性部と素子周縁部との境界の位置
FP フィールドプレート電極
P1 素子活性部の第1の並列pn構造の繰り返しピッチ
P2 素子周縁部の第2の並列pn構造の繰り返しピッチ
t1 p+ドレイン領域の最小幅
t2 pベース領域3aの基板おもて面側の幅の半分の幅
Claims (7)
- 基板の第1主面側に存在して能動または受動で電流を流す素子活性部と、前記基板の第2主面側の表面層に存在する第1導電型低抵抗層と、前記素子活性部と前記第1導電型低抵抗層との間に介在し、オン状態ではドリフト電流が縦方向に流れるとともにオフ状態では空乏化する縦型ドリフト部と、を有し、前記縦型ドリフト部が、前記基板の厚み方向に配向する第1の縦型第1導電型領域と前記基板の厚み方向に配向する第1の縦型第2導電型領域とが交互に繰り返し接合してなる第1の並列pn構造をなす半導体素子であって、
前記縦型ドリフト部の周りで前記第1主面と前記第1導電型低抵抗層との間に介在し、オン状態では概ね非電路領域であってオフ状態では空乏化する素子周縁部と、
前記第1の並列pn構造と前記第1導電型低抵抗層との間に、前記素子活性部から前記素子周縁部にわたって設けられた、前記第1導電型低抵抗層よりも高抵抗な第1導電型層と、
前記素子周縁部における前記第2主面側の表面層に選択的に設けられた第2導電型低抵抗層と、
前記第1導電型低抵抗層および前記第2導電型低抵抗層に接する出力電極と、
を備えることを特徴とする半導体素子。 - 前記第2導電型低抵抗層の不純物濃度は、前記第1導電型層の不純物濃度よりも高いことを特徴とする請求項1に記載の半導体素子。
- 前記第2導電型低抵抗層の不純物濃度は、前記第1導電型低抵抗層の不純物濃度よりも高いことを特徴とする請求項1に記載の半導体素子。
- 前記第1主面側に設けられた複数の第2導電型ベース領域をさらに有し、
前記第2導電型低抵抗層の内側の端部は、前記素子活性部と前記素子周縁部との境界に位置し、
前記第2導電型低抵抗層の外側の端部は、複数の前記第2導電型ベース領域のうちの最も外側に設けられた第2導電型ベース領域の外側の端部から、前記縦型ドリフト部の厚さ以上外側へ離れて位置していることを特徴とする請求項1に記載の半導体素子。 - 前記第2導電型低抵抗層は、前記素子活性部と前記素子周縁部との境界から前記素子周縁部の外周にわたって設けられていることを特徴とする請求項1に記載の半導体素子。
- 前記第2導電型低抵抗層は、前記第1導電型低抵抗層の前記第2主面側の表面層に設けられており、
前記第2導電型低抵抗層と前記第1導電型層との間に前記第1導電型低抵抗層が介在することを特徴とする請求項1に記載の半導体素子。 - 前記素子周縁部は、前記基板の厚み方向に配向する第2の縦型第1導電型領域と前記基板の厚み方向に配向する第2の縦型第2導電型領域とが交互に繰り返し接合してなる第2の並列pn構造をなすことを特徴とする請求項1~6のいずれか一つに記載の半導体素子。
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JP2014557358A JPWO2014112239A1 (ja) | 2013-01-16 | 2013-12-05 | 半導体素子 |
CN201380047274.XA CN104620388A (zh) | 2013-01-16 | 2013-12-05 | 半导体元件 |
DE201311004146 DE112013004146T5 (de) | 2013-01-16 | 2013-12-05 | Halbleitervorrichtung |
US14/643,651 US9437727B2 (en) | 2013-01-16 | 2015-03-10 | Semiconductor element including active region, low resistance layer and vertical drift portion |
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US14/643,651 Continuation US9437727B2 (en) | 2013-01-16 | 2015-03-10 | Semiconductor element including active region, low resistance layer and vertical drift portion |
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JP (1) | JPWO2014112239A1 (ja) |
CN (1) | CN104620388A (ja) |
DE (1) | DE112013004146T5 (ja) |
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JP2019521529A (ja) * | 2016-11-01 | 2019-07-25 | 杭州士▲蘭▼▲微▼▲電▼子股▲ふん▼有限公司 | パワーデバイス及びその製造方法 |
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DE102014109208A1 (de) * | 2014-07-01 | 2016-01-07 | Infineon Technologies Austria Ag | Ladungskompensationsvorrichtung und ihre herstellung |
JP6319453B2 (ja) * | 2014-10-03 | 2018-05-09 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
DE102015102136B4 (de) * | 2015-02-13 | 2021-09-30 | Infineon Technologies Austria Ag | Halbleiterbauelemente und ein verfahren zum bilden eines halbleiterbauelements |
US10529799B2 (en) * | 2016-08-08 | 2020-01-07 | Mitsubishi Electric Corporation | Semiconductor device |
JP6747195B2 (ja) | 2016-09-08 | 2020-08-26 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
CN106952946B (zh) * | 2017-04-19 | 2023-09-22 | 华润微电子(重庆)有限公司 | 一种过渡区结构 |
CN109256422B (zh) * | 2017-07-12 | 2022-04-29 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法和电子装置 |
CN110265299A (zh) * | 2019-05-17 | 2019-09-20 | 厦门芯达茂微电子有限公司 | 一种反向导通场截止型超结igbt及其制作方法 |
CN112234056B (zh) * | 2020-09-03 | 2024-04-09 | 深圳市汇德科技有限公司 | 一种半导体器件 |
CN111933691B (zh) * | 2020-10-12 | 2021-01-29 | 中芯集成电路制造(绍兴)有限公司 | 超结器件及其制造方法 |
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JP2004022716A (ja) * | 2002-06-14 | 2004-01-22 | Fuji Electric Holdings Co Ltd | 半導体素子 |
JP2009283781A (ja) * | 2008-05-23 | 2009-12-03 | Mitsubishi Electric Corp | 半導体装置 |
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CN1019720B (zh) | 1991-03-19 | 1992-12-30 | 电子科技大学 | 半导体功率器件 |
JPH09266311A (ja) | 1996-01-22 | 1997-10-07 | Fuji Electric Co Ltd | 半導体装置及びその製造方法 |
GB2309336B (en) | 1996-01-22 | 2001-05-23 | Fuji Electric Co Ltd | Semiconductor device |
JP4126915B2 (ja) | 2002-01-30 | 2008-07-30 | 富士電機デバイステクノロジー株式会社 | 半導体装置 |
JP2007173418A (ja) * | 2005-12-20 | 2007-07-05 | Toshiba Corp | 半導体装置 |
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2013
- 2013-12-05 WO PCT/JP2013/082747 patent/WO2014112239A1/ja active Application Filing
- 2013-12-05 CN CN201380047274.XA patent/CN104620388A/zh active Pending
- 2013-12-05 JP JP2014557358A patent/JPWO2014112239A1/ja active Pending
- 2013-12-05 DE DE201311004146 patent/DE112013004146T5/de not_active Withdrawn
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Patent Citations (3)
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JPH077154A (ja) * | 1993-03-25 | 1995-01-10 | Siemens Ag | パワーmosfet |
JP2004022716A (ja) * | 2002-06-14 | 2004-01-22 | Fuji Electric Holdings Co Ltd | 半導体素子 |
JP2009283781A (ja) * | 2008-05-23 | 2009-12-03 | Mitsubishi Electric Corp | 半導体装置 |
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JP2019521529A (ja) * | 2016-11-01 | 2019-07-25 | 杭州士▲蘭▼▲微▼▲電▼子股▲ふん▼有限公司 | パワーデバイス及びその製造方法 |
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TW201436234A (zh) | 2014-09-16 |
TWI621268B (zh) | 2018-04-11 |
DE112013004146T5 (de) | 2015-05-13 |
JPWO2014112239A1 (ja) | 2017-01-19 |
US20150187930A1 (en) | 2015-07-02 |
US9437727B2 (en) | 2016-09-06 |
CN104620388A (zh) | 2015-05-13 |
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