JP5065517B2 - 基板テーブル、および基板リリース特性を向上させる方法 - Google Patents
基板テーブル、および基板リリース特性を向上させる方法 Download PDFInfo
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- JP5065517B2 JP5065517B2 JP2011238385A JP2011238385A JP5065517B2 JP 5065517 B2 JP5065517 B2 JP 5065517B2 JP 2011238385 A JP2011238385 A JP 2011238385A JP 2011238385 A JP2011238385 A JP 2011238385A JP 5065517 B2 JP5065517 B2 JP 5065517B2
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- substrate
- substrate table
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70691—Handling of masks or workpieces
- G03F7/707—Chucks, e.g. chucking or un-chucking operations or structural details
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70691—Handling of masks or workpieces
- G03F7/707—Chucks, e.g. chucking or un-chucking operations or structural details
- G03F7/70708—Chucks, e.g. chucking or un-chucking operations or structural details being electrostatic; Electrostatically deformable vacuum chucks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/6875—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a plurality of individual support members, e.g. support posts or protrusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68757—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a coating or a hardness or a material
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Description
Claims (13)
- 基板を支持するための基板テーブルであって、
前記基板をクランプするチャックと、
前記基板の第1表面の対応する部分を支持する前記チャックに結合された複数の突起部と、
を備え、
少なくとも1つの前記突起部の第1表面が単分子層を備え、
前記基板を支持する際に、少なくとも1つの前記突起部の前記第1表面が前記基板の前記第1表面に対向する、
基板テーブル。 - 前記突起部はバールである、請求項1に記載の基板テーブル。
- 前記単分子層は弾性である、請求項1又は2に記載の基板テーブル。
- 前記単分子層は、化学的に実質的に非反応性の端部を有する、請求項1〜3のいずれかに記載の基板テーブル。
- 前記単分子層は、バッキーボール、ガラスパール、ポリマー分子またはナノチューブ、あるいはそれらの任意の組合せを含む、請求項1〜4のいずれかに記載の基板テーブル。
- 前記単分子層は、有機分子、芳香族分子、脂肪族分子、有極性分子、無極性分子、ハロゲン化分子またはフッ化分子、あるいはそれらの任意の組合せを含む、請求項1〜4のいずれかに記載の基板テーブル。
- 前記単分子層は、酸化物分子、窒化物分子またはテフロン(登録商標)分子、あるいはそれらの任意の組合せを含む、請求項1〜4のいずれかに記載の基板テーブル。
- 前記単分子層の厚さは、1〜30nmである、請求項1〜7のいずれかに記載の基板テーブル。
- 前記基板テーブルは前記リソグラフィ装置の一部を形成する、請求項1〜8のいずれかに記載の基板テーブル。
- 前記基板テーブルはイオン注入装置またはエッチングデバイスの一部を形成する、請求項1〜8のいずれかに記載の基板テーブル。
- 基板を支持する基板テーブルにおける突起部の基板リリース特性を向上させるための方法であって、
前記基板テーブルのチャックへ複数の突起部を結合させること、
前記基板テーブルの複数の突起部の少なくとも1つの第1表面に単分子層を配置すること、
を含む方法。 - 少なくとも1つの前記突起部の前記第1表面に有機分子を含むウェット溶液を塗布すること、
その後に紫外線源に対して前記溶液をさらす、または前記溶液を表面結合と化学反応させて、少なくとも1つの前記突起部の前記第1表面上に前記単分子層を形成すること、
をさらに含む請求項11に記載の方法。 - プラズマ化学気相分解プロセス、または、フィルタ高電流アークプロセスを実施して、少なくとも1つの前記突起部の前記第1表面上に前記単分子層を形成することをさらに含む、請求項11に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/645,812 US7791708B2 (en) | 2006-12-27 | 2006-12-27 | Lithographic apparatus, substrate table, and method for enhancing substrate release properties |
US11/645,812 | 2006-12-27 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009543972A Division JP4857381B2 (ja) | 2006-12-27 | 2007-12-17 | リソグラフィ装置、基板テーブル、および基板リリース特性を向上させるための方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012033964A JP2012033964A (ja) | 2012-02-16 |
JP5065517B2 true JP5065517B2 (ja) | 2012-11-07 |
Family
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JP2009543972A Active JP4857381B2 (ja) | 2006-12-27 | 2007-12-17 | リソグラフィ装置、基板テーブル、および基板リリース特性を向上させるための方法 |
JP2011238385A Active JP5065517B2 (ja) | 2006-12-27 | 2011-10-31 | 基板テーブル、および基板リリース特性を向上させる方法 |
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JP2009543972A Active JP4857381B2 (ja) | 2006-12-27 | 2007-12-17 | リソグラフィ装置、基板テーブル、および基板リリース特性を向上させるための方法 |
Country Status (3)
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US (2) | US7791708B2 (ja) |
JP (2) | JP4857381B2 (ja) |
WO (1) | WO2008078992A1 (ja) |
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US10784100B2 (en) * | 2016-07-21 | 2020-09-22 | Tokyo Electron Limited | Back-side friction reduction of a substrate |
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-
2006
- 2006-12-27 US US11/645,812 patent/US7791708B2/en active Active
-
2007
- 2007-12-17 WO PCT/NL2007/050657 patent/WO2008078992A1/en active Application Filing
- 2007-12-17 JP JP2009543972A patent/JP4857381B2/ja active Active
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2010
- 2010-08-13 US US12/856,106 patent/US8792085B2/en active Active
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2011
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Also Published As
Publication number | Publication date |
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JP2010515258A (ja) | 2010-05-06 |
WO2008078992A1 (en) | 2008-07-03 |
US20080158538A1 (en) | 2008-07-03 |
US20100296073A1 (en) | 2010-11-25 |
JP4857381B2 (ja) | 2012-01-18 |
JP2012033964A (ja) | 2012-02-16 |
US7791708B2 (en) | 2010-09-07 |
US8792085B2 (en) | 2014-07-29 |
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