JP2009505403A - シールドゲート電界効果トランジスタにおけるインターポリ絶縁膜の構造および製造方法。 - Google Patents
シールドゲート電界効果トランジスタにおけるインターポリ絶縁膜の構造および製造方法。 Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 31
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000000280 densification Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
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Abstract
【選択図】図1
Description
従って、改良されたIPDおよびゲート絶縁膜を有するシールドゲートトレンチFETの構造およびその製造方法が必要とされる。
Claims (33)
- 電界効果トランジスタの製造方法であって、
第1の導電型のシリコン領域内にシールド絶縁膜によって前記シリコン領域から絶縁されたシールド電極を有するトレンチを形成するステップと、
前記シールド電極の上面に沿って熱酸化物層およびコンフォーマルな絶縁体層からなるインターポリ絶縁膜(以下IPDという)を形成するステップと、
少なくともトレンチ側壁上方を覆うゲート絶縁膜を形成するステップと、
前記IPDによってシールド電極から絶縁されたゲート電極を前記トレンチ内に形成するステップと、を含むことを特徴とする製造方法。 - 前記IPDは凹状の上面を有することを特徴とする請求項1に記載の製造方法。
- 前記IPDの前記ゲート絶縁膜に対する厚さの比率は、3:1よりも大であることを特徴とする請求項1に記載の製造方法。
- 前記ゲート絶縁膜は、前記IPD形成後に形成されることを特徴とする請求項1に記載の製造方法。
- 前記IPDを形成するステップは、
前記トレンチの側壁上方に沿っておよび前記シールド電極の上面に沿って熱酸化物層を形成するステップと、
前記トレンチをコンフォーマルな絶縁体層で満たすステップと、
前記コンフォーマルな絶縁体層および前記熱酸化物層を部分的に除去するステップと、を含み、
前記IPDは、前記熱酸化物層の残存部分と前記コンフォーマルな絶縁体層の残存部分とからなることを特徴とする請求項1に記載の製造方法。 - 前記熱酸化物層を形成するステップは、前記トレンチの側壁に沿う部分よりも前記シールド絶縁膜の上面に沿う部分の方がより厚い熱酸化物層が形成されるように熱的にシリコンを酸化するステップを含むことを特徴とする請求項5に記載の製造方法。
- 前記部分的に除去するステップは、前記トレンチに隣接するシリコン表面および前記トレンチ側壁の上方に沿った全ての絶縁膜を完全に除去するステップであることを特徴とする請求項5に記載の製造方法。
- 前記満たすステップは、コンフォーマルな酸化物層を堆積し、前記トレンチを満たすステップを含むことを特徴とする請求項5に記載の製造方法。
- 前記部分的に除去するステップは、前記コンフォーマルな絶縁体層および前記熱酸化物層を前記トレンチ内の所望深さにまで等方的にエッチバックするステップを含み、
前記コンフォーマルな絶縁体層の残存部分が、その底面および前記コンフォーマルな絶縁体層の残存部分の側壁に沿った前記熱酸化物層の残存部分に囲まれていることを特徴とする請求項5に記載の製造方法。 - 前記トレンチを形成するステップは、
前記トレンチの側壁および底面を覆うシールド絶縁膜を形成するステップと、
前記トレンチ内に埋め込まれたシールド電極を形成するステップと、
少なくともトレンチの側壁上方に沿って前記シールド絶縁膜の薄い層が残るように前記シールド絶縁膜の露出部分を部分的に除去するステップと、を含むことを特徴とする請求項1に記載の製造方法。 - 前記シリコン領域内に第2の導電型のウェル領域を形成するステップと、
ソース領域が前記トレンチの側方に位置するように前記ウェル領域内にソース領域を形成するステップと、を更に含むことを特徴とする請求項1に記載の製造方法。 - 前記ゲート電極、前記ソース領域および前記ウェル領域上に延在するプレメタル絶縁体層を形成するステップと、
前記プレメタル絶縁体層の所定の部分を除去して前記ウェル領域の表面に対応する部分を露出させるステップと、
前記ソース領域の側壁が露出するように露出した表面に沿って前記ウェル領域にリセスを形成するステップと、
前記ウェル領域および前記ソース領域の露出した側壁に電気的に接続するメタル層を形成するステップと、を更に含むことを特徴とする請求項11に記載の製造方法。 - 電界効果トランジスタ(FET)であって、
第1の導電型のシリコン領域内部に伸長するトレンチと、
前記トレンチの下方部分に設けられてシールド絶縁膜によって前記シリコン領域から絶縁されたシールド電極と、
前記トレンチ内に設けられてIPDによって前記シールド電極から絶縁されたゲート電極と、を含み、
前記IPDは、コンフォーマルな絶縁体層と熱酸化物層からなることを特徴とするFET。 - 前記ゲート電極は、トレンチ側壁の上方に沿って延在するゲート絶縁膜によって前記シリコン領域から絶縁されており、前記IPDの厚さの前記ゲート絶縁膜の厚さに対する比率は3:1よりも大であることを特徴とする請求項13に記載のFET。
- 前記IPDはその上面に沿って凹状の輪郭を有していることを特徴とする請求項13に記載のFET。
- 前記ゲート電極は、その底面に沿って凹状の輪郭を有していることを特徴とする請求項13に記載のFET。
- 前記コンフォーマルな絶縁体層は、その底面および側壁に沿って熱絶縁膜によって囲まれていることを特徴とする請求項13に記載のFET。
- 前記コンフォーマルな絶縁体層は、凸状の底面および凹状の上面を有していることを特徴とする請求項13に記載のFET。
- 前記シールド電極は曲面状の上面を有していることを特徴とする請求項13に記載のFET。
- 前記シリコン領域は、第1の導電型のサブストレート上に延在する第1の導電型のエピタキシャル層と、前記エピタキシャル層内に設けられた第2の導電型のウェル領域と、前記ウェル領域内に設けられた第1の導電型のソース領域とを含み、前記ソース領域は前記トレンチの側方に位置していることを特徴とする請求項13に記載のFET。
- 前記トレンチは、前記エピタキシャル層内まで伸長し終端していることを特徴とする請求項20に記載のFET。
- 前記トレンチは前記エピタキシャル層を貫通し、前記サブストレート内において終端するように伸長していることを特徴とする請求項20に記載のFET。
- 電界効果トランジスタ(FET)であって、
第1の導電型のシリコン領域内に伸長するトレンチと、
前記トレンチの下方部分に設けられてシールド絶縁膜によって前記シリコン領域から絶縁されたシールド電極と、
前記トレンチ内に設けられて、その上面に沿った凹状の輪郭を有するIPDによって前記シールド電極から絶縁されたゲート電極と、を含むことを特徴とするFET。 - 前記シールド電極は曲面状の上面を有していることを特徴とする請求項23に記載のFET。
- 前記シリコン領域は、第1の導電型のサブストレート上に延在する第1の導電型のエピタキシャル層と、前記エピタキシャル層内に設けられた第2の導電型のウェル領域と、前記ウェル領域内に設けられた第1の導電型のソース領域とを含み、前記ソース流域は前記トレンチの側方に位置していることを特徴とする請求項23に記載のFET。
- 前記トレンチは前記エピタキシャル層内まで伸長し終端していることを特徴とする請求項25に記載のFET。
- 前記トレンチは前記エピタキシャル層を貫通し、前記サブストレート内において終端するように伸長していることを特徴とする請求項25に記載のFET。
- 電界効果トランジスタ(FET)であって、
第1の導電型のシリコン領域内部に伸長するトレンチと、
前記トレンチの下方部分に設けられてシールド絶縁膜によって前記シリコン領域から絶縁されたシールド電極と、
前記トレンチ内に設けられてIPDによって前記シールド電極から絶縁されたゲート電極と、を含み、
前記IPDは、その底面に沿った凸状の輪郭とその上面に沿った凹状の輪郭を有するコンフォーマルな絶縁体層を含むことを特徴とするFET。 - 前記ゲート電極は、その底面に沿って凹状の輪郭を有していることを特徴とする請求項28に記載のFET。
- 前記IPDは、その底面および側壁に沿って前記コンフォーマルな絶縁体層を囲む熱絶縁膜を更に含むことを特徴とする請求項28に記載のFET。
- 前記シリコン領域は、第1の導電型のサブストレート上に延在する第1の導電型のエピタキシャル層と、前記エピタキシャル層内に設けられた第2の導電型のウェル領域と、前記ウェル領域内に設けられた第1の導電型のソース領域とを含み、前記ソース流域は前記トレンチの側方に位置していることを特徴とする請求項28に記載のFET。
- 前記トレンチは前記エピタキシャル層内まで伸長し終端していることを特徴とする請求項31に記載のFET。
- 前記トレンチは前記エピタキシャル層を貫通し、前記サブストレート内において終端するように伸長していることを特徴とする請求項31に記載のFET。
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US11/201,400 US7385248B2 (en) | 2005-08-09 | 2005-08-09 | Shielded gate field effect transistor with improved inter-poly dielectric |
PCT/US2006/030944 WO2007021701A2 (en) | 2005-08-09 | 2006-08-04 | Structure and method for forming inter-poly dielectric in a shielded gate field effect transistor |
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Cited By (13)
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JP2013508984A (ja) * | 2009-10-21 | 2013-03-07 | ヴィシェイ−シリコニックス | 曲線状のゲート酸化物プロファイルを有するスプリットゲート半導体素子 |
JP2014056913A (ja) * | 2012-09-12 | 2014-03-27 | Sumitomo Electric Ind Ltd | 炭化珪素半導体装置 |
US9306056B2 (en) | 2009-10-30 | 2016-04-05 | Vishay-Siliconix | Semiconductor device with trench-like feed-throughs |
US9425305B2 (en) | 2009-10-20 | 2016-08-23 | Vishay-Siliconix | Structures of and methods of fabricating split gate MIS devices |
US9543412B2 (en) | 2012-09-12 | 2017-01-10 | Sumitomo Electric Industries, Ltd. | Method for manufacturing silicon carbide semiconductor device |
US9577089B2 (en) | 2010-03-02 | 2017-02-21 | Vishay-Siliconix | Structures and methods of fabricating dual gate devices |
JP2018046253A (ja) * | 2016-09-16 | 2018-03-22 | 株式会社東芝 | 半導体装置およびその製造方法 |
JPWO2017168733A1 (ja) * | 2016-03-31 | 2018-04-05 | 新電元工業株式会社 | 半導体装置の製造方法及び半導体装置 |
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Also Published As
Publication number | Publication date |
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CN101800245B (zh) | 2013-03-27 |
TWI417963B (zh) | 2013-12-01 |
DE112006002077T5 (de) | 2008-07-03 |
JP5075823B2 (ja) | 2012-11-21 |
US7385248B2 (en) | 2008-06-10 |
WO2007021701A3 (en) | 2007-09-13 |
US20070037327A1 (en) | 2007-02-15 |
KR101221242B1 (ko) | 2013-01-11 |
TW200715416A (en) | 2007-04-16 |
MY141412A (en) | 2010-04-30 |
US7598144B2 (en) | 2009-10-06 |
CN101238581B (zh) | 2010-04-14 |
AT504736A2 (de) | 2008-07-15 |
WO2007021701A2 (en) | 2007-02-22 |
US20080090339A1 (en) | 2008-04-17 |
DE112006002077B4 (de) | 2020-01-02 |
CN101238581A (zh) | 2008-08-06 |
CN101800245A (zh) | 2010-08-11 |
KR20080035686A (ko) | 2008-04-23 |
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