TWI227540B - Method for forming rounding corner in the trench - Google Patents
Method for forming rounding corner in the trench Download PDFInfo
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12275401227540
發明所屬之技術領域 本案係關於一種形成圓滑溝渠邊角之方法，尤指一種 應用於溝渠式金屬氧化半導體（trench —type m〇S)元件咬 積體電路（Integrated Circuit)元件製程中，以於溝渠中 形成圓滑邊角（rounding corner)之方法。 先前技術FIELD OF THE INVENTION The present invention relates to a method for forming smooth trench corners, and more particularly, to a method for forming trench-type metal oxide semiconductor (trench-type MOS) device integrated circuit (Integrated Circuit) device process, Method for forming rounding corners in trenches. Prior art
現今’溝渠式金屬氧化半導體（trench_type M0S)元 件或積體電路元件已廣為業界所應用。請參閱第一圖（a) 至第一圖（b )，其係為傳統製造溝渠式金氧半場效電晶體 的部分流程示意圖。如第一圖（a)所示，於製造溝渠式金 氧半場效電晶體時，首先提供一半導體基板1〇，接著於半 導體基板1 0上依序形成墊氧化層丨丨、氮化矽層丨2以及氧化 層1 3。然後，以傳統方法，例如微影與蝕刻方法，移除部 分乳化層13、氮化石夕層12、塾氧化層η以及半導體基板 1 0，以形成至少一溝渠1 4。Today's trench-type metal oxide semiconductor (trench_type MOS) devices or integrated circuit components have been widely used in the industry. Please refer to the first diagram (a) to the first diagram (b), which are schematic diagrams of part of a conventional process for manufacturing a trench-type metal-oxide-semiconductor field-effect transistor. As shown in the first figure (a), when manufacturing a trench metal-oxide-semiconductor field-effect transistor, a semiconductor substrate 10 is first provided, and then a pad oxide layer and a silicon nitride layer are sequentially formed on the semiconductor substrate 10丨 2 and the oxide layer 1 3. Then, by a conventional method, such as lithography and etching, a part of the emulsified layer 13, the nitrided layer 12, the hafnium oxide layer η, and the semiconductor substrate 10 are removed to form at least one trench 14.
由於在形成溝渠1 4時’使用電漿蝕刻通常會在溝渠J 4 側壁產生表面晶格缺陷或形成不平坦表面，因此為了解決 這個問題’會先在溝渠1 4側壁形成一犧牲氧化層 (sacrifice oxide)(未圖示），然後再移除該犧牲氧化 層。 隨後，如第一圖（b)所示，於溝渠14中及氧化層13上 形成一氧化層以作為閘極氧化層（gate oxide)或介電層 (dielectric layer)15。接著，進行後續程序，例如於溝Since the formation of trenches 14 using plasma etching usually causes surface lattice defects or uneven surfaces on the side walls of trenches J 4, a sacrificial oxide layer (sacrifice) is first formed on the side walls of trenches 14 in order to solve this problem. oxide) (not shown), and then remove the sacrificial oxide layer. Subsequently, as shown in the first figure (b), an oxide layer is formed in the trench 14 and on the oxide layer 13 to serve as a gate oxide or a dielectric layer 15. Then, follow-up procedures such as Yugou
12275401227540
五、發明說明（2) 渠14底部形成底氧化層（bottom oxide，未圖示）且/或沉 積多晶碎層（未圖不）於溝渠1 4專程序，以完成溝準式金氧 半場效電晶體之製作。 請再參閱第一圖（a)，當以電漿蝕刻方式形成溝渠14 時’通常會使溝渠14之側壁呈垂直輪廓，並使其底邊角以 近似於直角呈現’因此於後續氧化程序中，閘極氧化層或 介電層1 5會依照溝渠1 4的整體輪廓而形成。當進行後&製 程後，例如沉積多晶矽層於溝渠14且移除氧化層13、氮化 石夕層1 2與墊氧化層1 1後，由於溝渠丨4頂邊角與底邊角係以 近似於直角呈現，因此頂邊角附近之晶格會因彼此擠壓而 使其頂邊角產生邊角應力（corner stress)。另外，溝渠 1 4底邊角附近亦會產生閘極氧化層或介電層1 5厚度不均勻 的現象。 請參閱第二圖（a )與第二圖（b)，其係為習知製程步驟 所形成之溝渠於頂邊角與底邊角之掃描式電子顯微鏡圖。 由第二圖（a )可知’溝渠1 4之頂邊角以近似於直角的輪廓 呈現’此時溝渠1 4頂邊角附近的晶格會彼此擠壓，因而使 溝‘ 14產生邊角應力（corne：r stress)，因此當溝渠式金 氧半場效電晶體於操作時便會產生尖端放電的現象。另 外’由第二圖（b)可清楚地了解，溝渠1 4底邊角亦不甚圓 滑’當於溝渠1 4中形成閘極氧化層或介電層丨5時，閘極氧 化層或介電層1 5的厚度會不均勻，如此將使溝渠式金氧半 場效電晶體元件於操作時產生嚴重的漏電流（leakage current)之現象。V. Description of the invention (2) A bottom oxide layer (not shown) is formed at the bottom of the trench 14 and / or a polycrystalline debris layer (not shown) is deposited in the trench 14 for a special procedure to complete the trench quasi-metal-oxygen half field Production of effect transistor. Please refer to the first figure (a) again. When the trench 14 is formed by plasma etching, the sidewalls of the trench 14 are usually made into a vertical profile, and the bottom corners of the trench 14 are displayed at approximately right angles. Therefore, in the subsequent oxidation process, The gate oxide layer or the dielectric layer 15 is formed according to the overall contour of the trench 14. After the & process, for example, after depositing a polycrystalline silicon layer in the trench 14 and removing the oxide layer 13, the nitride layer 12 and the pad oxide layer 11, the top and bottom corners of the trench are approximated. It appears at right angles, so the lattice near the top corners will cause corner stress due to squeezing each other. In addition, the thickness of the gate oxide layer or the dielectric layer 15 may be uneven near the bottom corner of the trench 14. Please refer to the second image (a) and the second image (b), which are scanning electron microscope images of the top and bottom corners of the trench formed by the conventional process steps. From the second figure (a), it can be seen that the top corners of the trench 14 are presented in an approximately right-angled profile. At this time, the lattices near the top corners of the trench 14 will squeeze each other, so that the trench 14 will generate corner stress. (Corne: r stress), so when the trench-type metal-oxide-semiconductor half-effect transistor is operated, a tip discharge phenomenon will occur. In addition, it can be clearly understood from the second figure (b) that the bottom corner of the trench 14 is not very smooth. When the gate oxide layer or the dielectric layer is formed in the trench 14, the gate oxide layer or the dielectric layer The thickness of the electric layer 15 will be non-uniform, which will cause a serious leakage current phenomenon in the trench-type metal-oxide-semiconductor field-effect transistor element during operation.
第8頁 1227540 五、發明說明（3) / 因此，如何發展一種於溝渠式金屬氧化半導體元件或 積體電路元件製程中，以於溝渠中形成圓滑邊角之方法， 俾以避免邊角應力與閘極氧化層或介電層厚度不均勻所導 致之半導體元件尖端放電與漏電流的現象，實為目前迫切 需要解決之問題。 發明内容 本案之主要目的係提供一種於溝渠式金屬氧化半導體 元件或積體電路元件製程中，用以形成圓滑溝渠邊角之方 法，藉此可避免邊角應力與閘極氧化層或介電層厚度不均 勻之問題，進而防止半導體元件產生尖端放電與漏電流的 現象。 為達上述目的，本案提供一種形成圓滑溝渠邊角之方 法，其係應於溝渠式金屬氧化半導體元件製程中，該方法 至少包含下列步驟：（a )提供一半導體基板；（b )依序形成 一第一塾氧化層、一第一氮化砍層與一第一氧化層於半導 體基板上；（c )部份移除第一氧化層、第一氮化矽層、第 一墊氧化層與半導體基板，以形成至少一溝渠；（d )移除 鄰近溝渠之部分第一氧化層、第一氮化矽層與第一墊氧化 傷 層；（e)形成一第二墊氧化層於溝渠中；（f)形成一第二氮 化矽層於第二墊氧化層與第一氧化層上；（g)移除部分第 二氮化矽層，以於溝渠邊角與底部暴露第二墊氧化層； (h)於未被第二氮化矽層覆蓋之第二墊氧化層上形成一熱 氧化層；以及（i )移除第二氮化矽層、熱氧化層與第二墊Page 1227540 V. Description of the invention (3) / Therefore, how to develop a method for forming smooth corners in trenches in the process of trench-type metal oxide semiconductor devices or integrated circuit components, to avoid corner stress and The phenomenon of the tip discharge and leakage current of the semiconductor element caused by the uneven thickness of the gate oxide layer or the dielectric layer is an urgent problem to be solved at present. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for forming smooth trench corners in a trench metal oxide semiconductor device or integrated circuit device manufacturing process, thereby avoiding corner stress and gate oxide or dielectric layers. The problem of uneven thickness prevents the semiconductor device from generating tip discharge and leakage current. In order to achieve the above purpose, the present invention provides a method for forming smooth trench corners, which should be used in a trench metal oxide semiconductor device manufacturing process. The method includes at least the following steps: (a) providing a semiconductor substrate; (b) sequentially forming A first hafnium oxide layer, a first nitride cutting layer and a first oxide layer on a semiconductor substrate; (c) partially removing the first oxide layer, the first silicon nitride layer, the first pad oxide layer and A semiconductor substrate to form at least one trench; (d) removing portions of the first oxide layer, the first silicon nitride layer, and the first pad oxide damage layer adjacent to the trench; (e) forming a second pad oxide layer in the trench (F) forming a second silicon nitride layer on the second pad oxide layer and the first oxide layer; (g) removing a portion of the second silicon nitride layer to expose the second pad oxide at the corners and the bottom of the trench (H) forming a thermal oxide layer on the second pad oxide layer not covered by the second silicon nitride layer; and (i) removing the second silicon nitride layer, the thermal oxide layer and the second pad
第9頁 1227540 五、發明說明（4) 氧化層。 根據本案之構想，其中步驟（c)係由微影與蝕刻方法 完成。 根據本案之構想，其中溝渠之深度為1〇至3. 0· 2至 1· 0// m。 根據本案之構想 根據本案之構想 形成 其中步驟（d )係藉由氫氟酸完成。 其中第二氮化矽層係藉由沉積方式 成 成 根據本案之構想 根據本案之構想 其中步驟（g )係由乾蝕刻方式完 其中步驟（h )係藉由熱氧化法完 ΪΪ本案之構想，其中步驟⑴係藉由磷酸完成。 妙牙:夕=述目的，本案另提供一種溝渠式金屬氧化半導 本莫造方法，該方法至少包含下列步驟：（a)提供一 矽声盥土〗，父)依序形成一第-墊氧化層、-第-氮化 石^層^一第一氣化層於半導體基板上；（c)部份移除第一 =&= i第一氮化矽層、第一墊氧化層與半導體基板，以 H f ^ 一溝渠；（d)移除鄰近溝渠之部分第一氧化層、 i ^ ΐ石夕層與第一塾氧化層；⑷形成一第二塾氧化層 [:木 ’（f)形成一第二氮化矽層於第二墊氧化層與第 t化層上；（g)移除部分第二氮化矽層，以於溝渠邊角 1卩暴?第二墊氧化層；（h)於未被第二氮化矽層覆蓋 之一塾氧化層上形成一熱氧化層；（i)移除第二氮化矽Page 9 1227540 V. Description of the invention (4) Oxidation layer. According to the idea of this case, step (c) is performed by lithography and etching methods. According to the idea of the present case, the depth of the ditch is 10 to 3.0 · 2 to 1 · 0 // m. According to the idea of the present case, the step (d) is completed by hydrofluoric acid. The second silicon nitride layer is formed by a deposition method according to the concept of the present case. The step (g) is completed by a dry etching method. The step (h) is completed by a thermal oxidation method. Step VII is performed by phosphoric acid. Wonderful teeth: For the purpose stated, this case also provides a trench-type metal oxide semiconducting fabrication method. The method includes at least the following steps: (a) providing a silicon-acoustic toilet, father) forming a first pad in sequence. An oxide layer, a -th nitride layer, a first vaporized layer on a semiconductor substrate; (c) partially removing the first silicon oxide layer, the first pad oxide layer, and the semiconductor A substrate with H f ^ a trench; (d) removing part of the first oxide layer, i vermiculite layer and the first hafnium oxide layer adjacent to the trench; a second hafnium oxide layer [: 木 '(f ) Forming a second silicon nitride layer on the second pad oxide layer and the t-th layer; (g) removing a portion of the second silicon nitride layer to expose the second pad oxide layer at a corner of the trench 1; (H) forming a thermal oxide layer on a hafnium oxide layer not covered by the second silicon nitride layer; (i) removing the second silicon nitride layer
第10頁 1227540 五、發明說明（5) 層、熱氧化層與第二墊氧化層；以及（j )形成一第二氧化 層於該溝渠中與該第一氧化層上。 本案得藉由下列圖示與實施例說明，俾得一更清楚之 了解。 圖示簡單說明 第一圖（a)〜（b):其係為傳統製造溝渠式金氧半場效電晶 體的部分流程示意圖。 第二圖（a):其係顯示傳統製程所形成之溝渠於其頂部之掃 描式電子顯微鏡圖。 第二圖（b):其係顯示傳統製程所形成之溝渠於其底部之掃 描式電子顯微鏡圖。 第三圖（a)〜（g):其係為本案較佳實施例之流程示意圖。 第四圖（a):其係顯示本案製程所形成之溝渠於其頂部之掃 描式電子顯微鏡圖。 第四圖（b):其係顯示本案製程所形成之溝渠於其底部之掃 描式電子顯微鏡圖。 圖示符號說明 10 :半導體基板 1 2 :氮化石夕層 14:溝渠 2 0 :半導體基板 2 2 :第一氮化矽層 11 :墊氧化層 13 :氧化層 1 5 :閘極氧化層/介電層 2 1 :第一墊氧化層 2 3 :第一氧化層Page 10 1227540 V. Description of the invention (5) layer, thermal oxide layer and second pad oxide layer; and (j) forming a second oxide layer in the trench and on the first oxide layer. This case can be understood more clearly by the following illustrations and examples. The diagram is briefly explained. The first diagrams (a) to (b) are schematic diagrams of part of a conventional process for manufacturing a trench-type metal-oxide-semiconductor field-effect transistor. The second figure (a): it is a scanning electron microscope image showing a trench formed on the top by a traditional process. The second picture (b): it is a scanning electron microscope image showing the trench formed by the traditional process at the bottom. The third diagrams (a) to (g) are schematic diagrams of the processes of the preferred embodiment of the present invention. The fourth figure (a): it is a scanning electron microscope image showing the trench formed on the top of the trench formed by the process of this case. The fourth figure (b): it is a scanning electron microscope image showing the trench formed by the process of the present case at the bottom. Description of reference symbols 10: semiconductor substrate 1 2: nitride nitride layer 14: trench 2 0: semiconductor substrate 2 2: first silicon nitride layer 11: pad oxide layer 13: oxide layer 1 5: gate oxide layer / intermediate Electrical layer 2 1: first pad oxide layer 2 3: first oxide layer
第11頁 1227540 五、發明說明（6) 24:溝渠 25:第二墊氧化層 26·第二氮化矽層 27:熱氧化層 2 8 :閘極氧化層/介電層 實施方式Page 11 1227540 V. Description of the invention (6) 24: trench 25: second pad oxide layer 26 · second silicon nitride layer 27: thermal oxide layer 2 8: gate oxide layer / dielectric layer
本案方法主要係應用於溝渠式金屬氧化半導體元件或 積體電路元件的製程中，用以形成具圓滑邊角之溝渠，俾 以防止邊角應力與閘極氧化層或介電層厚度不均勻的現 象’，而避免尖端放電與漏電流的情形產生，以及溝渠式 ，屬氧 半導體元件或積體電路元件電性的改變。以^實 施例雖以溝渠式金氧半場效電晶體的製程為例，然而，其 他種1之溝渠式功率半導體元件在此皆可併入參考。The method in this case is mainly used in the process of manufacturing trench-type metal oxide semiconductor devices or integrated circuit components to form trenches with smooth corners to prevent corner stress and uneven thickness of the gate oxide or dielectric layer. Phenomenon ', to avoid the occurrence of tip discharge and leakage current, and the trench type, electrical changes of oxygen semiconductor devices or integrated circuit components. Taking the embodiment as an example, although the manufacturing process of a trench-type metal-oxide-semiconductor field-effect transistor is taken as an example, other types of trench-type power semiconductor devices can be incorporated herein by reference.
f參閱第三圖（a )至第三圖（g)，其係為本案較佳實施 你I之机程示意圖。如第三圖（a)所示，於製造溝渠式金氧 半場效電晶體時，首先提供一半導體基板20，其中半導體 基板j 0可為秒基板。然後，於半導體基板2 〇上依序形成第 一墊氧化層2卜第一氮化矽層22以及第一氧化層23。其 中，第一墊氧化層2 1係具有緩衝的作用，可減低半導體基 板2 0與第一氮化石夕層2 2之間的應力作用，而第一氧化層2〔 較佳為氧化石夕層。接著，以微影與蝕刻的方式移除部分第 一氧化層23、第一氮化矽層22、第一墊氧化層21以及半導 體基板2 0，以形成至少一溝渠2 4，其中溝渠2 4的深度最佳 為1 · 0至3.0// m’而寬度最佳為〇·2至i.o# m。 接下來’如第三圖（b)所示，以氫氟酸（HF)移除鄰近f Refer to the third diagram (a) to the third diagram (g), which are schematic diagrams of the procedures for the better implementation of this case. As shown in the third figure (a), when manufacturing a trench-type metal-oxide-semiconductor field-effect transistor, a semiconductor substrate 20 is first provided, and the semiconductor substrate j 0 may be a second substrate. Then, a first pad oxide layer 21, a first silicon nitride layer 22, and a first oxide layer 23 are sequentially formed on the semiconductor substrate 20. Among them, the first pad oxide layer 21 has a buffering effect, which can reduce the stress between the semiconductor substrate 20 and the first nitride layer 22, and the first oxide layer 2 [preferably an oxide layer . Then, a part of the first oxide layer 23, the first silicon nitride layer 22, the first pad oxide layer 21, and the semiconductor substrate 20 are removed by lithography and etching to form at least one trench 24, wherein the trench 2 4 The depth is preferably 1.0 to 3.0 m / m 'and the width is preferably 0.2 to io # m. Next ’, as shown in the third picture (b), remove the neighbor with hydrofluoric acid (HF)
第12頁 1227540 五、發明說明（7) 溝渠2 4處之部分第一氧化層23、第一氮化石夕2 2與第一塾氧 化層2 1。隨後，如第三圖（c )所示，於溝渠2 4中形成第二 墊氧化層25’且沉積第二氮化带層2 6於第二塾氧化層2 5上 並延伸覆蓋第一氧化層23。其中，第二墊氧化層25之厚度 以約3 0 0 - 4 0 01%佳，且第二氮化矽層2 6之厚度以約2 () 0 A 為佳。 然後，如第三圖（d)所示，以乾蝕刻（dry etch)方式 將水平方向（X方向）之第二氮化矽層2 6移除。此時垂直方 向（Y方向）之第二氮化碎層2 6會保留，使得溝渠2 4頂邊角 與底面之第二墊氧化層25以及第一氧化層23暴露出來。之 後，如第三圖（e)所示，以熱氧化法於溝渠24頂邊角與底 面未被第二氮化矽層2 6所覆蓋的地方形成一熱氧化層2 7， 此時第一氧化層2 3上方亦會形成一層薄的熱氧化層2 7。接 著，如第三圖（f )所示，以磷酸將第二氮化矽層2 6、熱氧 化層2 7與第二墊氧化層2 5移除，以形成具圓滑頂邊角與底 邊角之溝渠24。最後，如第三圖（g)所示，形成一第二氧 化層於溝渠24中與第一氧化層23上，以作為閘極氧化層或 介電層28。 隨後，進行後續製程，例如於溝渠2 4底部形成底閘氧 化層、沉積多晶矽於溝渠2 4中且/或移除第一氧化層2 3、 第一氮化矽層22與第一墊氧化層21等製程，以完成溝渠式 金氧半場效電晶體之製作。 請參閱第四圖（a)與第四圖（b)’其係分別為本案製程 步驟所形成之溝渠於頂邊角與底邊角之掃描式電子顯微鏡Page 12 1227540 V. Description of the invention (7) Part of the trench 2 The first oxide layer 23, the first nitride layer 22 and the first hafnium oxide layer 21. Subsequently, as shown in the third figure (c), a second pad oxide layer 25 'is formed in the trench 24 and a second nitrided strip layer 26 is deposited on the second hafnium oxide layer 25 and extends to cover the first oxide. Layer 23. Among them, the thickness of the second pad oxide layer 25 is preferably about 3 0-4 0 01%, and the thickness of the second silicon nitride layer 26 is preferably about 2 () 0 A. Then, as shown in the third figure (d), the second silicon nitride layer 26 in the horizontal direction (X direction) is removed by dry etch. At this time, the second nitride layer 26 in the vertical direction (Y direction) will remain, so that the second pad oxide layer 25 and the first oxide layer 23 of the top corner of the trench 24 and the bottom surface are exposed. After that, as shown in the third figure (e), a thermal oxidation layer 27 is formed on the top corners and the bottom surface of the trench 24 by the thermal oxidation method that is not covered by the second silicon nitride layer 26. At this time, the first A thin thermal oxide layer 27 is also formed on the oxide layer 23. Next, as shown in the third figure (f), the second silicon nitride layer 26, the thermal oxide layer 27, and the second pad oxide layer 25 are removed with phosphoric acid to form smooth top corners and bottom edges.角 之 沟沟 24. Finally, as shown in the third figure (g), a second oxide layer is formed in the trench 24 and the first oxide layer 23 as a gate oxide layer or a dielectric layer 28. Subsequently, subsequent processes are performed, such as forming a bottom gate oxide layer at the bottom of the trench 24, depositing polycrystalline silicon in the trench 24, and / or removing the first oxide layer 2 3, the first silicon nitride layer 22, and the first pad oxide layer. 21 and other processes to complete the production of trench-type metal-oxide half-field-effect transistor. Please refer to the fourth figure (a) and the fourth figure (b) ’, which are scanning electron microscopes of the top and bottom corners of the trenches formed by the process steps of this case, respectively.
第13頁 1227540 五、發明說明（8) ------— 圖。由第四圖（a)可知，溝渠24頂邊角經過上述圓滑化牛 驟後已明顯地以近似於圓弧的輪廓呈現，因此頂邊角附^ 的晶格便不易擠壓，溝渠24不再有邊角應力（c〇rner stress)作用，如此溝渠式金屬氧化半導體元件於操作 就不會產生大端放電的現象。另外，由第四圖（b)亦可清 楚地了解，溝渠24底邊角經上述圓滑化步驟後亦已明顯地 以近似於圓弧的輪廓呈現，因此於形成閘極氧化層或介 層28時，將使閘極氧化層或介電層28之厚度更趨於一致， 如此將可避免溝渠式金屬氧化半導體元件於操作時產生 重的漏電流之現象。 綜上所述，本案係一種形成圓滑溝渠邊角之方法，其 可應，於溝渠式金屬氧化半導體元件或積體電路元件製程 中。藉由本案之方法，不止可以避免溝渠邊角應力 (corner stress)與閘極氧化層厚度不均的問題，且可進 一步避免尖端放電與漏電流現象產生。本案極具產業之價 值，爰依法提出申請。 本案得藉由熟悉此技藝之人士任施匠思而為諸般修 飾’然皆不脫如附申請範圍所欲保護者。Page 13 1227540 V. Description of the invention (8) -------- Figure. It can be seen from the fourth figure (a) that the top corners of the ditch 24 have been apparently shown in a contour similar to an arc after the smoothing step, so the lattice attached to the top corners is not easy to squeeze, and the ditch 24 is not easy to squeeze. In addition, there is a corner stress effect, so that the trench-type metal oxide semiconductor device does not generate a large-end discharge phenomenon during operation. In addition, it can also be clearly understood from the fourth figure (b) that the bottom corners of the trench 24 have been apparently shown in a contour similar to an arc after the above-mentioned rounding step. As a result, the thickness of the gate oxide layer or the dielectric layer 28 tends to be more uniform, so that the phenomenon of heavy leakage current during the operation of the trench metal oxide semiconductor device can be avoided. To sum up, this case is a method for forming smooth trench corners, which can be applied in the process of manufacturing trench metal oxide semiconductor devices or integrated circuit components. By the method in this case, not only can the corner stress of the trench and the uneven thickness of the gate oxide layer be avoided, but also the phenomenon of tip discharge and leakage current can be further avoided. The case is of great industrial value, and the application was filed according to law. In this case, people who are familiar with this skill can use Ren Shijiangsi to make all kinds of modifications, but none of them can be protected as attached to the scope of application.
1227540 圖式簡單說明 第一圖（a)〜（b):其係為傳統製造溝渠式金氧半場效電晶 體的部分流程示意圖。 第二圖（a):其係顯示傳統製程所形成之溝渠於其頂部之掃 描式電子顯微鏡圖。 第二圖（b):其係顯示傳統製程所形成之溝渠於其底部之掃 描式電子顯微鏡圖。 第三圖（a)〜（g):其係為本案較佳實施例之流程示意圖。 第四圖（a):其係顯示本案製程所形成之溝渠於其頂部之掃 描式電子顯微鏡圖。 第四圖（b):其係顯示本案製程所形成之溝渠於其底部之掃 描式電子顯微鏡圖。1227540 Schematic description of the first diagram (a) ~ (b): It is a schematic diagram of part of the traditional manufacturing trench-type metal-oxide half-field effect crystal. The second figure (a): it is a scanning electron microscope image showing a trench formed on the top by a traditional process. The second picture (b): it is a scanning electron microscope image showing the trench formed by the traditional process at the bottom. The third diagrams (a) to (g) are schematic diagrams of the processes of the preferred embodiment of the present invention. The fourth figure (a): it is a scanning electron microscope image showing the trench formed on the top of the trench formed by the process of this case. The fourth figure (b): it is a scanning electron microscope image showing the trench formed by the process of the present case at the bottom.
第15頁Page 15
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