CN108140559A - 传导阻障直接混合型接合 - Google Patents

传导阻障直接混合型接合 Download PDF

Info

Publication number
CN108140559A
CN108140559A CN201680048737.8A CN201680048737A CN108140559A CN 108140559 A CN108140559 A CN 108140559A CN 201680048737 A CN201680048737 A CN 201680048737A CN 108140559 A CN108140559 A CN 108140559A
Authority
CN
China
Prior art keywords
barrier material
conduction barrier
original
layer
metal contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201680048737.8A
Other languages
English (en)
Other versions
CN108140559B (zh
Inventor
保罗·M·恩奎斯特
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Edya Semiconductor Bonding Technology Co ltd
Original Assignee
Anglo Sai Bond Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anglo Sai Bond Technology Co Ltd filed Critical Anglo Sai Bond Technology Co Ltd
Priority to CN202210544308.7A priority Critical patent/CN114944376A/zh
Publication of CN108140559A publication Critical patent/CN108140559A/zh
Application granted granted Critical
Publication of CN108140559B publication Critical patent/CN108140559B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/89—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/03452—Chemical vapour deposition [CVD], e.g. laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H01L2224/03616—Chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/0382—Applying permanent coating, e.g. in-situ coating
    • H01L2224/03825—Plating, e.g. electroplating, electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05007—Structure comprising a core and a coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/05078—Plural internal layers being disposed next to each other, e.g. side-to-side arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05547—Structure comprising a core and a coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05561—On the entire surface of the internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05562—On the entire exposed surface of the internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05657—Cobalt [Co] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05676—Ruthenium [Ru] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05681—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/05686—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/08112—Disposition the bonding area being at least partially embedded in the surface of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08121—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the connected bonding areas being not aligned with respect to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08123—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting directly to at least two bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08137—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/08147—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a bonding area disposed in a recess of the surface of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/29286—Material of the matrix with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/29287—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/3001—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/3005—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/305—Material
    • H01L2224/30505—Layer connectors having different materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009—Pre-treatment of the bonding area
    • H01L2224/8001—Cleaning the bonding area, e.g. oxide removal step, desmearing
    • H01L2224/80011—Chemical cleaning, e.g. etching, flux
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009—Pre-treatment of the bonding area
    • H01L2224/8003—Reshaping the bonding area in the bonding apparatus, e.g. flattening the bonding area
    • H01L2224/80031—Reshaping the bonding area in the bonding apparatus, e.g. flattening the bonding area by chemical means, e.g. etching, anodisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009—Pre-treatment of the bonding area
    • H01L2224/8003—Reshaping the bonding area in the bonding apparatus, e.g. flattening the bonding area
    • H01L2224/80035—Reshaping the bonding area in the bonding apparatus, e.g. flattening the bonding area by heating means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009—Pre-treatment of the bonding area
    • H01L2224/8003—Reshaping the bonding area in the bonding apparatus, e.g. flattening the bonding area
    • H01L2224/80047—Reshaping the bonding area in the bonding apparatus, e.g. flattening the bonding area by mechanical means, e.g. severing, pressing, stamping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80053—Bonding environment
    • H01L2224/80054—Composition of the atmosphere
    • H01L2224/80075—Composition of the atmosphere being inert
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80053—Bonding environment
    • H01L2224/80095—Temperature settings
    • H01L2224/80096—Transient conditions
    • H01L2224/80097—Heating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80053—Bonding environment
    • H01L2224/80095—Temperature settings
    • H01L2224/80099—Ambient temperature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8019—Arrangement of the bonding areas prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8019—Arrangement of the bonding areas prior to mounting
    • H01L2224/80194—Lateral distribution of the bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80909—Post-treatment of the bonding area
    • H01L2224/8093—Reshaping
    • H01L2224/80935—Reshaping by heating means, e.g. reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/8303—Reshaping the layer connector in the bonding apparatus, e.g. flattening the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Wire Bonding (AREA)

Abstract

本发明提供一种形成直接混合型接合的方法和源自直接混合型接合的装置，其包括：第一基板，其具有第一组金属接合衬垫(其较佳而言连接到装置或电路，而由传导阻障所覆盖)，并且具有第一非金属区域(其相邻于第一基板上的金属接合衬垫)；第二基板，其具有第二组金属接合衬垫(其由第二传导阻障所覆盖、对齐于第一组金属接合衬垫、较佳而言连接到装置或电路)，并且具有第二非金属区域(其相邻于第二基板上的金属接合衬垫)；以及接触接合接口，其在第一和第二组金属接合衬垫之间、由传导阻障所覆盖、而通过第一非金属区域对第二非金属区域的接触接合所形成。

Description

传导阻障直接混合型接合
相关申请案/作为参考并入于此的申请案的相交参考
本专利申请案相关于美国专利申请案第09/505,253、10/359,608以及11/201,321号，其在此通过引用方式整体并入。
技术领域
本发明关于直接接合的领域，更特定而言关于混合型直接接合(较佳而言在室温或低温)；更特别而言关于半导体材料、装置或电路的接合，而要用于堆栈半导体装置和集成电路制作；甚至更特别而言关于制作消费者和商业产品中的附加价值零件，包括移动电话中的影像传感器、移动电话中的射频(RF)前端、高效能图形产品中的三维(threedimensional，3D)内存、服务器中的3D内存。
背景技术
对于以较小形式因素、较低成本来增加功能性的持续要求而言，晶粒、芯片或晶圆堆栈已经变成工业标准实务。一般而言，堆栈可以随着堆栈诸层之间的电互连来做，而形成作为堆栈过程的一部分或在堆栈过程之后。在堆栈过程之后所形成的电互连的范例使用贯穿硅通孔(through silicon via，TSV)蚀刻，并且填充穿过堆栈中的一层而到堆栈中的相邻层里，以在堆栈的诸层之间做出电互连。形成作为堆栈过程的一部分的这些三维(3D)电互连的范例包括焊料凸块和铜柱(其具有或没有底填)、混合型接合、直接混合型接合。将3D电互连实现成堆栈过程的一部分则就许多原因来说是有利的，包括但不限于免除TSV(贯穿硅通孔)科技的成本和专属需求。直接混合型接合也称为直接接合互连(direct bondinginterconnect，)，则就许多原因来说要比其他形式的堆栈来得有利，包括但不限于在金属和介电表面构件上方有平坦的接合(其在低温下提供高强度)以及能够做到尺度达次微米的3D互连间距。
用于直接混合型接合的金属和介电表面构件可以由金属和介电质的各式各样组合所组成，其以各式各样的制作技术而形成各式各样的图案。金属的非限制性范例包括铜、镍、钨、铝。举例而言见：P.Enquist的「用于三维集成电路应用的高密度直接接合互连(DBITM)科技」，材料研究协会研讨会议事录，第970册，2007年，第13～24页；P.Gueguen等人的「铜直接接合做的3D垂直互连」，材料研究协会研讨会议事录，第1112册，2009年，第81页；P.Enquist的「直接接合互连作为三维整合架构和应用的大量商业化的驱动器所拥有的缩放性和低成本优点」，材料研究协会研讨会议事录，第1112册，2009年，第81页；DiCioccio等人的「归功于钨直接接合的垂直金属互连」，第60届ECTC的2010年议事录，第1359～1363页；H.Lin等人的「使用低温晶圆接合的直接Al–Al接触来整合MEMS和CMOS装置」，微电子工程，第85期(2008年)，第1059～1061页。介电质的非限制性范例包括氧化硅、氮化硅、氧氮化硅、氮化硅碳。举例而言见：P.Enquist的「3D科技平台——先进的直接接合科技」，C.S.Tan、K.N.Chen、S.J.Koester(编辑者)，「用于VLSI***的3D整合」，Pan Stanford，ISBN978-981-4303-81-1，2011年；J.A.Ruan、S.K.Ajmera、C.Jin、A.J.Reddy、T.S.Kim的「在蚀刻停止层和介电层之间具有改善附着和减少起泡的半导体装置」，美国专利第7732324B2号。各式各样图案的非限制性范例包括通孔数组或金属线和空间的数组，举例而言如在互补式金属氧化物半导体(CMOS)生产线后端(back-end-of-line，BEOL)互连制作中的通孔和接线层所发现的。以这些范例来说，3D电互连可以通过金属通孔对金属通孔、金属通孔对金属线、或金属线对金属线的对齐和接合而形成。建造适合混合型接合的表面的制作技术的非限制性范例是工业标准的单一和双重镶嵌过程，其若有需要的话则加以调整以满足适合的拓扑规格。
基本上有二种CMOS BEOL制程。一种典型而言称为铝(Al)BEOL，另一种称为铜(Cu)BEOL。于Al BEOL过程，具有适合的传导阻障层的Al典型而言使用作为接线层，并且具有适合的传导阻障层的钨(W)则用于通孔层以在二相邻Al接线层之间做电互连。Al接线层典型而言被干式蚀刻，后续以介电质沉积来平坦化，接着再做化学机械抛光(chemo-mechanicalpolishing，CMP)。W通孔层典型而言是以单一镶嵌过程所形成，其由以下所组成：介电质沉积、通孔图案化和蚀刻到先前的接线层、通过物理气相沉积和W化学气相沉积而以传导阻障层来填充通孔、并且做W和传导阻障层的CMP以隔离介电基质里的W通孔或栓塞。于Cu BEOL过程，具有适合的传导阻障层的Cu典型而言使用作为接线和通孔层。Cu接线和通孔层典型而言是以双重镶嵌过程所形成，其由以下所组成：介电质沉积、通孔图案化和蚀刻部分穿过介电层、接着做接线图案化(其重迭着通孔图案化)并且同时继续蚀刻(多个)通孔到先前的接线层，其中接线重迭着部分蚀刻的通孔，并且蚀刻出用于接线的沟槽，其连接到先前具有通孔的接线层。替代性的双重镶嵌过程是由以下所组成：介电质沉积、接线图案化和蚀刻部分穿过介电层(其在到达先前的接线层则停止)、通孔图案化和蚀刻到先前的接线层，其中通孔是在部分蚀刻的接线里，并且蚀刻完成了通孔蚀刻到先前的接线层。任一双重蚀刻表面然后填充了传导阻障层(举例而言通过物理气相沉积来为之)，接着再做Cu填充(举例而言通过电镀或物理气相沉积加电镀来为之)，最后做Cu和传导阻障层的CMP以隔离介电基质里的Cu接线。
使用上述工业标准的W或Cu镶嵌流程则可以用来形成用于混合型接合的表面，而接受适合的表面拓扑，举例而言如上所提供。然而，当这些表面用于混合型接合时，典型而言在一表面上的金属和在另一表面上的介电质之间将有异质接合构件，举例而言这是由于通孔表面未对齐的缘故。这可以导致来自一接合表面的通孔填充材料直接接触来自另一接合表面的介电质，而没有***传导阻障(其在Cu或W填充通孔和包围介电质之间的其他地方)。
较佳的是具有用于直接混合型接合过程科技的低热预算的宽制程窗口，而斟酌影响目前合格于CMOS BEOL半导体厂的材料和过程，以降低使直接混合型接合过程合格于该半导体厂的实行障碍。Cu BEOL过程是此种较佳能力的范例，因为Cu镶嵌过程已经是多年的工业标准，并且Cu直接混合型接合科技能够斟酌影响这基础架构。斟酌影响Al BEOL工业标准过程已经是比较具挑战性的，因为此过程中的二种主要金属W和Al由于包括高降伏强度、热膨胀系数(coefficient of thermal expansion，CTE)、原生氧化物、小丘形成等因素的组合而对于发展W或Al的直接混合型接合科技来说是比较具挑战性的材料。
发明内容
本发明的具体态样针对形成直接混合型接合表面的方法，其包括：在第一基板的上表面中形成多个第一金属接触结构，其中所述结构的顶面是在该上表面之下；在该上表面和所述多个金属接触结构上方形成传导阻障材料做的第一层；以及从该上表面移除传导阻障材料做的该第一层。
附图说明
当关于伴随图示来考虑而参考以下详细叙述时，由于更加了解则将轻易获得对本发明的更完整体会和其达成的许多优点，其中：
图1是单一或双重镶嵌过程所形成的传导层的靠近表面区域的示意截面图，其具有填充的通孔和/或接线，而在填充的通孔和/或接线与包围介电质之间则有传导阻障；
图2是图1在从包围介电质的表面移除传导层之后的示意截面图；
图3是图2在形成传导阻障材料层之后的示意截面图；
图4是图3在从包围介电质的表面移除传导阻障层材料层之后的示意截面图；
图5是二个混合型直接接合表面正在接合的示意图；
图6是二个混合型直接接合表面在接触个别的介电层之后的示意图；
图7是二个混合型直接接合表面已直接接合的示意图；
图8是传导阻障材料的上表面因为碟化而弯曲的示意图；
图9是根据本发明的一对基板的示意图，其中类似的通孔结构未对齐于传导阻障，并且通孔对齐于针对具有传导阻障的接线结构的传导阻障；
图10是表面的靠近表面区域的示意截面图，该表面由图案化的金属层所组成，其以包围介电质加以平坦化，而平坦化暴露图案化的金属层，在金属层和包围介电质的侧向之间没有传导阻障层；
图11是图10的示意截面图，其中图案化的金属层的暴露表面的传导部分根据本发明而覆盖了传导阻障金属；
图12是根据本发明的一对接触基板的示意图，其举的例子是在金属层和包围介电质的侧向之间没有传导阻障下将没有对于接线结构的传导阻障的接线结构加以对齐；
图13是本发明的另一具体态样的示意图，其具有贯穿硅通孔结构；
图14是图13的结构的示意图，其具有第二传导阻障材料层；以及
图15是本发明的另一具体态样的示意图，其具有贯穿硅通孔结构而在侧壁上具有介电层。
具体实施方式
现在参见图式，其中全篇相同的参考数字指称相同或对应的零件，并且特别参见图1，其显示在根据本发明的直接混合型接合过程中的基板30的表面的截面，其由导体1、传导阻障2、介电质3、金属结构4所组成。金属结构4形成在介电质3中。金属结构4位于介电质3里，并且可以是接触、衬垫、线或其他金属互连结构。开口形成在金属结构4上方的介电质3中，接着形成传导阻障2和导体1。导体1、传导阻障2、金属结构4的尺寸和厚度并未按照比例，而是为了示范本发明所绘制。虽然开口和金属结构显示成有相同的尺寸和形状，不过它们的尺寸和形状可以有所不同，此视设计或需要而定。
用于导体1的可能是各式各样的金属，包括但不限于Cu和W，其分别常见于Cu和AlBEOL半导体厂。Cu可以通过物理气相沉积(physical vapor deposition，PVD)或电镀(electroplating，EP)而沉积，并且W可以通过化学气相沉积(chemical vapordeposition，CVD)而沉积。用于传导阻障材料2的也可能是各式各样的传导阻障，其常见于Cu和Al BEOL半导体厂。Cu BEOL过程中的传导阻障包括钽(Ta)、氮化钛(TiN)、氮化钽(TaN)、氮化钨(WN)、氧化钌(RuO2)、氮化钽硅(TaSiN)、氮化钛硅(TiSiN)、氮化钨硼(TBN)、硼化钴钨(CoWB)、磷化钴钨或其组合(举例而言为Ti/TiN和Ta/TaN)，其可以通过各式各样的技术来沉积，包括PVD、CVD、金属有机CVD(metal organic CVD，MOCVD)。有各式各样的PVD技术可用，包括直流(DC)磁控溅镀、准直溅镀、离子化金属电浆(ionized metal plasma，IMP)。Al BEOL过程中的传导阻障包括Ti/TiN。其他材料也有可能作为阻障，举例而言为镍(Ni)。
也可能有各式各样的介电质，包括但不限于氧化硅、氮化硅、碳氮化硅，其常见于Cu和Al BEOL半导体厂。生成图1截面所述表面的常见方法是上述的镶嵌过程。
图1的上表面接受CMP以移除介电质3的顶部上的部分的导体1和传导阻障2。图2示范在CMP之后的结构。导体1和传导阻障2相对于介电质3的相对高度可以通过镶嵌过程的CMP部分来控制。
导体1和传导阻障2相对于介电质3的高度则有许多组态。导体1和阻障2的顶面可以在介电质3的表面之下、甚至之中、名义上甚至之中或之上。一般而言，直接混合型接合有可能具有所有的组态。然而，较佳的组态则是导体1和传导阻障2的相对高度是在介电质3之下的距离t1。这组态有助于形成无空洞的接合接口，并且对于跨越接合表面的相对高度变化而言是更可制造的。对于最适合直接混合型接合的表面来说，跨越传导层的接合表面而在介电质3之下的相对高度变化的范例是在介电质3之下一到十奈米，虽然也可能有较小和较大的变化。这凹陷典型而言称为碟化(dishing)。所得表面称为没有传导阻障2的混合型接合表面。
兼容于混合型接合的典型碟化量是0到20奈米，其称为标准碟化。标准碟化的增加量相当于图4所示的后续传导阻障7(其形成在图2所示这增加碟化形成开口5的顶部上)的厚度，所导致的碟化则相当于标准碟化并且兼容于直接混合型接合所要的。标准碟化增加的范例是5～20奈米，导致约5～40奈米的总碟化t1。这标准碟化的增加可以用各式各样的方式来形成，举例而言增加用来生成标准碟化的CMP直到达成所要的增加碟化为止。这CMP的增加可以由CMP时间的增加来完成，该时间量可以由常规的校正所决定，并且可以是CMP衬垫、浆液、向下力、承载器和桌台旋转、混合型表面上的导体和介电质的图案等的函数。
如图3所示，传导阻障金属层6形成在结构上方而在图2所示的介电质表面31上。阻障6的材料可以相同或不同于传导阻障2。增加碟化之后在导体1的顶部上形成阻障6则可以用许多方式来形成，举例而言为镶嵌过程，其包括在整个表面上方沉积传导阻障，接着做CMP以从较高的介电表面移除传导阻障，而不从凹陷里移除层6的显著量或所有的传导阻障材料。阻障的形成也可以用选择性过程来形成，举例而言为无电镀镍。所得结构在导体1和传导阻障2的顶部上的每个开口5中具有传导阻障7。这所得的碟化较佳而言兼容于直接混合型接合所需者，亦即传导阻障7的表面是在介电质3的表面之下小于20奈米，较佳而言为1～10奈米。图4示意所示的所得表面的截面称为具有传导阻障7的混合型接合表面。
层6的厚度可以小于导体1/阻障2的碟化量，如图3所示，或者可以相同或厚于这碟化量。于前者情形，仅从凹陷移除部分的层6或不移除。于层6相同或厚于凹陷量的情形，层6通过CMP而从凹陷里移除。层6在所有情形下被移除，如此则所得的碟化在形成阻障7中小于20奈米，较佳而言1～10奈米。
基板30的每个混合型接合表面可以包含装置和/或集成电路(未显示)，使得这些装置和/或集成电路在完成混合型接合之后可以彼此连接。装置和电路可以包含金属结构4，或者可以经由未示范的进一步的互连结构而连接到金属结构4。
皆具有传导阻障7而有例如图4所示的示意截面的基板30和32的二个混合型接合表面现在可以彼此做直接混合型接合，如图5和6的截面所示，以形成直接混合型接合12。将基板30和32对齐(图5)并且放置成直接接触，使得基板30和32中的介电层3彼此接触(图6)。对齐和接触可以在室温下进行，而在室内气氛或真空下。虽然图式示意显示在基板30和32的阻障7之间有间隙，但是在对齐和接触之后，阻障7之间可以有部分或显著的接触。虽然一对一的连接安排显示于图6，不过可能有其他的安排，例如一基板中的多个金属结构接合于另一基板中的单一金属结构。
基板30和32的介电表面较佳而言如美国专利申请案第09/505,283、10/359,608、11/201,321号所述的制备。简言之，表面可加以蚀刻、抛光、活化和/或终端有所要的接合物种，以促进和提升基板30和32上的介电质3之间的化学接合。制造出粗糙度方均根为0.1到3奈米的介电质3的平滑表面，其经由湿式或干式过程来活化和/或终端化。
随着基板表面在室温接触，基板表面的介电质3开始在一或多个接触点形成接合，并且晶圆之间的吸引接合力随着化学接合面积增加而增加。这接触可以包括阻障7或不包括阻障7。如果接触包括阻障7，则介电质3中的基板对基板化学接合所产生的压力导致有使阻障7的接触区域强烈结合的力，并且基板30和32中的介电质3之间的化学接合在二个不同晶圆上的金属衬垫之间产生电连接。
阻障7抵靠着彼此的内部压力(源自基板30和32的介电质3之间的接合)可能不适合达成较佳而言具有低电阻的电连接，举例而言这是由于原生氧化物或其他污染(举例而言为烃)的缘故。改善的接合或较佳而言为较低电阻的电连接可以通过移除阻障7上的原生氧化物来达成。举例而言，可以使用稀释的氢氟酸来清洁表面；或者在移除原生氧化物之后直到进行接合为止，基板30和32的表面可以暴露于惰性气氛，举例而言为氮或氩。
内部压力也可能不足以使阻障7的足够表面彼此接触。替代或附带而言，阻障7之间的改善接合或较佳而言为较低电阻的电连接可以通过加热来达成。加热的范例包括范围在100～400℃的温度、在10分钟和2小时之间的时间，此视用于接触结构4、阻障6、导体1的材料而定。有可能对于给定的材料组合做时间和温度的优化。举例而言，较短的加热时间可能可以有较高的温度，并且较低的温度可能可以有较长的加热时间。加热时间可以减到最少和/或加热温度可以减到最少的程度则将取决于特定的结构和材料组合，并且可以由常见的制程优化实务来决定。举例而言，如果阻障7是镍，则300℃的温度达二小时或者350℃的温度达15分钟可以是足以改善接合和改善电连接。也可能有较高和较低的温度和/或时间，此视阻障7的材料和阻障7底下的其他材料而定。温度增加可以通过减少原生氧化物或其他污染或者通过增加阻障7之间的内部压力(因为导体1和阻障7的热膨胀)而导致较佳而言为低电阻的电连接。材料4和在材料4之下的其他材料(未示范)也可以增加在阻障7底下的结构热膨胀，并且对应的增加相对阻障7之间的压力。举例而言，如果材料4是具有关联的CTE和杨氏模数的铝，则相较于具有较低CTE和/或杨氏模数的替代性材料4可以产生较高的压力。加热也可以增加阻障7之间的交互扩散以产生较佳的较低电阻电连接。
如果基板30和32的介电质3之间的起初接合不包括阻障7，则可以使用加热以导致阻障7之间的接触，因为阻障7的CTE高于介电质3。加热或温度上升的量则取决于阻障7之间的分离、阻障7和导体1和金属结构4的厚度、CTE、杨氏模数，因为对于给定的温度上升来说，这些参数影响相对阻障7之间的压力。举例而言，相较于20奈米的分离，使阻障7之间的分离减到最小(举例而言小于10奈米)则可以减少加热。举进一步范例来说，阻障7和/或导体1的高度或厚度将增加压力，因为阻障7和导体1的热膨胀将随着厚度而增加。举例而言，阻障7和导体1的典型膨胀增加是与厚度成正比。举进一步范例来说，具有较高杨氏模数的导体1预期要比具有较低杨氏模数的替代性导体1产生更高的压力，因为较高杨氏模数的材料在当产生压力时较不可能降伏。具有较低杨氏模数的阻障7可以不需要像它可以通过在较低压力下降伏而便于形成连接的那么多的加热。当基板30和32的表面起初接触时，如果阻障7不是紧密接触，则在加热之后，导体1和阻障7的热膨胀因此导致有紧密接触的低电阻连接，如图7所示。
虽然导体1/阻障2和阻障7的表面在上面的范例中显示成平坦的，不过该一或二者由于CMP过程的缘故而可以具有某些弯曲。轮廓显示于图8，其中二者都具有弯曲。于图8，显示的基板33具有阻障7和导体1/阻障2，其表面有所变化。阻障7的厚度较佳而言是够厚以容纳导体1的粗糙度的涵盖范围，但不是太厚而使制作变得复杂。典型的厚度范围可以是5～20奈米。阻障在弯曲的中间和边缘的相对厚度可以较厚或较薄，此视在阻障7沉积在导体1之前的接触1表面形成的弯曲和阻障7形成的弯曲而定，举例而言这是因为用来形成接触1的表面的CMP过程和用来形成阻障7的表面的CMP过程有不同的特征的缘故。阻障7的中央凹陷在介电质3的表面之下小于20奈米，较佳而言为1～10奈米。
图9示范具有混合型接合表面的二个基板34和35的上部。具有传导阻障的混合型接合表面可以包括通孔构件8，其连接到底下的联机构件(未显示)；或者包括联机构件9，其连接到底下的通孔构件(未显示)。在接合之后，在个别混合型接合表面之间典型而言有些未对齐于传导阻障。这未对齐可以导致第一混合型接合表面上的传导阻障7接触第二混合型接合表面上的介电表面31，以及导致第一混合型接合表面上的介电表面31接触第二混合型接合表面上的传导阻障7，如图9的10所示。这未对齐也可以导致一混合型接合表面上的传导阻障7接触另一表面上的介电表面31，以及导致来自一表面的传导阻障7的整个表面接触另一混合型接合表面上的传导阻障7的部分表面，如图9的11所示。
尽管有这未对齐，根据本发明，第一或第二混合型接合表面上的介电质3的表面接触另一混合型接合表面上的传导阻障7，并且在第一或第二混合型接合表面上的传导阻障7接触另一混合型接合表面上的传导阻障7或介电质3的表面。尽管未对齐，导体1的顶部上的传导阻障7因此避免导体2和介电质3之间有所接触。举例而言当Cu使用作为导体1而具有CuBEOL所建造的Cu单一或双重镶嵌直接混合型接合表面，本发明的这特色可以改善直接混合型接合的可靠度，举例而言对于考虑如果Cu直接接触介电质3则Cu会扩散到介电质3里的应用来说便是如此。该特色对于某些结构来说也可以便于跨越接合接口而形成电连接，举例而言，当导体1是Al BEOL所建造的W栓塞单一镶嵌直接混合型接合表面，则在相对表面上的导体1之间做出电连接要比在相对表面上的导体1的顶部上的传导阻障7之间做出电连接还更有挑战性。
图2所示的碟化量可以影响使用这些表面而具有凹陷传导部分的后续直接混合型接合的热预算。举例而言，在将直接混合型接合表面起初放置成直接接触之后，介电部分可以呈直接接触，并且所有或某些的凹陷传导部分可以因为凹陷而不直接接触。加热具有凹陷传导部分的这些直接混合型接合表面可以导致凹陷传导部分膨胀，如此则它们在高于直接混合型接合表面被带去接触的温度下，甚至在更高的温度下，被带去直接接触，并且产生显著压力以便于相对凹陷传导部分之间有电连接。这些更高的温度可以便于在相对的凹陷传导部分之间形成电互连并且完成直接混合型接合。将凹陷部分带去直接接触并且产生显著压力以便于相对凹陷传导部分之间有电连接所需的温度则是传导材料、传导材料上的残余或原生氧化物、传导材料的降伏强度、传导材料的碟化或凹陷等的组合。举例而言，较少的碟化可以导致在低温或室温下起初直接接合相对介电表面之后需要较低的热预算来完成混合型接合，这是因为需要较少的导体1和传导阻障7的膨胀以在相对传导阻障7的表面之间形成金属接合。
举例而言，当使用Ni作为传导阻障时，可以通过加热到约350℃而容纳10奈米的凹陷；相较而言，如果使用铜而无覆盖传导阻障，则约200℃便可以是足够的。为了减少热预算，一般来说使用较高CTE(热膨胀系数)的材料而具有较低降伏强度和较少的碟化则是有用的。一般而言，CTE和降伏强度是由选择的阻障所给定，并且碟化是可变的，其可加以变化来达成适合的热预算。热预算也可以受到在导体底下的材料的影响。举例而言，在导体1底下而具有较高CTE(亦即每℃高于15ppm)的导体1(举例而言为金属结构4，如图4所示)要形成混合型接合电连接所具有的热预算可以低于具有较低CTE的导体1和/或金属结构4。每℃高于15ppm的高CTE金属的范例包括Cu和Al，其是常见于Al和Cu BEOL过程中的导体。
于根据本发明的第二具体态样，由介电部分14所包围的传导部分13则包括在基板36中的直接混合型接合表面15，如图10所示。传导部分13的范例是铝，并且介电部分14的范例是层间介电质，其范例为用于Al BEOL的氧化硅和其他介电质，其用于Al BEOL的典型材料的范例。金属部分13可以包括通孔和/或接线图案，其连接到底下的互连层。介电部分14可以是连续邻接的，举例而言如果传导部分仅由通孔所组成的话；或者介电部分14可以不是连续邻接的，举例而言如果传导部分是由接线图案所分开的话。于此具体态样，直接混合型接合表面15较佳而言具有在直接混合型接合规格里的碟化传导部分。这表面可以通过Al金属化、介电质沉积、CMP平坦化的组合而形成，以形成具有图10所示截面的表面。Al金属化可以包括在顶部上的传导阻障，举例而言为Ti。如果有传导阻障并且它通过CMP平坦化而移除，则表面将具有图10所示的截面。如果传导阻障是够厚以致它未被CMP平坦化所整个移除，并且有适合的碟化t2(举例而言为用于混合型接合的混合型接合表面有0～20奈米的传导阻障部分)，则这表面(譬如图11所示)可以适合直接混合型接合，而不必额外的传导阻障沉积和CMP。
图10所述的碟化t2所增加的量则相当于后续传导阻障16(其形成在这增加的碟化的顶部上)的厚度，而导致相当于图10并且兼容于直接混合型接合(图10)所需的碟化。这厚度的增加是在约5～20奈米的范围。这标准碟化的增加可以用各式各样的方式来形成，举例而言增加用来兼容于直接混合型接合所需的CMP的量。在增加碟化的顶部上形成阻障则可以用许多方式来形成，举例而言为镶嵌过程，其包括在整个表面上方沉积传导阻障(类似于图3)，接着做CMP以从较高的介电表面17移除传导阻障，而不从凹陷里移除显著量或所有的传导阻障(图11)。形成的阻障厚度可以相当于、大于或小于增加的碟化厚度，举例而言小于约40奈米。在形成阻障之后，最终的阻障厚度和碟化则可以由CMP来控制。
于此具体态样，这造成的碟化较佳而言兼容于直接混合型接合所需者。所得表面的截面示意显示于图11，其示范基板37并且称为混合型接合表面18，其所具有的传导阻障16不接触底下的传导阻障。阻障的形成也可以用选择性过程来形成，举例而言为无电镀镍。
具有传导阻障16而形成如图11所示的示意截面图的基板38和39的二个混合型接合表面现在可以彼此做直接混合型接合，如图12的截面所示，以形成具有传导阻障16的直接混合型接合而无底下的传导阻障。每个混合型接合表面是基板的表面，并且每个基板可以包含装置和/或集成电路，使得这些装置和/或集成电路在完成混合型接合之后可以彼此连接。具有传导阻障的混合型接合表面可以包括连接到底下联机构件(未显示)的通孔构件或连接到底下通孔构件(未显示)的联机构件19。
在接合之后，在个别混合型接合表面之间典型而言有些未对齐于传导阻障。这未对齐可以导致第一混合型接合表面上的传导阻障16接触基板36中的第二混合型接合表面上的介电表面17，并且导致第一混合型接合表面上的介电表面17接触第二混合型接合表面上的传导阻障16，如图12的20所示。这未对齐也可以导致一混合型接合表面上的传导阻障16接触另一表面上的介电表面17，并且导致来自一表面的传导阻障16的表面接触另一混合型接合表面上的传导阻障16的部分表面，如图12的21所示。
尽管有这未对齐，根据本发明，在第一或第二混合型接合表面上的介电表面17接触另一混合型接合表面上的传导阻障16，并且在第一或第二混合型接合表面上的传导阻障16接触另一混合型接合表面上的传导阻障16或介电表面17。这特色对于某些结构而言可以便于形成跨越接合接口的电连接，举例而言当导体13是Al BEOL所建造的Al接线表面，则在相对表面上的导体13之间做出电连接要比在相对表面上的导体13的顶部上的传导阻障16之间做出电连接还更具挑战性。
图11所示的碟化量可以影响使用这些表面的后续直接混合型接合的热预算。举例而言，在低温或室温下起初直接接合相对的介电表面之后，较少的碟化可以导致需要较低的热预算来完成混合型接合，这是因为需要较少的导体13膨胀来在相对的传导阻障16表面之间形成金属接合。
于根据本发明的第三具体态样，混合型表面包括传导贯穿硅通孔(TSV)结构23和25，如图13～15所示。每张图为了方便释例而显示二种不同的结构，其具有(25)和没有(23)传导阻障材料层26，该层的形成方式类似于上面图1～4。TSV延伸穿过基板40以接触基板41中的金属导体4。TSV 23和25的传导材料可以由像是Cu或W的金属或像是多晶硅的非金属所组成。传导材料可以相邻于绝缘材料24，如图13所示；或者如包括基板42的图14所示，可以具有插置在传导材料和绝缘材料之间的阻障层27。
于另一范例，TSV 23和25可以具有插置在传导材料和半导体基板43之间的绝缘阻障28，如图15所示。TSV可以凹陷成具有增加的碟化，如第一和第二具体态样所述，并且传导阻障26形成在这增加的碟化里，如第一和第二具体态样所述，以形成具有适合直接混合型接合的碟化的混合型接合表面。这些类型的表面可以彼此做直接混合型接合，举例而言如果TSV表面穿过CMOS结构的背部而暴露，则造成所谓背对背的直接混合型接合。也有可能使用这些混合型接合表面中的某一个来形成对于形成在CMOS结构正面上的混合型接合表面的直接混合型接合，举例而言在Cu BEOL或Al BEOL的顶部上，以形成所谓前对背的直接混合型接合。
于本发明，BEOL通孔填充金属可以完全由传导阻障所包封。进一步而言，本发明允许混合型接合制作来利用介电质和传导阻障材料而做直接混合型接合。可以改善用于直接混合型接合过程的过程窗口，而斟酌影响目前合格于CMOS BEOL半导体厂的材料和/或过程。本发明也允许降低制造商要使直接混合型接合科技合格的实行障碍、使用CMOS BEOL所用的绝缘介电质和传导阻障材料的组合来制造直接混合型接合表面、可以提供抑制小丘形成的直接混合型接合表面的方法和结构、可以减少直接混合型接合中的热预算。
本发明的应用包括但不限于经处理的集成电路的垂直整合，而用于3D SOC、微衬垫封装、低成本和高效能的取代覆晶接合，晶圆级封装、热管理、独特装置结构(例如金属基底装置)。应用进一步包括但不限于集成电路(像是背面照明的影像传感器)、RF前端、微机电结构(micro-electrical mechanical structure，MEMS)(包括但不限于皮米投影器(pico-projector)和陀螺仪)、3D堆栈内存(包括但不限于混合型记忆方块)、高带宽内存、DIRAM、2.5D(包括但不限于在插置物上倾斜的FPGA)和当中使用这些电路的产品(包括但不限于移动电话和其他行动装置、膝上型计算机、服务器)。
鉴于以上教导，本发明可能有许多的修改和变化。因此要了解在所附的权利要求里，本发明可以不如在此特定所述的来实施。

Claims (23)

1.(原始)一种形成直接混合型接合表面的方法，其包括：
在第一基板的上表面中形成多个第一金属接触结构，其中所述结构的顶面是在该上表面之下；
在该上表面和所述多个金属接触结构上方形成传导阻障材料做的第一层；以及
从该上表面移除传导阻障材料做的该第一层。
2.(原始)根据权利要求1所述的方法，其包括：
移除传导阻障材料做的该第一层，以在所述多个金属接触结构上留下该传导阻障材料，所述多个金属接触结构上的该传导阻障材料的顶面是在该基板的该上表面之下小于20奈米。
3.(原始)根据权利要求1所述的方法，其包括：
移除传导阻障材料做的该第一层，以在所述多个金属接触结构上留下该传导阻障材料，所述多个金属接触结构上的该传导阻障材料的顶面是在该基板的该上表面之下约1～10奈米的范围。
4.(原始)根据权利要求1所述的方法，其包括：
在该上表面之下约5～40奈米形成该顶面；
移除该传导阻障，以在所述多个金属接触结构上留下该传导阻障材料，所述多个金属接触结构上的该传导阻障材料的顶面是在该上表面之下1～10奈米。
5.(原始)根据权利要求1的所述的方法，其包括：
在所述金属接触结构的底部和侧面上形成传导阻障材料做的第二层。
6.(原始)根据权利要求3的所述的方法，其包括：
形成传导阻障材料做的所述第一和第二层以完全包围所述金属接触结构。
7.(原始)根据权利要求1所述的方法，其包括：
在该基板上的介电层中形成所述金属接触结构。
8.(原始)一种接合基板的方法，其包括：
在第一和第二基板的个别上表面中形成多个第一和第二金属接触结构，其中所述多个第一金属接触结构的第一顶面是在该第一基板的该上表面之下，并且所述多个第二金属接触结构的第二顶面是在该第二基板的该上表面之下；
在所述上表面和所述多个金属接触结构及所述基板上方形成传导阻障材料做的第一层；以及
从所述第一和第二基板的所述上表面移除传导阻障材料做的该第一层，以在所述多个第一和第二金属接触结构上留下该传导阻障材料。
9.(原始)根据权利要求8所述的方法，其包括：
在所述第一和第二基板的所述上表面之下约5～40奈米分别形成所述第一和第二顶面；
移除传导阻障材料做的该第一层，以在所述多个第一和第二金属接触结构上留下该传导阻障材料，所述多个第一和第二金属接触结构上的该传导阻障材料的顶面分别是在所述第一和第二上表面之下1～10奈米。
10.(原始)根据权利要求8所述的方法，其包括：
在所述多个第一和第二金属接触结构的底部和侧面上形成传导阻障材料做的第二层。
11.(原始)根据权利要求10所述的方法，其包括：
形成传导阻障材料做的所述第一和第二层以完全包围所述金属接触结构。
12.(原始)根据权利要求8所述的方法，其包括：
在所述第一和第二基板上的个别介电层中形成所述多个第一和第二金属接触结构。
13.(原始)根据权利要求8所述的方法，其包括：
移除传导阻障材料做的该第一层，使得所述多个金属接触结构上的该传导阻障材料的顶面分别是在所述第一和第二基板的所述上表面之下小于20奈米。
14.(原始)根据权利要求8所述的方法，其包括：
移除传导阻障材料做的该第一层，使得所述多个金属接触结构上的该传导阻障材料的顶面分别是在所述第一和第二基板的所述上表面之下约1～10奈米的范围。
15.(原始)一种结构，其包括：
直接混合型接合表面，其包括：
介电层，
传导接触结构，以及
第一传导阻障材料层，其直接形成在所述传导接触结构的每一个的上表面上，
其中该传导阻障层的上表面凹陷在该介电层的上表面下方约一到十奈米。
16.(原始)根据权利要求15所述的结构，其包括：
所述传导接触结构的顶面是在该上表面之下约5～40奈米。
17.(原始)根据权利要求15所述的结构，其包括：
传导阻障材料做的第二层，其在所述金属接触结构的底部和侧面上。
18.(原始)根据权利要求15所述的结构，其中：
传导阻障材料做的所述第一和第二层完全包围所述传导接触结构。
19.(原始)一种接合结构，其包括：
第一和第二直接混合型接合表面，每一个包括：
介电层，
传导接触结构，以及
第一传导阻障材料层，其直接形成在所述传导接触结构的每一个的上表面上，
其中所述传导接触结构的上表面凹陷在该介电层的上表面下方约5到40奈米，以及
所述第一和第二直接混合型接合表面中的所述介电层彼此直接接触并且彼此直接接合，并且所述第一和第二直接混合型接合表面中的所述传导阻障材料层彼此直接接触。
20.(原始)根据权利要求19所述的结构，其包括：
第二传导阻障材料层，其配置在所述传导接触结构的底部和侧面上。
21.(原始)根据权利要求20所述的结构，其中：
所述第一和第二传导阻障材料层完全包围所述传导接触结构。
22.(原始)根据权利要求19所述的结构，其中：
所述传导阻障材料层的上表面凹陷在该介电层的该上表面之下小于20奈米。
23.(原始)根据权利要求19所述的结构，其中：
所述传导阻障材料层的上表面凹陷在该介电层的该上表面之下约1～10奈米的范围。
CN201680048737.8A 2015-08-25 2016-08-25 传导阻障直接混合型接合 Active CN108140559B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210544308.7A CN114944376A (zh) 2015-08-25 2016-08-25 传导阻障直接混合型接合

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/835,379 US9953941B2 (en) 2015-08-25 2015-08-25 Conductive barrier direct hybrid bonding
US14/835,379 2015-08-25
PCT/US2016/048609 WO2017035321A1 (en) 2015-08-25 2016-08-25 Conductive barrier direct hybrid bonding

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN202210544308.7A Division CN114944376A (zh) 2015-08-25 2016-08-25 传导阻障直接混合型接合

Publications (2)

Publication Number Publication Date
CN108140559A true CN108140559A (zh) 2018-06-08
CN108140559B CN108140559B (zh) 2022-05-24

Family

ID=58100993

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201680048737.8A Active CN108140559B (zh) 2015-08-25 2016-08-25 传导阻障直接混合型接合
CN202210544308.7A Pending CN114944376A (zh) 2015-08-25 2016-08-25 传导阻障直接混合型接合

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN202210544308.7A Pending CN114944376A (zh) 2015-08-25 2016-08-25 传导阻障直接混合型接合

Country Status (7)

Country Link
US (5) US9953941B2 (zh)
EP (1) EP3341956A4 (zh)
JP (1) JP6743149B2 (zh)
KR (2) KR102659849B1 (zh)
CN (2) CN108140559B (zh)
TW (1) TWI702659B (zh)
WO (1) WO2017035321A1 (zh)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108447839A (zh) * 2017-02-16 2018-08-24 南亚科技股份有限公司 半导体装置及其制造方法
CN110945650A (zh) * 2019-11-05 2020-03-31 长江存储科技有限责任公司 具有通过键合而形成的毗连通孔结构的半导体设备和用于形成其的方法
CN112106176A (zh) * 2018-12-04 2020-12-18 索尼半导体解决方案公司 半导体装置和电子设备
CN112534574A (zh) * 2018-06-13 2021-03-19 伊文萨思粘合技术公司 Tsv之上的大金属焊盘
CN112585740A (zh) * 2018-06-13 2021-03-30 伊文萨思粘合技术公司 作为焊盘的tsv
CN112771656A (zh) * 2018-08-29 2021-05-07 伊文萨思粘合技术公司 通过在直接键合工艺期间捕获污染物并阻止裂纹来增强微电子结构中的键合
CN111933533B (zh) * 2020-08-17 2021-06-04 长江存储科技有限责任公司 半导体封装结构及其制造方法
CN112956011A (zh) * 2018-08-31 2021-06-11 伊文萨思粘合技术公司 微电子学中在低温下进行直接金属间键合的层结构
CN113035729A (zh) * 2021-03-10 2021-06-25 联合微电子中心有限责任公司 混合键合方法及键合用衬底
CN113169159A (zh) * 2018-12-06 2021-07-23 伊文萨思公司 用于微电子器件的直接接合的界面中的电容性耦合
CN113348555A (zh) * 2019-03-18 2021-09-03 铠侠股份有限公司 半导体装置及其制造方法
WO2022000385A1 (zh) * 2020-07-01 2022-01-06 重庆康佳光电技术研究院有限公司 显示面板的制作方法、显示面板及显示装置
WO2023272903A1 (zh) * 2021-07-01 2023-01-05 长鑫存储技术有限公司 一种半导体结构及其形成方法

Families Citing this family (149)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6984571B1 (en) 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6902987B1 (en) 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
US6962835B2 (en) 2003-02-07 2005-11-08 Ziptronix, Inc. Method for room temperature metal direct bonding
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
US7485968B2 (en) 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
EP2372755B1 (de) * 2010-03-31 2013-03-20 EV Group E. Thallner GmbH Verfahren zum permanenten Verbinden zweier Metalloberflächen
US8735219B2 (en) 2012-08-30 2014-05-27 Ziptronix, Inc. Heterogeneous annealing method and device
FR3011679B1 (fr) * 2013-10-03 2017-01-27 Commissariat Energie Atomique Procede ameliore d'assemblage par collage direct entre deux elements, chaque element comprenant des portions de metal et de materiaux dielectriques
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US9455182B2 (en) 2014-08-22 2016-09-27 International Business Machines Corporation Interconnect structure with capping layer and barrier layer
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
US9741620B2 (en) 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US10032751B2 (en) 2015-09-28 2018-07-24 Invensas Corporation Ultrathin layer for forming a capacitive interface between joined integrated circuit components
US10811388B2 (en) 2015-09-28 2020-10-20 Invensas Corporation Capacitive coupling in a direct-bonded interface for microelectronic devices
US9852988B2 (en) 2015-12-18 2017-12-26 Invensas Bonding Technologies, Inc. Increased contact alignment tolerance for direct bonding
US10446532B2 (en) 2016-01-13 2019-10-15 Invensas Bonding Technologies, Inc. Systems and methods for efficient transfer of semiconductor elements
US10636767B2 (en) 2016-02-29 2020-04-28 Invensas Corporation Correction die for wafer/die stack
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US10446487B2 (en) 2016-09-30 2019-10-15 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10719762B2 (en) 2017-08-03 2020-07-21 Xcelsis Corporation Three dimensional chip structure implementing machine trained network
US10580735B2 (en) 2016-10-07 2020-03-03 Xcelsis Corporation Stacked IC structure with system level wiring on multiple sides of the IC die
TW202414634A (zh) 2016-10-27 2024-04-01 美商艾德亞半導體科技有限責任公司 用於低溫接合的結構和方法
US10002844B1 (en) 2016-12-21 2018-06-19 Invensas Bonding Technologies, Inc. Bonded structures
US10796936B2 (en) 2016-12-22 2020-10-06 Invensas Bonding Technologies, Inc. Die tray with channels
US10707087B2 (en) 2016-12-28 2020-07-07 Invensas Bonding Technologies, Inc. Processing stacked substrates
US20180182665A1 (en) 2016-12-28 2018-06-28 Invensas Bonding Technologies, Inc. Processed Substrate
KR20190092584A (ko) 2016-12-29 2019-08-07 인벤사스 본딩 테크놀로지스 인코포레이티드 집적된 수동 컴포넌트를 구비한 접합된 구조체
US10276909B2 (en) 2016-12-30 2019-04-30 Invensas Bonding Technologies, Inc. Structure comprising at least a first element bonded to a carrier having a closed metallic channel waveguide formed therein
JP7030825B2 (ja) 2017-02-09 2022-03-07 インヴェンサス ボンディング テクノロジーズ インコーポレイテッド 接合構造物
WO2018169968A1 (en) 2017-03-16 2018-09-20 Invensas Corporation Direct-bonded led arrays and applications
US10515913B2 (en) 2017-03-17 2019-12-24 Invensas Bonding Technologies, Inc. Multi-metal contact structure
US10508030B2 (en) 2017-03-21 2019-12-17 Invensas Bonding Technologies, Inc. Seal for microelectronic assembly
WO2018183739A1 (en) 2017-03-31 2018-10-04 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10269756B2 (en) 2017-04-21 2019-04-23 Invensas Bonding Technologies, Inc. Die processing
US10529634B2 (en) 2017-05-11 2020-01-07 Invensas Bonding Technologies, Inc. Probe methodology for ultrafine pitch interconnects
US10879212B2 (en) 2017-05-11 2020-12-29 Invensas Bonding Technologies, Inc. Processed stacked dies
IT201700053902A1 (it) 2017-05-18 2018-11-18 Lfoundry Srl Metodo di bonding ibrido per wafer a semiconduttore e relativo dispositivo integrato tridimensionale
US10446441B2 (en) 2017-06-05 2019-10-15 Invensas Corporation Flat metal features for microelectronics applications
US10217720B2 (en) 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
JP2019054153A (ja) * 2017-09-15 2019-04-04 東芝メモリ株式会社 半導体装置の製造方法
US10840205B2 (en) * 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11195748B2 (en) 2017-09-27 2021-12-07 Invensas Corporation Interconnect structures and methods for forming same
US11031285B2 (en) 2017-10-06 2021-06-08 Invensas Bonding Technologies, Inc. Diffusion barrier collar for interconnects
US10658313B2 (en) 2017-12-11 2020-05-19 Invensas Bonding Technologies, Inc. Selective recess
US11011503B2 (en) 2017-12-15 2021-05-18 Invensas Bonding Technologies, Inc. Direct-bonded optoelectronic interconnect for high-density integrated photonics
US10923408B2 (en) 2017-12-22 2021-02-16 Invensas Bonding Technologies, Inc. Cavity packages
US11380597B2 (en) 2017-12-22 2022-07-05 Invensas Bonding Technologies, Inc. Bonded structures
WO2019144219A1 (en) 2018-01-23 2019-08-01 Lumiense Photonics Inc. Method of manufacturing of advanced three-dimensional semiconductor structures and structures produced therefrom
DE102018103431A1 (de) * 2018-02-15 2019-08-22 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung einer Verbindung zwischen Bauteilen und Bauelement aus Bauteilen
US10727219B2 (en) 2018-02-15 2020-07-28 Invensas Bonding Technologies, Inc. Techniques for processing devices
US11169326B2 (en) 2018-02-26 2021-11-09 Invensas Bonding Technologies, Inc. Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects
US11256004B2 (en) 2018-03-20 2022-02-22 Invensas Bonding Technologies, Inc. Direct-bonded lamination for improved image clarity in optical devices
JP6952629B2 (ja) * 2018-03-20 2021-10-20 株式会社東芝 半導体装置
KR102075764B1 (ko) * 2018-03-28 2020-02-10 한국과학기술원 이종 광 집적회로 및 이의 제조 방법
US11056348B2 (en) 2018-04-05 2021-07-06 Invensas Bonding Technologies, Inc. Bonding surfaces for microelectronics
US11244916B2 (en) 2018-04-11 2022-02-08 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US10790262B2 (en) 2018-04-11 2020-09-29 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US12046505B2 (en) 2018-04-20 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same utilizing localized SOI formation
US10964664B2 (en) 2018-04-20 2021-03-30 Invensas Bonding Technologies, Inc. DBI to Si bonding for simplified handle wafer
US11004757B2 (en) * 2018-05-14 2021-05-11 Invensas Bonding Technologies, Inc. Bonded structures
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
CN108520858A (zh) * 2018-06-07 2018-09-11 长江存储科技有限责任公司 金属连接结构及其形成方法
WO2019241367A1 (en) 2018-06-12 2019-12-19 Invensas Bonding Technologies, Inc. Interlayer connection of stacked microelectronic components
US10910344B2 (en) 2018-06-22 2021-02-02 Xcelsis Corporation Systems and methods for releveled bump planes for chiplets
US20200006193A1 (en) 2018-07-02 2020-01-02 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
WO2020010056A1 (en) 2018-07-03 2020-01-09 Invensas Bonding Technologies, Inc. Techniques for joining dissimilar materials in microelectronics
US11462419B2 (en) 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US11158606B2 (en) 2018-07-06 2021-10-26 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
US11211333B2 (en) * 2018-07-16 2021-12-28 Taiwan Semiconductor Manufacturing Co., Ltd. Through silicon via optimization for three-dimensional integrated circuits
US10700094B2 (en) * 2018-08-08 2020-06-30 Xcelsis Corporation Device disaggregation for improved performance
US11515291B2 (en) 2018-08-28 2022-11-29 Adeia Semiconductor Inc. Integrated voltage regulator and passive components
US11309334B2 (en) 2018-09-11 2022-04-19 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
KR102661959B1 (ko) 2018-09-20 2024-04-30 삼성전자주식회사 반도체 장치 및 이를 포함하는 반도체 패키지
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
KR102596758B1 (ko) 2018-10-24 2023-11-03 삼성전자주식회사 반도체 패키지
US11309278B2 (en) * 2018-10-29 2022-04-19 Applied Materials, Inc. Methods for bonding substrates
US11211334B2 (en) 2018-11-18 2021-12-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US11646242B2 (en) 2018-11-29 2023-05-09 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
CN111739792B (zh) * 2018-11-30 2021-06-08 长江存储科技有限责任公司 键合存储器件及其制造方法
JP7243015B2 (ja) * 2018-12-04 2023-03-22 日清紡マイクロデバイス株式会社 電子部品および電子部品の接合構造
US11244920B2 (en) 2018-12-18 2022-02-08 Invensas Bonding Technologies, Inc. Method and structures for low temperature device bonding
US11476213B2 (en) 2019-01-14 2022-10-18 Invensas Bonding Technologies, Inc. Bonded structures without intervening adhesive
US12046483B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US20200235040A1 (en) 2019-01-23 2020-07-23 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
US12046570B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11923313B2 (en) 2019-01-23 2024-03-05 Qorvo Us, Inc. RF device without silicon handle substrate for enhanced thermal and electrical performance and methods of forming the same
US11387157B2 (en) 2019-01-23 2022-07-12 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11901281B2 (en) 2019-03-11 2024-02-13 Adeia Semiconductor Bonding Technologies Inc. Bonded structures with integrated passive component
US10854578B2 (en) 2019-03-29 2020-12-01 Invensas Corporation Diffused bitline replacement in stacked wafer memory
US11373963B2 (en) 2019-04-12 2022-06-28 Invensas Bonding Technologies, Inc. Protective elements for bonded structures
US11610846B2 (en) 2019-04-12 2023-03-21 Adeia Semiconductor Bonding Technologies Inc. Protective elements for bonded structures including an obstructive element
US11205625B2 (en) 2019-04-12 2021-12-21 Invensas Bonding Technologies, Inc. Wafer-level bonding of obstructive elements
US11355404B2 (en) 2019-04-22 2022-06-07 Invensas Bonding Technologies, Inc. Mitigating surface damage of probe pads in preparation for direct bonding of a substrate
US11385278B2 (en) * 2019-05-23 2022-07-12 Invensas Bonding Technologies, Inc. Security circuitry for bonded structures
US20200395321A1 (en) 2019-06-12 2020-12-17 Invensas Bonding Technologies, Inc. Sealed bonded structures and methods for forming the same
US20230386999A1 (en) * 2019-06-13 2023-11-30 Nanya Technology Corporation Method of manufacturing integrated circuit device with bonding structure
US11315871B2 (en) * 2019-06-13 2022-04-26 Nanya Technology Corporation Integrated circuit device with bonding structure and method of forming the same
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11227838B2 (en) 2019-07-02 2022-01-18 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits
TWI686518B (zh) 2019-07-19 2020-03-01 國立交通大學 具有奈米雙晶銅之電連接結構及其形成方法
US11139272B2 (en) * 2019-07-26 2021-10-05 Sandisk Technologies Llc Bonded assembly containing oxidation barriers and/or adhesion enhancers and methods of forming the same
US11393780B2 (en) 2019-07-26 2022-07-19 Sandisk Technologies Llc Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same
US11515273B2 (en) 2019-07-26 2022-11-29 Sandisk Technologies Llc Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same
US11443981B2 (en) * 2019-08-16 2022-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding method of package components and bonding apparatus
KR20210024893A (ko) 2019-08-26 2021-03-08 삼성전자주식회사 반도체 소자 제조 방법
KR20210025156A (ko) 2019-08-26 2021-03-09 삼성전자주식회사 반도체 장치 및 그 제조방법
US11862602B2 (en) 2019-11-07 2024-01-02 Adeia Semiconductor Technologies Llc Scalable architecture for reduced cycles across SOC
US11094653B2 (en) * 2019-11-13 2021-08-17 Sandisk Technologies Llc Bonded assembly containing a dielectric bonding pattern definition layer and methods of forming the same
GB2589329B (en) * 2019-11-26 2022-02-09 Plessey Semiconductors Ltd Substrate bonding
US11646289B2 (en) 2019-12-02 2023-05-09 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive
US11762200B2 (en) 2019-12-17 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded optical devices
US11876076B2 (en) 2019-12-20 2024-01-16 Adeia Semiconductor Technologies Llc Apparatus for non-volatile random access memory stacks
US11721653B2 (en) 2019-12-23 2023-08-08 Adeia Semiconductor Bonding Technologies Inc. Circuitry for electrical redundancy in bonded structures
KR20220120631A (ko) 2019-12-23 2022-08-30 인벤사스 본딩 테크놀로지스 인코포레이티드 결합형 구조체를 위한 전기적 리던던시
US11270963B2 (en) * 2020-01-14 2022-03-08 Sandisk Technologies Llc Bonding pads including interfacial electromigration barrier layers and methods of making the same
CN111244123A (zh) * 2020-02-03 2020-06-05 长江存储科技有限责任公司 半导体结构及其制备方法
US20210265253A1 (en) 2020-02-25 2021-08-26 Tokyo Electron Limited Split substrate interposer with integrated passive device
CN115943489A (zh) 2020-03-19 2023-04-07 隔热半导体粘合技术公司 用于直接键合结构的尺寸补偿控制
JP2021150574A (ja) * 2020-03-23 2021-09-27 キオクシア株式会社 半導体装置
US11742314B2 (en) 2020-03-31 2023-08-29 Adeia Semiconductor Bonding Technologies Inc. Reliable hybrid bonded apparatus
CN111463114B (zh) * 2020-04-17 2021-08-06 武汉新芯集成电路制造有限公司 半导体器件及其形成方法、芯片
WO2021236361A1 (en) 2020-05-19 2021-11-25 Invensas Bonding Technologies, Inc. Laterally unconfined structure
US11233088B2 (en) * 2020-06-12 2022-01-25 Omnivision Technologies, Inc. Metal routing in image sensor using hybrid bonding
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11430753B2 (en) 2020-07-08 2022-08-30 Raytheon Company Iterative formation of damascene interconnects
KR20220014759A (ko) 2020-07-29 2022-02-07 삼성전자주식회사 본딩 신뢰성을 향상시킬 수 있는 반도체 패키지
KR20220021798A (ko) 2020-08-14 2022-02-22 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11164822B1 (en) * 2020-09-28 2021-11-02 United Microelectronics Corp. Structure of semiconductor device and method for bonding two substrates
US11837623B2 (en) 2020-10-12 2023-12-05 Raytheon Company Integrated circuit having vertical routing to bond pads
US11264357B1 (en) 2020-10-20 2022-03-01 Invensas Corporation Mixed exposure for large die
EP3993021A1 (en) * 2020-11-03 2022-05-04 Infineon Technologies AG Method of manufacturing a bonded substrate stack
KR20220060612A (ko) * 2020-11-04 2022-05-12 삼성전자주식회사 반도체 장치 및 이를 포함하는 데이터 저장 시스템
KR20220060620A (ko) 2020-11-04 2022-05-12 삼성전자주식회사 반도체 장치 및 이를 포함하는 전자 시스템
US11424215B2 (en) * 2020-11-10 2022-08-23 Sandisk Technologies Llc Bonded assembly formed by hybrid wafer bonding using selectively deposited metal liners
US11710756B2 (en) 2020-11-19 2023-07-25 Raytheon Company Integrating optical elements with electro-optical sensors via direct-bond hybridization
WO2022125722A1 (en) * 2020-12-11 2022-06-16 Qorvo Us, Inc. Microelectronics package with vertically stacked wafer slices and process for making the same
US11527501B1 (en) * 2020-12-15 2022-12-13 Intel Corporation Sacrificial redistribution layer in microelectronic assemblies having direct bonding
WO2022172349A1 (ja) * 2021-02-10 2022-08-18 キヤノンアネルバ株式会社 化学結合法及びパッケージ型電子部品
CN113299601A (zh) * 2021-05-21 2021-08-24 浙江集迈科微电子有限公司 一种多层转接板的晶圆级焊接工艺
CN115513046A (zh) 2021-06-23 2022-12-23 联华电子股份有限公司 半导体元件
US11817420B2 (en) 2021-07-19 2023-11-14 Micron Technology, Inc. Systems and methods for direct bonding in semiconductor die manufacturing
WO2023162264A1 (ja) * 2022-02-28 2023-08-31 株式会社レゾナック 半導体装置の製造方法、及び半導体装置
WO2023195322A1 (ja) * 2022-04-06 2023-10-12 Ｈｄマイクロシステムズ株式会社 半導体装置の製造方法、ハイブリッドボンディング絶縁膜形成材料及び半導体装置
US20240170452A1 (en) * 2022-11-22 2024-05-23 Applied Materials, Inc. Method for collective dishing of singulated dies

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030113976A1 (en) * 2001-12-17 2003-06-19 Stefan Hau-Riege Wafer-bonding using solder and method of making the same
US20040056361A1 (en) * 2000-03-21 2004-03-25 Mcteer Allen Multi-layered copper bond pad for an integrated circuit
US20060024950A1 (en) * 2004-08-02 2006-02-02 Suk-Hun Choi Methods of forming metal contact structures and methods of fabricating phase-change memory devices using the same
US20070212870A1 (en) * 2006-03-13 2007-09-13 International Business Machines Corporation Interconnect structure with a barrier-redundancy feature
KR100850212B1 (ko) * 2007-04-20 2008-08-04 삼성전자주식회사 균일한 무전해 도금 두께를 얻을 수 있는 반도체 소자의제조방법
JP2012019148A (ja) * 2010-07-09 2012-01-26 Canon Inc 固体撮像装置用の部材および固体撮像装置の製造方法
US20130221527A1 (en) * 2012-02-24 2013-08-29 International Business Machines Corporation Metallic capped interconnect structure with high electromigration resistance and low resistivity
US20130285248A1 (en) * 2012-04-26 2013-10-31 Asia Pacific Microsystems, Inc. Package Structure and Substrate Bonding Method
US20130320556A1 (en) * 2012-06-05 2013-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. Three Dimensional Integrated Circuit Structures and Hybrid Bonding Methods for Semiconductor Wafers
US20140353828A1 (en) * 2013-05-30 2014-12-04 International Business Machines Corporation Substrate bonding with diffusion barrier structures
US20150108644A1 (en) * 2013-10-17 2015-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. 3D Integrated Circuit and Methods of Forming the Same
CN104576518A (zh) * 2013-10-23 2015-04-29 格罗方德半导体公司 用于后段制程金属化的混合型锰和氮化锰阻障物及其制法

Family Cites Families (264)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6130059A (ja) 1984-07-20 1986-02-12 Nec Corp 半導体装置の製造方法
KR900008647B1 (ko) 1986-03-20 1990-11-26 후지쓰 가부시끼가이샤 3차원 집적회로와 그의 제조방법
JPH07112041B2 (ja) 1986-12-03 1995-11-29 シャープ株式会社 半導体装置の製造方法
US4904328A (en) 1987-09-08 1990-02-27 Gencorp Inc. Bonding of FRP parts
US4784970A (en) 1987-11-18 1988-11-15 Grumman Aerospace Corporation Process for making a double wafer moated signal processor
JPH0272642A (ja) 1988-09-07 1990-03-12 Nec Corp 基板の接続構造および接続方法
JPH0344067A (ja) 1989-07-11 1991-02-25 Nec Corp 半導体基板の積層方法
US5489804A (en) 1989-08-28 1996-02-06 Lsi Logic Corporation Flexible preformed planar structures for interposing between a chip and a substrate
JP3190057B2 (ja) 1990-07-02 2001-07-16 株式会社東芝 複合集積回路装置
JP2729413B2 (ja) 1991-02-14 1998-03-18 三菱電機株式会社 半導体装置
JP2910334B2 (ja) 1991-07-22 1999-06-23 富士電機株式会社 接合方法
JPH05198739A (ja) 1991-09-10 1993-08-06 Mitsubishi Electric Corp 積層型半導体装置およびその製造方法
CA2083072C (en) 1991-11-21 1998-02-03 Shinichi Hasegawa Method for manufacturing polyimide multilayer wiring substrate
US6008126A (en) 1992-04-08 1999-12-28 Elm Technology Corporation Membrane dielectric isolation IC fabrication
US5236118A (en) 1992-05-12 1993-08-17 The Regents Of The University Of California Aligned wafer bonding
JPH0682753B2 (ja) 1992-09-28 1994-10-19 株式会社東芝 半導体装置の製造方法
US5503704A (en) 1993-01-06 1996-04-02 The Regents Of The University Of California Nitrogen based low temperature direct bonding
DE59406156D1 (de) 1993-02-11 1998-07-16 Siemens Ag Verfahren zur Herstellung einer dreidimensionalen Schaltungsanordnung
US5516727A (en) 1993-04-19 1996-05-14 International Business Machines Corporation Method for encapsulating light emitting diodes
JPH0766093A (ja) 1993-08-23 1995-03-10 Sumitomo Sitix Corp 半導体ウエーハの貼り合わせ方法およびその装置
EP0651449B1 (en) 1993-11-01 2002-02-13 Matsushita Electric Industrial Co., Ltd. Electronic component and method for producing the same
US5501003A (en) 1993-12-15 1996-03-26 Bel Fuse Inc. Method of assembling electronic packages for surface mount applications
US5442235A (en) * 1993-12-23 1995-08-15 Motorola Inc. Semiconductor device having an improved metal interconnect structure
US5413952A (en) 1994-02-02 1995-05-09 Motorola, Inc. Direct wafer bonded structure method of making
JP3294934B2 (ja) 1994-03-11 2002-06-24 キヤノン株式会社 半導体基板の作製方法及び半導体基板
JPH07283382A (ja) 1994-04-12 1995-10-27 Sony Corp シリコン基板のはり合わせ方法
KR960009074A (ko) 1994-08-29 1996-03-22 모리시다 요이치 반도체 장치 및 그 제조방법
JPH08125121A (ja) 1994-08-29 1996-05-17 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP3171366B2 (ja) 1994-09-05 2001-05-28 三菱マテリアル株式会社 シリコン半導体ウェーハ及びその製造方法
DE4433330C2 (de) 1994-09-19 1997-01-30 Fraunhofer Ges Forschung Verfahren zur Herstellung von Halbleiterstrukturen mit vorteilhaften Hochfrequenzeigenschaften sowie eine Halbleiterwaferstruktur
DE4433845A1 (de) 1994-09-22 1996-03-28 Fraunhofer Ges Forschung Verfahren zur Herstellung einer dreidimensionalen integrierten Schaltung
JPH08186235A (ja) 1994-12-16 1996-07-16 Texas Instr Inc <Ti> 半導体装置の製造方法
JP2679681B2 (ja) 1995-04-28 1997-11-19 日本電気株式会社 半導体装置、半導体装置用パッケージ及びその製造方法
US5610431A (en) 1995-05-12 1997-03-11 The Charles Stark Draper Laboratory, Inc. Covers for micromechanical sensors and other semiconductor devices
JP3490198B2 (ja) 1995-10-25 2004-01-26 松下電器産業株式会社 半導体装置とその製造方法
JP3979687B2 (ja) 1995-10-26 2007-09-19 アプライド マテリアルズ インコーポレイテッド ハロゲンをドープした酸化珪素膜の膜安定性を改良する方法
KR100438256B1 (ko) 1995-12-18 2004-08-25 마츠시타 덴끼 산교 가부시키가이샤 반도체장치 및 그 제조방법
US5956605A (en) 1996-09-20 1999-09-21 Micron Technology, Inc. Use of nitrides for flip-chip encapsulation
JP3383811B2 (ja) 1996-10-28 2003-03-10 松下電器産業株式会社 半導体チップモジュール及びその製造方法
US5888631A (en) 1996-11-08 1999-03-30 W. L. Gore & Associates, Inc. Method for minimizing warp in the production of electronic assemblies
US6054363A (en) 1996-11-15 2000-04-25 Canon Kabushiki Kaisha Method of manufacturing semiconductor article
US5821692A (en) 1996-11-26 1998-10-13 Motorola, Inc. Organic electroluminescent device hermetic encapsulation package
US6809421B1 (en) 1996-12-02 2004-10-26 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof
US6333206B1 (en) 1996-12-24 2001-12-25 Nitto Denko Corporation Process for the production of semiconductor device
US6221753B1 (en) 1997-01-24 2001-04-24 Micron Technology, Inc. Flip chip technique for chip assembly
JPH10223636A (ja) 1997-02-12 1998-08-21 Nec Yamagata Ltd 半導体集積回路装置の製造方法
JP4026882B2 (ja) * 1997-02-24 2007-12-26 三洋電機株式会社 半導体装置
US5929512A (en) 1997-03-18 1999-07-27 Jacobs; Richard L. Urethane encapsulated integrated circuits and compositions therefor
US5915167A (en) 1997-04-04 1999-06-22 Elm Technology Corporation Three dimensional structure memory
AU7147798A (en) 1997-04-23 1998-11-13 Advanced Chemical Systems International, Inc. Planarization compositions for cmp of interlayer dielectrics
JP4032454B2 (ja) 1997-06-27 2008-01-16 ソニー株式会社 三次元回路素子の製造方法
US6097096A (en) 1997-07-11 2000-08-01 Advanced Micro Devices Metal attachment method and structure for attaching substrates at low temperatures
JPH11186120A (ja) 1997-12-24 1999-07-09 Canon Inc 同種あるいは異種材料基板間の密着接合法
US6137063A (en) 1998-02-27 2000-10-24 Micron Technology, Inc. Electrical interconnections
EP0951068A1 (en) 1998-04-17 1999-10-20 Interuniversitair Micro-Elektronica Centrum Vzw Method of fabrication of a microstructure having an inside cavity
US6147000A (en) * 1998-08-11 2000-11-14 Advanced Micro Devices, Inc. Method for forming low dielectric passivation of copper interconnects
US6316786B1 (en) 1998-08-29 2001-11-13 International Business Machines Corporation Organic opto-electronic devices
JP2000100679A (ja) 1998-09-22 2000-04-07 Canon Inc 薄片化による基板間微小領域固相接合法及び素子構造
JP2000150810A (ja) 1998-11-17 2000-05-30 Toshiba Microelectronics Corp 半導体装置及びその製造方法
US6515343B1 (en) 1998-11-19 2003-02-04 Quicklogic Corporation Metal-to-metal antifuse with non-conductive diffusion barrier
US6232150B1 (en) 1998-12-03 2001-05-15 The Regents Of The University Of Michigan Process for making microstructures and microstructures made thereby
JP3293792B2 (ja) 1999-01-12 2002-06-17 日本電気株式会社 半導体装置及びその製造方法
JP3918350B2 (ja) 1999-03-05 2007-05-23 セイコーエプソン株式会社 半導体装置の製造方法
US6348709B1 (en) * 1999-03-15 2002-02-19 Micron Technology, Inc. Electrical contact for high dielectric constant capacitors and method for fabricating the same
JP3532788B2 (ja) 1999-04-13 2004-05-31 唯知 須賀 半導体装置及びその製造方法
US6259160B1 (en) * 1999-04-21 2001-07-10 Advanced Micro Devices, Inc. Apparatus and method of encapsulated copper (Cu) Interconnect formation
JP2000311982A (ja) 1999-04-26 2000-11-07 Toshiba Corp 半導体装置と半導体モジュールおよびそれらの製造方法
US6258625B1 (en) 1999-05-18 2001-07-10 International Business Machines Corporation Method of interconnecting electronic components using a plurality of conductive studs
KR100333384B1 (ko) 1999-06-28 2002-04-18 박종섭 칩 사이즈 스택 패키지 및 그의 제조방법
US6218203B1 (en) 1999-06-28 2001-04-17 Advantest Corp. Method of producing a contact structure
JP3619395B2 (ja) 1999-07-30 2005-02-09 京セラ株式会社 半導体素子内蔵配線基板およびその製造方法
US6756253B1 (en) 1999-08-27 2004-06-29 Micron Technology, Inc. Method for fabricating a semiconductor component with external contact polymer support layer
US6583515B1 (en) 1999-09-03 2003-06-24 Texas Instruments Incorporated Ball grid array package for enhanced stress tolerance
US6593645B2 (en) 1999-09-24 2003-07-15 United Microelectronics Corp. Three-dimensional system-on-chip structure
JP2001102479A (ja) 1999-09-27 2001-04-13 Toshiba Corp 半導体集積回路装置およびその製造方法
US6984571B1 (en) 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6902987B1 (en) 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
EP1130654A1 (de) 2000-03-01 2001-09-05 Infineon Technologies AG Integriertes Bauelement mit Metall-Isolator-Metall-Kondensator
JP4123682B2 (ja) 2000-05-16 2008-07-23 セイコーエプソン株式会社 半導体装置及びその製造方法
US6326698B1 (en) 2000-06-08 2001-12-04 Micron Technology, Inc. Semiconductor devices having protective layers thereon through which contact pads are exposed and stereolithographic methods of fabricating such semiconductor devices
JP4322402B2 (ja) 2000-06-22 2009-09-02 大日本印刷株式会社 プリント配線基板及びその製造方法
JP2002009248A (ja) 2000-06-26 2002-01-11 Oki Electric Ind Co Ltd キャパシタおよびその製造方法
JP3440057B2 (ja) 2000-07-05 2003-08-25 唯知 須賀 半導体装置およびその製造方法
TW515223B (en) 2000-07-24 2002-12-21 Tdk Corp Light emitting device
US6423640B1 (en) 2000-08-09 2002-07-23 Taiwan Semiconductor Manufacturing Co., Ltd. Headless CMP process for oxide planarization
US6483044B1 (en) 2000-08-23 2002-11-19 Micron Technology, Inc. Interconnecting substrates for electrical coupling of microelectronic components
US6583460B1 (en) * 2000-08-29 2003-06-24 Micron Technology, Inc. Method of forming a metal to polysilicon contact in oxygen environment
JP2002110799A (ja) 2000-09-27 2002-04-12 Toshiba Corp 半導体装置及びその製造方法
US6600224B1 (en) 2000-10-31 2003-07-29 International Business Machines Corporation Thin film attachment to laminate using a dendritic interconnection
US6552436B2 (en) 2000-12-08 2003-04-22 Motorola, Inc. Semiconductor device having a ball grid array and method therefor
US7084507B2 (en) 2001-05-02 2006-08-01 Fujitsu Limited Integrated circuit device and method of producing the same
JP2002353416A (ja) 2001-05-25 2002-12-06 Sony Corp 半導体記憶装置およびその製造方法
JP3705159B2 (ja) 2001-06-11 2005-10-12 株式会社デンソー 半導体装置の製造方法
DE10131627B4 (de) 2001-06-29 2006-08-10 Infineon Technologies Ag Verfahren zum Herstellen einer Halbleiterspeichereinrichtung
JP2003023071A (ja) 2001-07-05 2003-01-24 Sony Corp 半導体装置製造方法および半導体装置
US6847527B2 (en) 2001-08-24 2005-01-25 3M Innovative Properties Company Interconnect module with reduced power distribution impedance
US6555917B1 (en) 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
US20030113947A1 (en) 2001-12-19 2003-06-19 Vandentop Gilroy J. Electrical/optical integration scheme using direct copper bonding
US6660564B2 (en) 2002-01-25 2003-12-09 Sony Corporation Wafer-level through-wafer packaging process for MEMS and MEMS package produced thereby
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6624003B1 (en) 2002-02-06 2003-09-23 Teravicta Technologies, Inc. Integrated MEMS device and package
US6661085B2 (en) 2002-02-06 2003-12-09 Intel Corporation Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US6720212B2 (en) 2002-03-14 2004-04-13 Infineon Technologies Ag Method of eliminating back-end rerouting in ball grid array packaging
US6627814B1 (en) 2002-03-22 2003-09-30 David H. Stark Hermetically sealed micro-device package with window
US6642081B1 (en) 2002-04-11 2003-11-04 Robert Patti Interlocking conductor method for bonding wafers to produce stacked integrated circuits
US6713402B2 (en) 2002-05-31 2004-03-30 Texas Instruments Incorporated Methods for polymer removal following etch-stop layer etch
CN1248304C (zh) 2002-06-13 2006-03-29 松下电器产业株式会社 布线结构的形成方法
TWI229435B (en) 2002-06-18 2005-03-11 Sanyo Electric Co Manufacture of semiconductor device
US7105980B2 (en) 2002-07-03 2006-09-12 Sawtek, Inc. Saw filter device and method employing normal temperature bonding for producing desirable filter production and performance characteristics
JP2004133384A (ja) 2002-08-14 2004-04-30 Sony Corp レジスト用剥離剤組成物及び半導体装置の製造方法
JP4083502B2 (ja) 2002-08-19 2008-04-30 株式会社フジミインコーポレーテッド 研磨方法及びそれに用いられる研磨用組成物
US7023093B2 (en) 2002-10-24 2006-04-04 International Business Machines Corporation Very low effective dielectric constant interconnect Structures and methods for fabricating the same
US7485962B2 (en) 2002-12-10 2009-02-03 Fujitsu Limited Semiconductor device, wiring substrate forming method, and substrate processing apparatus
JP3918935B2 (ja) 2002-12-20 2007-05-23 セイコーエプソン株式会社 半導体装置の製造方法
US7354798B2 (en) 2002-12-20 2008-04-08 International Business Machines Corporation Three-dimensional device fabrication method
KR100598245B1 (ko) 2002-12-30 2006-07-07 동부일렉트로닉스 주식회사 반도체 금속 배선 형성 방법
JP4173374B2 (ja) 2003-01-08 2008-10-29 株式会社ルネサステクノロジ 半導体装置の製造方法
JP3981026B2 (ja) 2003-01-30 2007-09-26 株式会社東芝 多層配線層を有する半導体装置およびその製造方法
US6962835B2 (en) 2003-02-07 2005-11-08 Ziptronix, Inc. Method for room temperature metal direct bonding
US7135780B2 (en) 2003-02-12 2006-11-14 Micron Technology, Inc. Semiconductor substrate for build-up packages
JP4082236B2 (ja) 2003-02-21 2008-04-30 ソニー株式会社 半導体装置及びその製造方法
JP4001115B2 (ja) 2003-02-28 2007-10-31 セイコーエプソン株式会社 半導体装置及びその製造方法
US6908027B2 (en) 2003-03-31 2005-06-21 Intel Corporation Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening process
DE10319538B4 (de) 2003-04-30 2008-01-17 Qimonda Ag Halbleitervorrichtung und Verfahren zur Herstellung einer Halbleitereinrichtung
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
JP4130158B2 (ja) 2003-06-09 2008-08-06 三洋電機株式会社 半導体装置の製造方法、半導体装置
US20040245636A1 (en) 2003-06-06 2004-12-09 International Business Machines Corporation Full removal of dual damascene metal level
TWI275168B (en) 2003-06-06 2007-03-01 Sanyo Electric Co Semiconductor device and method for making the same
TWI229930B (en) 2003-06-09 2005-03-21 Advanced Semiconductor Eng Chip structure
US20040262772A1 (en) 2003-06-30 2004-12-30 Shriram Ramanathan Methods for bonding wafers using a metal interlayer
JP2005086089A (ja) 2003-09-10 2005-03-31 Seiko Epson Corp ３次元デバイスの製造方法
JP2005093486A (ja) 2003-09-12 2005-04-07 Seiko Epson Corp 半導体装置の製造方法及び半導体装置
US6867073B1 (en) 2003-10-21 2005-03-15 Ziptronix, Inc. Single mask via method and device
JP2005135988A (ja) 2003-10-28 2005-05-26 Toshiba Corp 半導体装置の製造方法
DE102004001853B3 (de) 2004-01-13 2005-07-21 Infineon Technologies Ag Verfahren zum Herstellen von Kontaktierungsanschlüssen
US7842948B2 (en) 2004-02-27 2010-11-30 Nvidia Corporation Flip chip semiconductor die internal signal access system and method
JP4897201B2 (ja) 2004-05-31 2012-03-14 ルネサスエレクトロニクス株式会社 半導体装置
JP4376715B2 (ja) 2004-07-16 2009-12-02 三洋電機株式会社 半導体装置の製造方法
US20060057945A1 (en) 2004-09-16 2006-03-16 Chia-Lin Hsu Chemical mechanical polishing process
US20060076634A1 (en) 2004-09-27 2006-04-13 Lauren Palmateer Method and system for packaging MEMS devices with incorporated getter
KR100580212B1 (ko) 2004-12-20 2006-05-16 삼성전자주식회사 급지장치 및 이를 구비하는 화상형성장치
GB0505680D0 (en) 2005-03-22 2005-04-27 Cambridge Display Tech Ltd Apparatus and method for increased device lifetime in an organic electro-luminescent device
US7485968B2 (en) 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
US7193423B1 (en) 2005-12-12 2007-03-20 International Business Machines Corporation Wafer-to-wafer alignments
TWI299552B (en) 2006-03-24 2008-08-01 Advanced Semiconductor Eng Package structure
US7972683B2 (en) 2006-03-28 2011-07-05 Innovative Micro Technology Wafer bonding material with embedded conductive particles
US7750488B2 (en) 2006-07-10 2010-07-06 Tezzaron Semiconductor, Inc. Method for bonding wafers to produce stacked integrated circuits
KR100825648B1 (ko) * 2006-11-29 2008-04-25 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조 방법
US7803693B2 (en) 2007-02-15 2010-09-28 John Trezza Bowed wafer hybridization compensation
DE102008007001B4 (de) * 2008-01-31 2016-09-22 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Vergrößern des Widerstandsverhaltens gegenüber Elektromigration in einer Verbindungsstruktur eines Halbleiterbauelements durch Bilden einer Legierung
US20090200668A1 (en) * 2008-02-07 2009-08-13 International Business Machines Corporation Interconnect structure with high leakage resistance
US8349635B1 (en) 2008-05-20 2013-01-08 Silicon Laboratories Inc. Encapsulated MEMS device and method to form the same
US9893004B2 (en) 2011-07-27 2018-02-13 Broadpak Corporation Semiconductor interposer integration
KR100945800B1 (ko) 2008-12-09 2010-03-05 김영혜 이종 접합 웨이퍼 제조방법
US8476165B2 (en) 2009-04-01 2013-07-02 Tokyo Electron Limited Method for thinning a bonding wafer
US8101517B2 (en) * 2009-09-29 2012-01-24 Infineon Technologies Ag Semiconductor device and method for making same
US8482132B2 (en) * 2009-10-08 2013-07-09 International Business Machines Corporation Pad bonding employing a self-aligned plated liner for adhesion enhancement
FR2954585B1 (fr) 2009-12-23 2012-03-02 Soitec Silicon Insulator Technologies Procede de realisation d'une heterostructure avec minimisation de contrainte
EP2544225A4 (en) * 2010-03-01 2018-07-25 Osaka University Semiconductor device and bonding material for semiconductor device
FR2966283B1 (fr) 2010-10-14 2012-11-30 Soi Tec Silicon On Insulator Tech Sa Procede pour realiser une structure de collage
US8377798B2 (en) 2010-11-10 2013-02-19 Taiwan Semiconductor Manufacturing Co., Ltd Method and structure for wafer to wafer bonding in semiconductor packaging
US8476146B2 (en) 2010-12-03 2013-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing wafer distortion through a low CTE layer
US8778773B2 (en) * 2010-12-16 2014-07-15 Soitec Methods for directly bonding together semiconductor structures, and bonded semiconductor structures formed using such methods
US8620164B2 (en) 2011-01-20 2013-12-31 Intel Corporation Hybrid III-V silicon laser formed by direct bonding
US8988299B2 (en) 2011-02-17 2015-03-24 International Business Machines Corporation Integrated antenna for RFIC package applications
JP2012174988A (ja) * 2011-02-23 2012-09-10 Sony Corp 接合電極、接合電極の製造方法、半導体装置、及び、半導体装置の製造方法
US8501537B2 (en) 2011-03-31 2013-08-06 Soitec Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures formed using such methods
US8716105B2 (en) 2011-03-31 2014-05-06 Soitec Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures and intermediate structures formed using such methods
KR20230130169A (ko) 2011-05-24 2023-09-11 소니그룹주식회사 반도체 장치
JP5982748B2 (ja) 2011-08-01 2016-08-31 ソニー株式会社 半導体装置、半導体装置の製造方法、および電子機器
US8896125B2 (en) 2011-07-05 2014-11-25 Sony Corporation Semiconductor device, fabrication method for a semiconductor device and electronic apparatus
US8697493B2 (en) 2011-07-18 2014-04-15 Soitec Bonding surfaces for direct bonding of semiconductor structures
US8441131B2 (en) 2011-09-12 2013-05-14 Globalfoundries Inc. Strain-compensating fill patterns for controlling semiconductor chip package interactions
FR2986904A1 (fr) * 2012-02-14 2013-08-16 St Microelectronics Crolles 2 Systeme d'assemblage de puces
CN103377911B (zh) 2012-04-16 2016-09-21 中国科学院微电子研究所 提高化学机械平坦化工艺均匀性的方法
US9142517B2 (en) 2012-06-05 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding mechanisms for semiconductor wafers
US8772946B2 (en) * 2012-06-08 2014-07-08 Invensas Corporation Reduced stress TSV and interposer structures
US8735219B2 (en) 2012-08-30 2014-05-27 Ziptronix, Inc. Heterogeneous annealing method and device
DE102012224310A1 (de) 2012-12-21 2014-06-26 Tesa Se Gettermaterial enthaltendes Klebeband
US20140175655A1 (en) 2012-12-22 2014-06-26 Industrial Technology Research Institute Chip bonding structure and manufacturing method thereof
US8916448B2 (en) 2013-01-09 2014-12-23 International Business Machines Corporation Metal to metal bonding for stacked (3D) integrated circuits
TWI518991B (zh) 2013-02-08 2016-01-21 Sj Antenna Design Integrated antenna and integrated circuit components of the shielding module
US8946784B2 (en) 2013-02-18 2015-02-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for image sensor packaging
US9105485B2 (en) 2013-03-08 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding structures and methods of forming the same
US9443796B2 (en) 2013-03-15 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Air trench in packages incorporating hybrid bonding
US8802538B1 (en) 2013-03-15 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for hybrid wafer bonding
US9929050B2 (en) 2013-07-16 2018-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming three-dimensional integrated circuit (3DIC) stacking structure
US9723716B2 (en) 2013-09-27 2017-08-01 Infineon Technologies Ag Contact pad structure, an electronic component, and a method for manufacturing a contact pad structure
JP2015115446A (ja) 2013-12-11 2015-06-22 株式会社東芝 半導体装置の製造方法
US9437572B2 (en) 2013-12-18 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive pad structure for hybrid bonding and methods of forming same
US9865523B2 (en) * 2014-01-17 2018-01-09 Taiwan Semiconductor Manufacturing Company, Ltd. Robust through-silicon-via structure
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US9299736B2 (en) 2014-03-28 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding with uniform pattern density
US9230941B2 (en) 2014-03-28 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding structure for stacked semiconductor devices
US9472458B2 (en) 2014-06-04 2016-10-18 Semiconductor Components Industries, Llc Method of reducing residual contamination in singulated semiconductor die
KR102275705B1 (ko) 2014-07-11 2021-07-09 삼성전자주식회사 웨이퍼 대 웨이퍼 접합 구조
US9455182B2 (en) 2014-08-22 2016-09-27 International Business Machines Corporation Interconnect structure with capping layer and barrier layer
US9536848B2 (en) 2014-10-16 2017-01-03 Globalfoundries Inc. Bond pad structure for low temperature flip chip bonding
US9394161B2 (en) 2014-11-14 2016-07-19 Taiwan Semiconductor Manufacturing Co., Ltd. MEMS and CMOS integration with low-temperature bonding
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
US9741620B2 (en) 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
US9656852B2 (en) 2015-07-06 2017-05-23 Taiwan Semiconductor Manufacturing Company Ltd. CMOS-MEMS device structure, bonding mesa structure and associated method
US10075657B2 (en) 2015-07-21 2018-09-11 Fermi Research Alliance, Llc Edgeless large area camera system
US9728521B2 (en) 2015-07-23 2017-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bond using a copper alloy for yield improvement
US9559081B1 (en) 2015-08-21 2017-01-31 Apple Inc. Independent 3D stacking
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US9496239B1 (en) 2015-12-11 2016-11-15 International Business Machines Corporation Nitride-enriched oxide-to-oxide 3D wafer bonding
US9852988B2 (en) 2015-12-18 2017-12-26 Invensas Bonding Technologies, Inc. Increased contact alignment tolerance for direct bonding
US9881882B2 (en) 2016-01-06 2018-01-30 Mediatek Inc. Semiconductor package with three-dimensional antenna
US9923011B2 (en) 2016-01-12 2018-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure with stacked semiconductor dies
US10446532B2 (en) 2016-01-13 2019-10-15 Invensas Bonding Technologies, Inc. Systems and methods for efficient transfer of semiconductor elements
US10636767B2 (en) 2016-02-29 2020-04-28 Invensas Corporation Correction die for wafer/die stack
US10026716B2 (en) 2016-04-15 2018-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC formation with dies bonded to formed RDLs
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
KR102505856B1 (ko) 2016-06-09 2023-03-03 삼성전자 주식회사 웨이퍼 대 웨이퍼 접합 구조체
US9941241B2 (en) 2016-06-30 2018-04-10 International Business Machines Corporation Method for wafer-wafer bonding
US10446487B2 (en) 2016-09-30 2019-10-15 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10163750B2 (en) 2016-12-05 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure for heat dissipation
US10453832B2 (en) 2016-12-15 2019-10-22 Taiwan Semiconductor Manufacturing Co., Ltd. Seal ring structures and methods of forming same
US10002844B1 (en) 2016-12-21 2018-06-19 Invensas Bonding Technologies, Inc. Bonded structures
US20180182665A1 (en) 2016-12-28 2018-06-28 Invensas Bonding Technologies, Inc. Processed Substrate
US10707087B2 (en) 2016-12-28 2020-07-07 Invensas Bonding Technologies, Inc. Processing stacked substrates
US20180190583A1 (en) 2016-12-29 2018-07-05 Invensas Bonding Technologies, Inc. Bonded structures with integrated passive component
KR20190092584A (ko) 2016-12-29 2019-08-07 인벤사스 본딩 테크놀로지스 인코포레이티드 집적된 수동 컴포넌트를 구비한 접합된 구조체
US10276909B2 (en) 2016-12-30 2019-04-30 Invensas Bonding Technologies, Inc. Structure comprising at least a first element bonded to a carrier having a closed metallic channel waveguide formed therein
US10431614B2 (en) 2017-02-01 2019-10-01 Semiconductor Components Industries, Llc Edge seals for semiconductor packages
JP7030825B2 (ja) 2017-02-09 2022-03-07 インヴェンサス ボンディング テクノロジーズ インコーポレイテッド 接合構造物
US10508030B2 (en) 2017-03-21 2019-12-17 Invensas Bonding Technologies, Inc. Seal for microelectronic assembly
JP6640780B2 (ja) 2017-03-22 2020-02-05 キオクシア株式会社 半導体装置の製造方法および半導体装置
WO2018183739A1 (en) 2017-03-31 2018-10-04 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10269756B2 (en) 2017-04-21 2019-04-23 Invensas Bonding Technologies, Inc. Die processing
US10580823B2 (en) 2017-05-03 2020-03-03 United Microelectronics Corp. Wafer level packaging method
US10879212B2 (en) 2017-05-11 2020-12-29 Invensas Bonding Technologies, Inc. Processed stacked dies
US10217720B2 (en) 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11195748B2 (en) 2017-09-27 2021-12-07 Invensas Corporation Interconnect structures and methods for forming same
US11251157B2 (en) 2017-11-01 2022-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Die stack structure with hybrid bonding structure and method of fabricating the same and package
CN107748879A (zh) 2017-11-16 2018-03-02 百度在线网络技术（北京）有限公司 用于获取人脸信息的方法及装置
US10923408B2 (en) 2017-12-22 2021-02-16 Invensas Bonding Technologies, Inc. Cavity packages
US11380597B2 (en) 2017-12-22 2022-07-05 Invensas Bonding Technologies, Inc. Bonded structures
US10727219B2 (en) 2018-02-15 2020-07-28 Invensas Bonding Technologies, Inc. Techniques for processing devices
US11169326B2 (en) 2018-02-26 2021-11-09 Invensas Bonding Technologies, Inc. Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects
US11398258B2 (en) 2018-04-30 2022-07-26 Invensas Llc Multi-die module with low power operation
US11004757B2 (en) 2018-05-14 2021-05-11 Invensas Bonding Technologies, Inc. Bonded structures
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
WO2020010056A1 (en) 2018-07-03 2020-01-09 Invensas Bonding Technologies, Inc. Techniques for joining dissimilar materials in microelectronics
US11462419B2 (en) 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
US11244920B2 (en) 2018-12-18 2022-02-08 Invensas Bonding Technologies, Inc. Method and structures for low temperature device bonding
US11476213B2 (en) 2019-01-14 2022-10-18 Invensas Bonding Technologies, Inc. Bonded structures without intervening adhesive
US11901281B2 (en) 2019-03-11 2024-02-13 Adeia Semiconductor Bonding Technologies Inc. Bonded structures with integrated passive component
US11610846B2 (en) 2019-04-12 2023-03-21 Adeia Semiconductor Bonding Technologies Inc. Protective elements for bonded structures including an obstructive element
US11373963B2 (en) 2019-04-12 2022-06-28 Invensas Bonding Technologies, Inc. Protective elements for bonded structures
US11205625B2 (en) 2019-04-12 2021-12-21 Invensas Bonding Technologies, Inc. Wafer-level bonding of obstructive elements
US11385278B2 (en) 2019-05-23 2022-07-12 Invensas Bonding Technologies, Inc. Security circuitry for bonded structures
US20200395321A1 (en) 2019-06-12 2020-12-17 Invensas Bonding Technologies, Inc. Sealed bonded structures and methods for forming the same
US20210098412A1 (en) 2019-09-26 2021-04-01 Invensas Bonding Technologies, Inc. Direct gang bonding methods and structures
US11762200B2 (en) 2019-12-17 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded optical devices
KR20220120631A (ko) 2019-12-23 2022-08-30 인벤사스 본딩 테크놀로지스 인코포레이티드 결합형 구조체를 위한 전기적 리던던시
US11721653B2 (en) 2019-12-23 2023-08-08 Adeia Semiconductor Bonding Technologies Inc. Circuitry for electrical redundancy in bonded structures
US20210242152A1 (en) 2020-02-05 2021-08-05 Invensas Bonding Technologies, Inc. Selective alteration of interconnect pads for direct bonding
CN115943489A (zh) 2020-03-19 2023-04-07 隔热半导体粘合技术公司 用于直接键合结构的尺寸补偿控制

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040056361A1 (en) * 2000-03-21 2004-03-25 Mcteer Allen Multi-layered copper bond pad for an integrated circuit
US20030113976A1 (en) * 2001-12-17 2003-06-19 Stefan Hau-Riege Wafer-bonding using solder and method of making the same
US20060024950A1 (en) * 2004-08-02 2006-02-02 Suk-Hun Choi Methods of forming metal contact structures and methods of fabricating phase-change memory devices using the same
US20070212870A1 (en) * 2006-03-13 2007-09-13 International Business Machines Corporation Interconnect structure with a barrier-redundancy feature
KR100850212B1 (ko) * 2007-04-20 2008-08-04 삼성전자주식회사 균일한 무전해 도금 두께를 얻을 수 있는 반도체 소자의제조방법
JP2012019148A (ja) * 2010-07-09 2012-01-26 Canon Inc 固体撮像装置用の部材および固体撮像装置の製造方法
US20130221527A1 (en) * 2012-02-24 2013-08-29 International Business Machines Corporation Metallic capped interconnect structure with high electromigration resistance and low resistivity
US20130285248A1 (en) * 2012-04-26 2013-10-31 Asia Pacific Microsystems, Inc. Package Structure and Substrate Bonding Method
US20130320556A1 (en) * 2012-06-05 2013-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. Three Dimensional Integrated Circuit Structures and Hybrid Bonding Methods for Semiconductor Wafers
US20140353828A1 (en) * 2013-05-30 2014-12-04 International Business Machines Corporation Substrate bonding with diffusion barrier structures
US20150108644A1 (en) * 2013-10-17 2015-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. 3D Integrated Circuit and Methods of Forming the Same
CN104576518A (zh) * 2013-10-23 2015-04-29 格罗方德半导体公司 用于后段制程金属化的混合型锰和氮化锰阻障物及其制法

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108447839B (zh) * 2017-02-16 2020-01-10 南亚科技股份有限公司 半导体装置及其制造方法
US10825794B2 (en) 2017-02-16 2020-11-03 Nanya Technology Corporation Method for preparing a semiconductor apparatus
US10923455B2 (en) 2017-02-16 2021-02-16 Nanya Technology Corporation Semiconductor apparatus and method for preparing the same
CN108447839A (zh) * 2017-02-16 2018-08-24 南亚科技股份有限公司 半导体装置及其制造方法
CN112534574A (zh) * 2018-06-13 2021-03-19 伊文萨思粘合技术公司 Tsv之上的大金属焊盘
CN112585740A (zh) * 2018-06-13 2021-03-30 伊文萨思粘合技术公司 作为焊盘的tsv
CN112771656A (zh) * 2018-08-29 2021-05-07 伊文萨思粘合技术公司 通过在直接键合工艺期间捕获污染物并阻止裂纹来增强微电子结构中的键合
CN112956011A (zh) * 2018-08-31 2021-06-11 伊文萨思粘合技术公司 微电子学中在低温下进行直接金属间键合的层结构
CN112956011B (zh) * 2018-08-31 2022-07-26 伊文萨思粘合技术公司 微电子学中在低温下进行直接金属间键合的层结构
CN112106176A (zh) * 2018-12-04 2020-12-18 索尼半导体解决方案公司 半导体装置和电子设备
CN113169159A (zh) * 2018-12-06 2021-07-23 伊文萨思公司 用于微电子器件的直接接合的界面中的电容性耦合
CN113348555A (zh) * 2019-03-18 2021-09-03 铠侠股份有限公司 半导体装置及其制造方法
CN113348555B (zh) * 2019-03-18 2023-08-18 铠侠股份有限公司 半导体装置及其制造方法
CN110945650A (zh) * 2019-11-05 2020-03-31 长江存储科技有限责任公司 具有通过键合而形成的毗连通孔结构的半导体设备和用于形成其的方法
TWI759678B (zh) * 2019-11-05 2022-04-01 大陸商長江存儲科技有限責任公司 半導體裝置、三維記憶體裝置和用於形成半導體結構的方法
US11424208B2 (en) 2019-11-05 2022-08-23 Yangtze Memory Technologies Co., Ltd. Semiconductor devices having adjoined via structures formed by bonding and methods for forming the same
US11887954B2 (en) 2019-11-05 2024-01-30 Yangtze Memory Technologies Co., Ltd. Semiconductor devices having adjoined via structures formed by bonding and methods for forming the same
WO2022000385A1 (zh) * 2020-07-01 2022-01-06 重庆康佳光电技术研究院有限公司 显示面板的制作方法、显示面板及显示装置
US12040431B2 (en) 2020-07-01 2024-07-16 Chongqing Konka Photoelectric Technology Research Institute Co., Ltd. Method for manufacturing display panel, display panel, and display apparatus
CN113380640A (zh) * 2020-08-17 2021-09-10 长江存储科技有限责任公司 半导体封装结构及其制造方法
CN111933533B (zh) * 2020-08-17 2021-06-04 长江存储科技有限责任公司 半导体封装结构及其制造方法
CN113380640B (zh) * 2020-08-17 2024-07-02 长江存储科技有限责任公司 半导体封装结构及其制造方法
CN113035729A (zh) * 2021-03-10 2021-06-25 联合微电子中心有限责任公司 混合键合方法及键合用衬底
WO2023272903A1 (zh) * 2021-07-01 2023-01-05 长鑫存储技术有限公司 一种半导体结构及其形成方法
US11973045B2 (en) 2021-07-01 2024-04-30 Changxin Memory Technologies, Inc. Semiconductor structure and method for forming same

Also Published As

Publication number Publication date
US20190237419A1 (en) 2019-08-01
US20220254746A1 (en) 2022-08-11
KR102659849B1 (ko) 2024-04-22
JP2018528622A (ja) 2018-09-27
US20170062366A1 (en) 2017-03-02
EP3341956A4 (en) 2019-03-06
US9953941B2 (en) 2018-04-24
TWI702659B (zh) 2020-08-21
US20180226371A1 (en) 2018-08-09
US11264345B2 (en) 2022-03-01
CN114944376A (zh) 2022-08-26
KR20180034671A (ko) 2018-04-04
KR20220083859A (ko) 2022-06-20
JP6743149B2 (ja) 2020-08-19
US20240243085A1 (en) 2024-07-18
US11830838B2 (en) 2023-11-28
WO2017035321A1 (en) 2017-03-02
KR102408487B1 (ko) 2022-06-13
US10262963B2 (en) 2019-04-16
EP3341956A1 (en) 2018-07-04
CN108140559B (zh) 2022-05-24
TW201715620A (zh) 2017-05-01

Similar Documents

Publication Publication Date Title
CN108140559A (zh) 传导阻障直接混合型接合
CN102237338B (zh) 具有改进连接的基板通孔
CN102832165B (zh) 经过改进的用于双镶嵌工艺的间隙填充方法
CN103548120B (zh) 最优化环形穿透基板通路
CN102074545B (zh) 集成电路元件、半导体元件以及半导体工艺
CN102446830B (zh) 形成低成本的tsv
TWI451544B (zh) 平坦化矽貫孔之方法
CN102420210A (zh) 具有硅通孔(tsv)的器件及其形成方法
US10886169B2 (en) Airgap formation in BEOL interconnect structure using sidewall image transfer
TW201025501A (en) Method of manufacturing through-silicon-via and through-silicon-via structure
CN101924096A (zh) 硅通孔结构及其形成工艺
CN101789390A (zh) 硅导通孔的制造方法与硅导通孔结构
CN107591389A (zh) 内牺牲间隔件的互连
US20170330820A1 (en) Method for fabrication semiconductor device
TWI697969B (zh) 具有混合金屬化之互連
TWI648838B (zh) 被金屬覆蓋層覆蓋的鈷互連
CN108807340B (zh) 用于互连开口的衬垫取代
TWI707401B (zh) 基本原則區域中完全對準介層窗
CN102437100A (zh) 一种使用双大马士革工艺同时形成铜接触孔和第一层金属的方法
US10283372B2 (en) Interconnects formed by a metal replacement process

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CP01 Change in the name or title of a patent holder

Address after: California, USA

Patentee after: Edya Semiconductor Bonding Technology Co.,Ltd.

Address before: California, USA

Patentee before: INVENSAS BONDING TECHNOLOGIES, Inc.

CP01 Change in the name or title of a patent holder