CN102420210A - 具有硅通孔(tsv)的器件及其形成方法 - Google Patents
具有硅通孔(tsv)的器件及其形成方法 Download PDFInfo
- Publication number
- CN102420210A CN102420210A CN2011102183037A CN201110218303A CN102420210A CN 102420210 A CN102420210 A CN 102420210A CN 2011102183037 A CN2011102183037 A CN 2011102183037A CN 201110218303 A CN201110218303 A CN 201110218303A CN 102420210 A CN102420210 A CN 102420210A
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- Prior art keywords
- insulating barrier
- silicon substrate
- tsv
- layer
- interface
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
具有硅通孔(TSV)的器件及其形成方法包括:在硅衬底中形成开口,在开口的侧壁和底部上形成第一绝缘层,在开口的侧壁和底部上形成第二绝缘层。第一绝缘层和硅衬底之间的第一界面具有小于5nm的峰谷高度的界面粗糙度。第二绝缘层和导电层之间的第二界面具有小于5nm的峰谷高度的界面粗糙度。
Description
技术领域
本发明涉及集成电路制造,更具体地,涉及硅通孔(TSV)制造。
背景技术
通过对高速、高密度、小尺寸和多功能电子器件的强烈需要而驱动了三维***封装(3D-SiP)技术。硅通孔(TSV)互连由于其较短的互连距离和较快的速度而作为3D集成的一种形式。为了解决对倒装封装技术的需求,具有TSV的硅(Si)内插器已经由于从芯片到衬底的短互连而作为提供高写入密度互连、使管芯和内插器之间的热膨胀(CTE)失配的系数最小化、以及提高电子性能的良好解决方法。在TSV工艺中涉及多个步骤,可以成功地解决封装技术的限制,包括通孔形成、侧壁绝缘、通孔填充、晶片减薄和/或晶片/管芯堆叠。TSV通过还用于确定TSV寄生电容的TSV侧壁绝缘来与衬底和其他TSV连接电隔离。为了确保具有高击穿电压、无泄漏和无裂化(cracking)的预期绝缘性能,TSV侧壁绝缘需要良好的覆盖和均匀性、低应力、以及工艺兼容性。然而,传统的硅上通孔蚀刻工艺、通孔侧壁表现出由许多微凹面组成的扇贝状,其可以根据工艺参数而改变尺寸。硅中的一系列蚀刻“扇贝(scallop)”引起了不平坦的层/电介质层以及导体填充通孔的空隙。侧壁绝缘粗糙度是TSV工艺中的一项挑战瓶颈。
发明内容
为解决上述问题,本发明提出了一种器件,包括:硅衬底;硅通孔(TSV)结构,穿透硅衬底;以及绝缘结构,形成在硅衬底和TSV结构之间,其中,在绝缘结构和硅衬底之间的第一界面具有小于5nm的峰谷高度的界面粗糙度,以及绝缘结构和TSV结构之间的第二界面具有小于5nm的峰谷高度的界面粗糙度。
其中,绝缘结构包括与硅衬底相邻的第一绝缘层以及与TSV结构相邻的第二绝缘层。
其中,第二绝缘层的各向同性蚀刻率大于第一绝缘层的各向同性蚀刻率。
其中,第一绝缘层和第二绝缘层之间的第三界面具有大于10nm的峰谷高度的界面粗糙度。
其中,第一绝缘层是氧化物层,第二绝缘层是氧化物层。
其中,TSV结构包括铜层。
其中,TSV结构包括环绕铜层的扩散阻挡层。
该器件还包括:第一管芯,电连接至硅衬底的第一侧。
该器件还包括:第二管芯,电连接至硅衬底的第二侧,第二侧与硅衬底的第一侧相对。
此外,本发明还提出了一种方法,包括:形成开口,开口从硅衬底的顶表面延伸到硅衬底中预定深度;沿着开口的侧壁和底部在硅衬底上形成绝缘结构;在绝缘结构上形成导电层,以填充开口;其中,在绝缘结构和硅衬底之间的第一界面具有小于5nm的峰谷高度的界面粗糙度,以及绝缘结构和导电层之间的第二界面具有小于5nm的峰谷高度的界面粗糙度。
其中,形成绝缘结构包括:执行第一沉积工艺,以形成与硅衬底相邻的第一绝缘层;以及执行第二沉积工艺,以形成与导电层相邻的第二绝缘层;其中,第二沉积工艺不同于第一沉积工艺。
其中,第一沉积工艺为热氧化工艺。
其中,第二沉积工艺包括次常压化学汽相沉积(SACVD)工艺、等离子体增强型化学汽相沉积(PECVD)工艺和等离子体增强型原子层沉积(PEALD)工艺中的至少一种。
其中,第二绝缘层的各向同性蚀刻率大于第一绝缘层的各向同性蚀刻率。
其中,第一沉积工艺包括次常压化学汽相沉积(SACVD)工艺、等离子体增强型化学汽相沉积(PECVD)工艺和等离子体增强型原子层沉积(PEALD)工艺中的至少一种。
其中,第二沉积工艺为热氧化工艺。
其中,第一沉积工艺形成与硅衬底相邻的第一氧化物层,以及第二沉积工艺形成与导电层相邻的第二氧化物层。
其中,在绝缘结构上形成导电层的步骤是形成铜层。
其中,导电层包括在铜层下方的扩散阻挡层。
该方法还包括:形成电连接至在硅衬底中形成的导电层的集成电路管芯。
附图说明
图1是示出根据实施例的3D集成电路(3D-IC)器件的截面图;
图2A是根据实施例的形成在图1所示第一衬底中的互连结构的截面图;
图2B是根据实施例的形成在图1所示第一衬底中的互连结构的截面图;
图3是用于制造根据本公开各个方面的TSV结构的方法的流程图;
图4A至图4E是根据图2A的互连结构以及图3的方法的实施例的处于各个制造阶段的部分晶片的截面图;以及
图5A至图5D是根据图2B的互连结构以及图3的方法的实施例的处于各个制造阶段的部分晶片的截面图。
具体实施方式
本公开提供了具有侧壁绝缘的TSV及其形成工艺的实施例。具有侧壁绝缘的TSV可以在晶片、集成电路管芯、内插器或衬底上制造,应用于倒装组件、晶片级芯片规模封装(WLCSP)、三维集成电路(3D-IC)堆叠和/或任何先进的封装技术领域。现在将详细描述附图中所示的示例性实施例。在可能的情况下,在图中和描述中使用相同的参考标号以代表相同或类似的部件。在附图中,形状和厚度可以为清晰和便利而夸大。该描述具体针对形成根据本公开的装置的一部分的元件或者与根据本公开的装置直接协作的元件。应该理解,没有具体示出或描述的元件可以采用本领域已知的任何形式。此外,当层被描述为在另一层上或在衬底“上”时,其可以直接在另一层或衬底上,或者还可以存在中间层。该说明书中的“一个实施例”或“实施例”意味着参照该实施例描述的具体部件、结构或特性包括在至少一个实施例中。因此,该说明书中的各个地方出现的短语“在一个实施例中”或“在实施例中”不是必须都是指相同的实施例。此外,可以在一个或多个实施例中以任何适当的方式组合特定的部件、结构或特性。应该理解,以下附图没有按比例绘制,这些附图仅仅是为了示意性的目的。
图1是根据实施例的3D-IC器件的截面图。第一衬底100设置有多个形成在其中的互连结构10。在一个实施例中,第一衬底100是硅衬底,并且互连结构10是TSV(硅通孔)结构10。硅衬底可以为内插器或集成电路管芯。第一管芯200结合至第一衬底100的第一侧,以及第二管芯300结合至第一衬底100的第二侧,形成3D-IC堆叠。因此,第一管芯200通过至少一个TSV结构10电连接至第二管芯300。第一管芯200和第二管芯300可以为用于特定应用的任何适当的集成电路。第一管芯200和第二管芯300中的一个为存储芯片、逻辑电路芯片或控制器芯片,例如,闪存芯片、PRAM芯片、MRAM芯片、SRAM芯片、DRAM芯片、微处理器、数字信号处理器和/或微控制器。第一衬底100通过导电突起102电连接至第二衬底400。底部填充材料104形成在各种部件(例如,第一管芯200、第二管芯300、第一衬底100和第二衬底400)之间。诸如顶部绝缘材料(TIM)的密封剂500还可以形成在部件的上方,以保护部件免受环境和外部污染物的影响。还可以形成附加外模,以完全密封一些部件。
图2A示出了根据实施例的形成在图1所示第一衬底中的互连结构的截面图。互连结构是形成在硅衬底100中的TSV结构10A,用于贯通硅衬底100的前表面100a和后表面100b。TSV结构10A包括导电层20和环绕导电层20的阻挡层18。在TSV结构10A和衬底10之间形成侧壁绝缘结构16,以使TSV结构10A与其他连接隔离。在第一侧壁绝缘结构16和硅衬底100之间存在第一界面11,以及在侧壁绝缘结构16和TSV结构10A之间存在第二界面15。第一界面11具有第一界面粗糙度,其具有小于5nm的峰谷高度。第二界面15具有第二界面粗糙度,其具有小于5nm的峰谷高度。具有平滑表面的侧壁绝缘结构16可以实现环绕TSV结构10A的均匀绝缘厚度。在一个实施例中,侧壁绝缘结构16具有从50nm到5um的厚度。可以控制侧壁绝缘结构16的厚度,以优化TSV的诸如电容和电阻的电特性。在一些实施例中,具有平滑表面和均匀厚度的侧壁绝缘结构16减少了由扇贝或粗糙界面所引起的硅破裂或层破裂。这增加了TSV金属化步骤中的工艺可靠性。减轻了由绝缘膜质量和阶梯覆盖之间的折中以及蚀刻产量和界面粗糙度之间的折中所引起的难度。
在一个实施例中,侧壁绝缘结构16包括与硅衬底100相邻的第一绝缘层12以及与TSV结构10A相邻的第二绝缘层14。第一界面11在第一绝缘层12和硅衬底100之间。第二界面15在第二绝缘层14和TSV结构10A之间。第一绝缘层12和第二绝缘层14通过使用不同的沉积方法由氧化物层形成。在一些实施例中,使用热氧化工艺执行第一绝缘层12的沉积。在一些实施例中,使用多种技术(包括SACVD(次常压化学汽相沉积)、PECVD(等离子体增强化学汽相沉积)、PEALD(等离子体增强原子层沉积)和未来显影沉积工艺)中的任何一种来执行第二绝缘层14的沉积。因此,第一绝缘层12和第二绝缘层14具有不同的膜特性,诸如相同溶液中的不同的各向同性蚀刻率。在一个实施例中,使用处于室温的稀释氢氟酸(DHF)溶液,第二绝缘层14的各向同性蚀刻率大于第一绝缘层12的各向同性蚀刻率。例如,使用50∶1的DHF溶液,热氧化物膜的蚀刻率大约为SACVD氧化物膜的蚀刻率大约为SACVD氧化物膜和热氧化物膜之间的湿蚀刻选择性可以根据SACVD工艺控制而大于约6。可以使用这种DHF蚀刻溶液在第一绝缘层12和第二绝缘层14之间观察到第三界面13的粗糙度。第三界面13具有第三界面粗糙度,其具有大于10nm的峰谷高度,例如从10nm到1000nm以上。
图2B示出了根据另一实施例的形成在图1所示第一衬底中的互连结构的截面图。将省略与图2A的描述相同或相似的部分的解释。示出了形成在硅衬底100中的TSV结构10B,用于贯通硅衬底100的前表面100a和后表面100b。TSV结构10B包括导电层20和环绕导电层20的阻挡层18。在TSV结构10B和衬底10之间形成侧壁绝缘结构26,以使TSV结构10B与其他连接隔离。在第一侧壁绝缘结构26和硅衬底100之间存在第一界面21,以及在第一侧壁绝缘结构26和TSV结构10B之间存在第二界面25。第一界面21具有第一界面粗糙度,其具有小于5nm的峰谷高度。第二界面25具有第二界面粗糙度,其具有小于5nm的峰谷高度。具有平滑表面的侧壁绝缘结构26可以实现环绕TSV结构10B的均匀绝缘厚度。在一个实施例中,侧壁绝缘结构26具有从50nm到5um的厚度。具有平滑表面和均匀厚度的侧壁绝缘结构26可以减少由扇贝或粗糙界面所引起的硅破裂或层破裂。这可以增加TSV金属化步骤中的工艺可靠性。可以解决由绝缘膜质量和阶梯覆盖之间的折中以及蚀刻产量和界面粗糙度之间的折中所导致的难度。
在一个实施例中,侧壁绝缘结构26包括与硅衬底100相邻的第一绝缘层22以及与TSV结构10B相邻的第二绝缘层24。第一界面21存在于第一绝缘层22和硅衬底100之间。第二界面25存在于第二绝缘层24和TSV结构10B之间。第一绝缘层22和第二绝缘层24通过使用不同的沉积方法由氧化物层形成。在一些实施例中,使用多种技术(包括SACVD(次常压化学汽相沉积)、PECVD(等离子体增强化学汽相沉积)、PEALD(等离子体增强原子层沉积)和未来显影沉积工艺)中的任何一种来执行第一绝缘层22的沉积。在一些实施例中,使用热氧化工艺执行第二绝缘层24的沉积。在第二绝缘层24的沉积期间,热氧化工艺中的高温循环可以提高第一绝缘层22的膜特性,以使得两层22和24具有类似的膜特性,诸如相同溶液中的类似的各向同性蚀刻率。因此,消除了第一绝缘层22和第二绝缘层24之间的第三界面23(示为虚线)。在一些实施例中,两个绝缘层22和24变为一个热氧化物膜,并且难以使用例如DHF蚀刻溶液观察到第三界面23。
图3是用于制造根据本公开各个方面的TSV结构的方法的流程图。方法600开始于块610,其中,在硅衬底中形成TSV开口。方法600继续到块620,其中,通过第一沉积工艺在TSV开口中形成第一绝缘层。在硅衬底上形成第一绝缘层,以对TSV开口的底部和侧壁加衬(line)。在一些实施例中,第一绝缘层为氧化物层,并且使用多种技术(包括热氧化工艺、SACVD、PECVD、PEALD和未来显影沉积工艺)中的任何一种来执行第一沉积工艺。方法600继续到块630,其中,通过第二沉积工艺在TSV开口中形成第二绝缘层。在一些实施例中,第二绝缘层为氧化物层,并且使用多种技术(包括热氧化工艺、SACVD、PECVD、PEALD和未来显影沉积工艺)中的任何一种来执行第二沉积工艺。第二沉积工艺不同于第一沉积工艺。方法继续到块640,其中,在TSV开口中形成导电层。形成导电层以填充TSV开口。
图4A至图4E是根据图2A的互连结构以及图3的方法的实施例的处于各个制造阶段的部分晶片的截面图。
图4A是包括衬底100的晶片2的截面图。衬底100具有前表面100a和后表面100b。衬底100可以由半导体材料形成,诸如硅、锗化硅、碳化硅、砷化镓或其他半导体材料。可选地,衬底100由诸如氧化硅等的电介质材料形成。在一个实施例中,衬底100通常为硅(Si),例如具有或不具有外延层的硅衬底或者包含埋入绝缘层的绝缘体上硅衬底。贯穿整个描述,衬底100以及上覆和在下互连结构组合被称为内插器晶片,其基本上不具有集成电路器件,包括诸如晶体管和二极管的有源器件。此外,内插器晶片可以包括或者可以不包括诸如电容器、电阻器、电感器、变容二极管等的无源器件。
工艺前进到在衬底100中形成开口30,其具有大于约5的高纵横比。在形成TSV结构的实施例中,开口30是其中将执行金属化工艺的TSV开口。在限定TSV开口的过程中,在衬底100上方形成硬掩模层32,随后在其上形成图样化光刻胶层。硬掩模层32可以为氮化硅层、氮氧化硅层等。通过本领域已知的曝光、烘烤、显影和/或其他光刻工艺对光刻胶层(未示出)进行图样化,以提供露出硬掩模层32的开口。然后,将图样化的光刻胶层作为掩模元件,通过湿蚀刻或干蚀刻工艺来蚀刻露出的硬掩模层32,以提供开口。使用硬掩模层32和图样化的光刻胶层作为掩模元件,执行蚀刻工艺以蚀刻露出的衬底100,形成具有侧壁30a和底部30b的TSV开口30,穿透衬底100的至少一部分。可使用任何适当的蚀刻方法(例如,等离子体蚀刻、化学湿蚀刻、激光钻和/或本领域已知的其他工艺)来蚀刻TSV开口30。在一个实施例中,蚀刻工艺包括深反应离子蚀刻(RIE)工艺,以蚀刻衬底100。蚀刻工艺可以为使得TSV开口30从前表面100a蚀刻到达大约几十微米到几百微米的深度,而不穿透后表面100b。蚀刻工艺可以在与TSV开口30的侧壁30a相邻的硅衬底100上导致一系列蚀刻的微扇贝(macro scallop)。可以在随后工艺中平滑微扇贝(micro scallop)侧壁。在一个实施例中,TSV开口30具有大约从20至100μm的深度以及大约从1.5至10μm的尺寸。TSV开口30具有在大约5和大约10之间的高纵横比。在一些实施例中,TSV开口30的纵横比大于10。在硅衬底100中形成具有高纵横比的TSV开口30的过程中,可以在硅衬底100的侧壁30a上形成一系列蚀刻的微扇贝(未示出),其可以根据工艺参数而改变尺寸。在随后的热氧化工艺中平滑微扇贝侧壁。
现在,参照图4B,工艺前进到在硅衬底100上形成第一绝缘层12,以覆盖硬掩模层32,并对TSV开口30的侧壁30a和底部30b加衬。在一个实施例中,第一绝缘层12是通过高温热氧化工艺生长的热氧化物层。在一些实施例中,热氧化物层为氧化硅(SiOx)。热氧化物层在整个衬底表面上生长,并且还在TSV开口30的侧壁30a和底部30b上生长,使得热氧化物层平滑最初蚀刻的开口30的粗糙侧壁。因此,平滑第一绝缘层12和邻近侧壁30a的硅衬底100之间的界面11,以实现小于5nm的峰谷高度的粗糙度。与界面11相比,第一绝缘层12的内表面13a相对粗糙,其具有大于10nm的峰谷高度的表面粗糙度。可以控制第一绝缘层12的厚度,以优化TSV的诸如电容和电感的电特性。
现在,参照图4C,工艺前进到在硅衬底100上形成第二绝缘层14,其可以形成在第一绝缘层12上。在一个实施例中,第二绝缘层14是通过SACVD工艺形成的氧化物层。SACVD氧化物层沿着TSV开口30的侧壁30a和底部30b沉积在第一绝缘层12的整个表面上。在PECVD单晶片室中执行SACVD工艺,该PECVD单晶片室被机械地改变以安全地处理高室压。工艺是在没有等离子体的情况下运行的,并且在100至600torr的压力范围内使用TEOS(四乙基邻位硅酸盐)和Ozone(O3)的混合物。由于SACVD沉积期间的生长特性,第二绝缘层14具有外表面15a,其具有小于5nm的峰谷高度的表面粗糙度。与外表面15a相比,第一绝缘层12和第二绝缘层14之间的界面13相对粗糙,其具有大于10nm的峰谷高度的界面粗糙度。在一些实施例中,第二绝缘层14是通过PECVD、PEALD或未来显影沉积工艺所形成的氧化物层,以实现具有小于5nm的峰谷高度的平滑表面。可以控制第二绝缘层14的厚度,以优化TSV的诸如电容和电感的电特性。
现在,参照图4D,工艺前进到用于填充TSV开口30的金属化工艺。一些实施例提供了在形成TSV的过程中使用铜金属化以及使用铜电镀技术来填充高纵横比开口,以避免接缝或虚缺陷。如本公开所采用的,铜(Cu)想要包围基本上显示出Cu的电特性的基础Cu以及基于Cu的合金。为了避免金属从TSV金属扩散到硅衬底,在绝缘层和TSV金属之间使用阻挡层。
在第二绝缘层14上形成阻挡层18,对TSV开口30加衬。阻挡层18用作扩散阻挡以防止金属扩散,以及用作金属和电介质之间的粘合层。难熔金属、难熔金属-氮化物、难熔金属-硅-氮化物以及它们的组合通常被用于阻挡层18。例如,可以使用TaN、Ta、Ti、TiN、TiSiN、WN或它们的组合。在一些实施例中,阻挡层18包括TaN层和Ta层。在一些实施例中,阻挡层18为TiN层。在一些实施例中,阻挡层18为Ti层。
然后,在阻挡层18上形成金属晶种层(未示出)。在一些实施例中,金属晶种层为可通过物理汽相沉积形成的铜晶种层。可以使用形成铜晶种层的其他方法,诸如本领域已知的CVD。然后,晶片2被转印到电镀工具(诸如电化学电镀(ECP)工具),并且通过电镀工艺在晶片2上镀上导电层20以填充TSV开口30。虽然本文描述了ECP工艺,但实施例不限于ECP沉积金属。导电层20可包括选自包含但不限于铜和基于铜的合金的导电材料组中的低阻导电材料。可选地,导电层可包括各种材料,诸如钨、铝、金、银等。在一个实施例中,导电层20为形成在铜晶种层上方的包含铜的层。阻挡层18和第二绝缘层14之间的界面15被平滑,以具有小于5nm的峰谷高度的界面粗糙度。
随后,如图4E所示,通过蚀刻、化学机械抛光(CMP)等,去除TSV开口30外部的导电层20、金属晶种层、阻挡层18、第二绝缘层14、第一绝缘层12和/或硬掩模层32的多余部分,形成基本上与衬底100的上表面共面的金属填充开口的上表面。TSV开口30中的导电层20和阻挡层18的剩余部分形成TSV结构10A。TSV开口30中第二绝缘层14和第一绝缘层12的剩余部分变为侧壁绝缘结构16,其夹置在TSV结构10A和硅衬底100之间。
接下来,晶片2经受后段制程(BEOL,back-end-of-line)互连工艺、晶片减薄工艺和背侧金属化工艺。管芯200和300可通过倒装结合来结合至硅衬底100。在切割之后,堆叠管芯例如通过各向异性导电连接膜被安装到IC卡上。
图5A至图5D是根据图2B的互连结构以及图3的方法的实施例的处于各个制造阶段的部分晶片的截面图。本文将省略对与图4A至图4E中相同或相似部分的描述。
图5A是包括衬底100的晶片2的截面图。硅衬底100具有前表面100a和后表面100b。工艺前进到通过使用硬掩模层32和湿蚀刻或干蚀刻工艺在硅衬底100中形成TSV开口30,其具有大于约5的纵横比。可以在与TSV开口30的侧壁30a相邻的硅衬底100上形成一系列蚀刻的微扇贝。可以在随后的热氧化工艺中平滑微扇贝侧壁。工艺前进到在硅衬底100上形成第一绝缘层22,以覆盖硬掩模层32并对TSV开口30的侧壁30a和底部30b加衬。在一个实施例中,第一绝缘层12是通过SACVD工艺形成的氧化物层。沿着TSV开口30的侧壁30a和底部30b在整个硅表面上沉积SACVD氧化物层。由于SACVD沉积期间的独特生长特性,第一绝缘层22可具有被平滑以实现具有小于5nm的峰谷高度的表面粗糙度的外表面23a。与外表面23a相比,第一绝缘层22与侧壁30a相邻的硅衬底100之间的界面21相对粗糙,其具有大于10nm的峰谷高度的界面粗糙度。在一些实施例中,第一绝缘层22是通过PECVD、PEALD或未来显影沉积工艺所形成的氧化物层,以实现具有小于5nm的峰谷高度的平滑表面。在一些实施例中,可以控制第一绝缘层22的厚度,以优化TSV的诸如电容和电感的电特性。
现在,参照图5B,工艺前进到在硅衬底100上形成第二绝缘层24,其形成在第一绝缘层22上或下。在一个实施例中,第二绝缘层24是通过高温热氧化工艺生长的热氧化物层。在一些实施例中,热氧化物层为氧化硅(SiOx)。热氧化物层具有被平滑以实现小于5nm的峰谷高度的表面粗糙度的外表面25a。热氧化物层沿着TSV开口30的侧壁30a和底部30b在第一绝缘层22的整个表面23a上生长,使得热氧化工艺中的高温循环可以提高第一绝缘层22的膜特性,以使两层22和24具有类似的膜特性,例如,相同湿蚀刻溶液中的各向同性的蚀刻率。因此,消除了称为第一绝缘层22和第二绝缘层24之间的界面23(示为虚线)的粗糙面23a。两层22和24形成绝缘结构26,并且难以在其中观察到界面23。在一些实施例中,两个绝缘层22和24变成一个热氧化物膜。可以控制第二绝缘层24的厚度,以优化TSV的诸如电容和电感的电特性。
现在,参照图5C,工艺前进到用于填充TSV开口30的金属化工艺。在第二绝缘层24上形成阻挡层18,对TSV开口30加衬。阻挡层18用作扩散阻挡,以防止金属扩散,以及用作金属和电介质之间和粘合层。难熔金属、难熔金属-氮化物、难熔金属-硅-氮化物以及它们的组合通常被用于阻挡层18。例如,可以使用TaN、Ta、Ti、TiN、TiSiN、WN或它们的组合。在一些实施例中,阻挡层18包括TaN层和Ta层。在一些实施例中,阻挡层18为TiN层。在一些实施例中,阻挡层18为Ti层。然后,在阻挡层18上形成金属晶种层(未示出)。在一些实施例中,金属晶种层为可通过物理汽相沉积形成的铜晶种层。可以使用形成铜晶种层的其他方法,诸如本领域已知的CVD。然后,晶片2被转印到电镀工具(诸如电化学电镀(ECP)工具),并且通过电镀工艺在晶片2上镀上导电层20以填充TSV开口30。虽然本文描述了ECP工艺,但实施例不限于ECP沉积金属。在一些实施例中,导电层20包括选自包含但不限于铜和基于铜的合金的导电材料组中的低阻导电材料。可选地,导电层可包括各种材料,诸如钨、铝、金、银等。在一个实施例中,导电层20为形成在铜晶种层上方的包含铜的层。
随后,如图5D所示,通过蚀刻、化学机械抛光(CMP)等,去除TSV开口30外部的导电层20、金属晶种层、阻挡层18、第二绝缘层24、第一绝缘层22和/或硬掩模层32的多余部分,形成基本上与衬底100的上表面共面的金属填充开口的上表面。TSV开口30中的导电层20和阻挡层18的剩余部分形成TSV结构10B。TSV开口30中第二绝缘层24和第一绝缘层22的剩余部分变为侧壁绝缘结构26,其夹置在TSV结构10B和硅衬底100之间。
接下来,晶片2经受后段制程(BEOL)互连工艺、晶片减薄工艺和背侧金属化工艺。管芯200和300可通过倒装结合来结合至硅衬底100。在切割之后,堆叠管芯例如通过各向异性导电连接膜被安装到IC卡上。
在前面详细的描述中,参照其示例性实施例描述了本公开。然而,明显地,在不背离本公开的精神和范围的情况下,可以进行各种修改、结构。工艺和变化。因此,说明书和附图被认为是示例性且不具有限制性。应该理解,本公开能够使用各种其他组合和条件,并且能够在本发明的发明概念的范围内进行改变或修改。
Claims (10)
1.一种器件,包括:
硅衬底;
硅通孔(TSV)结构,穿透所述硅衬底;以及
绝缘结构,形成在所述硅衬底和所述TSV结构之间,
其中,在所述绝缘结构和所述硅衬底之间的第一界面具有小于5nm的峰谷高度的界面粗糙度,以及所述绝缘结构和所述TSV结构之间的第二界面具有小于5nm的峰谷高度的界面粗糙度。
2.根据权利要求1所述的器件,其中,所述绝缘结构包括与所述硅衬底相邻的第一绝缘层以及与所述TSV结构相邻的第二绝缘层。
3.根据权利要求2所述的器件,其中,所述第二绝缘层的各向同性蚀刻率大于所述第一绝缘层的各向同性蚀刻率。
4.根据权利要求2所述的器件,其中,所述第一绝缘层和所述第二绝缘层之间的第三界面具有大于10nm的峰谷高度的界面粗糙度。
5.根据权利要求2所述的器件,其中,所述第一绝缘层是氧化物层,所述第二绝缘层是氧化物层。
6.根据权利要求1所述的器件,其中,所述TSV结构包括铜层。
7.根据权利要求6所述的器件,其中,所述TSV结构包括环绕所述铜层的扩散阻挡层。
8.根据权利要求1所述的器件,还包括:第一管芯,电连接至所述硅衬底的第一侧。
9.根据权利要求8所述的器件,还包括:第二管芯,电连接至所述硅衬底的第二侧,所述第二侧与所述硅衬底的第一侧相对。
10.一种方法,包括:
形成开口,所述开口从硅衬底的顶表面延伸到所述硅衬底中预定深度;
沿着所述开口的侧壁和底部在所述硅衬底上形成绝缘结构;
在所述绝缘结构上形成导电层,以填充所述开口;
其中,在所述绝缘结构和所述硅衬底之间的第一界面具有小于5nm的峰谷高度的界面粗糙度,以及所述绝缘结构和所述导电层之间的第二界面具有小于5nm的峰谷高度的界面粗糙度。
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US20120074582A1 (en) | 2012-03-29 |
US9087878B2 (en) | 2015-07-21 |
CN102420210B (zh) | 2014-03-26 |
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